JP2718050B2 - Intermediate repeater - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used in the field of digital transmission communication.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate repeater in a digital transmission system, and particularly to a signal switching means for switching a transmission signal to an intermediate repeater of a lower station to a fixed pulse pattern signal generated from the inside of the intermediate repeater when an input signal abnormality occurs. And an intermediate repeater having:

〔Overview〕

The present invention provides an intermediate repeater that switches an output signal to a internally generated fixed pulse pattern signal when an abnormality occurs in an input signal from a transmission line, and outputs the output signal to a phase of a clock extracted from the input signal. The internal clock signal is generated based on the output signal of a phase-locked oscillator that oscillates in synchronization, the phase of the fixed pulse pattern signal is phase-synchronized with the frame of the input signal, and a frame synchronization bit signal is output to the output signal. By inserting an error, even if an abnormality occurs in the input signal and the output signal is switched back and forth, a frame synchronization bit signal can be transmitted regardless of that, and the subsequent and subsequent faulty relay sections It is intended to sufficiently prevent the influence of the fault from spreading to the intermediate repeater.

[Conventional technology]

Conventionally, this type of intermediate repeater uses a surplus bit of a transmission line code sent from a terminal repeater to branch a supervisory control signal and insert monitoring information. It has a pseudo-pattern generator inside and generates a clock signal based on a built-in oscillator separately from the clock signal for retiming in the intermediate repeater extracted from the input signal. If the input signal is lost or frame synchronization is lost due to the failure of the transmission path, the failure of the transmission path disconnection does not spread to the relay section located after the failure relay section.
Transmission by a clock signal generated based on the oscillator built in the intermediate repeater so that transfer of fault information in the faulty relay section and monitoring and control of the relay section in a normal state can be performed. The system switched to sending a fixed pulse pattern signal (hereinafter referred to as AIS signal) that is asynchronous with the input signal from the road.

Also, when the transmission path failure is restored, the intermediate repeater switches the output signal back from the AIS signal to the main line signal received from the transmission path, but this achieves frame synchronization of the input signal after the restoration of the failure, and It is performed after the bit error rate has recovered to a certain extent, and at this time, in order to switch back after confirming that the input signal has recovered more reliably, that is, the input signal from the transmission path fluctuates near the break, Alternatively, in order to prevent the signal switching and switching back from being repeated due to fluctuations in the bit error rate, a protection time Tg is provided when switching back the signal. In other words, once a failure in the transmission path has occurred and the output signal of the intermediate repeater is switched to the AIS signal, even if the failure is restored and the signal is re-input and frame synchronization is achieved, the switching back of the output signal is immediately performed. Not performed, switch back only if the failure does not reoccur within a certain protection time Tg, and the code error rate of the re-input signal is not abnormal,
If the failure reoccurs within the protection time Tg, or if the code error rate of the re-input signal is found to be abnormal, the failback is suspended until the reoccurrence is restored.

[Problems to be solved by the invention]

In the signal switching method of the conventional intermediate repeater described above, when an input signal is interrupted due to a transmission line disconnection failure, the input signal is simultaneously disconnected in all intermediate repeaters after the failure relay section, and the transmission of each intermediate repeater is performed. Signal is AI by built-in oscillator
The signal is switched to the S signal, and the intermediate repeater in the faulty relay section recovers from the fault until the re-input signal is reliably recovered.
Although the AIS signal continues to be transmitted, the intermediate repeater in a normal relay section thereafter receives the AIS signal generated from inside the intermediate repeater of one higher station, restores frame synchronization, and obtains the protection time Tg. AI that occurred inside the intermediate relay
It was sent to the lower station instead of the S signal.

Therefore, the intermediate repeater in the faulty relay section is defined as an intermediate repeater (1), and the intermediate repeaters connected thereafter are sequentially arranged as the intermediate repeater (2), the intermediate repeater (3), the intermediate repeater (4),
..., the intermediate repeater (2) replaces the AIS signal transmitted from the intermediate repeater (1) with the AIS signal generated from the inside of the intermediate repeater and transmits the AIS signal as described above. I need it. Actually (synchronization recovery time) + (backward protection time)
+ Tg, but the normal protection time Tg is (synchronization recovery time) +
Since the time is set to be sufficiently longer than the (backward protection time), (synchronization recovery time) + (backward protection time) can be ignored.

However, in the intermediate repeater (3), the input signal is interrupted after the occurrence of the fault, and the AIS signal is transmitted from the own intermediate repeater (3) and the AIS generated from the inside of the intermediate repeater (2).
Tg is required to receive the signal and transmit the received AIS signal with frame synchronization as in the case of the intermediate repeater (2), but the transmission signal is generated from inside the intermediate repeater (2).
At the same time as switching back to the AIS signal, the intermediate repeater (2) switches the transmission signal from the AIS signal generated from inside the intermediate repeater to the AIS signal received from the intermediate repeater (1). Internally generated with the input signal from
Since it is asynchronous with the AIS signal, frame synchronization is lost in the intermediate repeater (3), and the transmission signal is switched to the AIS signal from the inside of the intermediate repeater, and the intermediate repeater (1) receives the signal from the intermediate repeater (1). It takes an additional Tg time to transmit the AIS signal to the transmission line with frame synchronization.

Therefore, in the intermediate repeater (3), it takes 2Tg time to transmit the AIS signal from the intermediate repeater (1) to the transmission line due to the occurrence of a failure. The same applies to the following intermediate repeaters (4), (5),..., And the intermediate repeaters (n) (n =
In (2, 3, 4,...), Approximately (n-1) Tg from when the input signal is cut off until the AIS signal transmitted from the intermediate repeater (1) in the faulty relay section is received and transmitted. (N = 2, 3, 4, 5,...).

The normal protection time Tg is set to a sufficiently long time as compared with the frame synchronization recovery time and the frame synchronization protection time. Therefore, when n is a certain value or more, (n-1) Tg is a sufficiently long time.

Therefore, although the AIS signal is sent when a failure occurs because the fault in the faulty relay section does not spread to the subsequent relay section in the first place, the fault spreads transiently and the AIS signal is received from the faulty relay section. If there are n relay sections up to the end station repeater, the switching of the (n-1) Tg time signal and the switching back are repeated, and the transmission path becomes unstable, and the quality of the monitoring information deteriorates during this time. And the transfer of the fault information in the faulty relay section is delayed.

The object of the present invention is to eliminate the disadvantages mentioned above,
Even if the transmission path is interrupted, in the intermediate repeater after the faulty relay section, the fault will not spread and the input signal will not be lost or the frame synchronization will not be lost. It is an object of the present invention to provide an intermediate repeater having means capable of promptly searching for the information and transmitting the monitoring information of a normal relay section without interruption.

[Means for solving the problem]

The present invention is cascadedly connected to a transmission path, monitors an input signal from the transmission path, and when an input signal is disconnected or out of frame synchronization occurs, an output signal is generated internally by a fixed pulse pattern signal. In the intermediate repeater for switching and outputting, a receiving circuit for reproducing and outputting the input signal and also for self-extracting the clock signal and monitoring the disconnection of the input signal, and inputting the clock signal self-extracted from the input signal, A phase-locked oscillator that generates an internal clock signal in synchronism with the phase and generates an internal clock signal when the input signal is disconnected, and the input signal is synchronized with the internal clock signal to cause a frame loss of synchronization. A frame synchronization circuit that outputs a frame synchronization bit signal while maintaining the phase before the loss of synchronization, and a frame of the fixed pulse pattern signal. A fixed pulse pattern signal generation circuit that is generated in phase synchronization with the frame of the input signal by the frame synchronization bit signal, and a code error detection circuit that monitors a code error rate of a reproduced signal of the input signal and detects loss of frame synchronization. A signal switching circuit for switching the fixed pulse pattern signal to the fixed pulse pattern signal in place of the reproduction signal of the input signal upon detection of the input signal disconnection or loss of frame synchronization, and an output signal of the intermediate repeater to the transmission line A synchronization bit insertion circuit that inserts the frame synchronization bit signal with the frame synchronization bit signal, and by detecting the input signal disconnection or loss of frame synchronization, controls the signal switching circuit to switch to the fixed pulse pattern signal, In the above-mentioned code error detection circuit, the input signal is cut or the code error after the frame synchronization recovery. When the rate is restored to a predetermined value, characterized in that the fixed pulse pattern signal with said signal switching circuit and a signal switching control circuit for switching back to the playback signal of the input signal.

[Action]

The phase-locked oscillator oscillates with a clock signal that is self-extracted from an input signal and outputs an internal clock signal. This oscillation oscillates at the pull-in frequency in synchronization with the phase of the clock signal when an input signal is being input, and continues to oscillate at the free-running frequency when the input signal is cut off. The pull-in frequency and the free-running frequency are on the order of several ppm, and the transition is sufficiently slow with respect to the transmission speed. The frame synchronization means synchronizes the input signal with the internal clock signal to generate a frame synchronization bit signal, and the fixed pulse pattern signal generation means converts the AIS signal frame to the input signal frame by the frame synchronization bit signal. The AIS signal is generated by phase synchronization, and the synchronization bit insertion means inserts the phase synchronization bit signal into the output signal from the repeater and transmits the signal.

Therefore, even if an abnormality occurs in the input signal and the switching back of the output signal is performed, a frame synchronization bit signal can be transmitted irrespective of that, and the propagation of a failure from the failure relay section to the intermediate repeater transitioning. It is possible to sufficiently prevent it.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a main part of one embodiment of the present invention.

In this embodiment, a phase-locked oscillation circuit (PLO) 2 that receives a clock signal 101 self-extracted from an input signal 113, oscillates in synchronization with the phase thereof, and outputs a PLO output signal 102 as an internal clock signal. Receives the input signal 113 from the transmission line, outputs the clock signal 101, and outputs the PLO output signal 10
A receiving circuit 1 for outputting a reproduction signal 103 in accordance with 2 and further outputting an input disconnection signal 105 indicating input disconnection information, and a PLO output signal
102 and the reproduction signal 103 are input and the frame synchronization bit is tracked to synchronize the frame and the frame synchronization bit signal 10
7, a frame synchronization circuit 3 as a frame synchronization means for outputting a surplus bit designation signal 104 indicating the position of the surplus bits, a PLO output signal 102 and a reproduction signal.
A code error detection circuit 4 which inputs 103 to detect out-of-synchronization and code errors and outputs an abnormal signal 106, and a PLO output signal 102, a reproduction signal 103 and a surplus bit designation signal 104 to input a monitoring control signal 111 A signal branching circuit 5 for branching and outputting from the reproduction signal 103, an AIS signal generating circuit 6 for receiving and synchronizing the frame synchronization bit signal 107 and generating an AIS signal 114, and an input disconnection signal 105 and an abnormal signal 106 A signal switching control circuit 7 for outputting a signal switching control signal 108, a PLO output signal 102, a reproduction signal 103, and an AIS signal 114.
And a signal switching circuit 8 for switching to any one by the switching control signal 108 and outputting it as an output signal 109, and an output signal 109 and a PLO output signal 102, and according to a surplus bit designation signal 104 and a frame synchronization signal 107, A signal insertion circuit 9 as a synchronization bit insertion means for inserting a monitoring signal 112, further inserting a frame synchronization bit signal 107 and outputting it as an output signal 110, and inputting an output signal 110 and a PLO output signal 102 and outputting an output signal 115 And a transmission circuit 10 that outputs the signal to the transmission path.

The feature of the present invention is that the phase-locked oscillation circuit 2 shown in FIG.
And a frame synchronization circuit 3, an AIS signal generation circuit 6 for generating an AIS signal in synchronization with the frame synchronization bit signal, and a signal insertion circuit 9.

 Next, the operation of the present embodiment will be described.

The receiving circuit 1 inputs a clock signal 101, which is self-timed extracted from an input signal 113 received from the transmission line, to a phase-locked oscillation circuit 2, and oscillates in the phase-locked oscillation circuit 2 in synchronization with the phase of the input clock signal 101. Output PLO
Based on the output signal 102, the input signal 113 is identified and reproduced, and a reproduced signal 103 is output. The frame synchronization circuit 3 receives the reproduction signal 103 from the reception circuit 1, tracks the frame synchronization bits, synchronizes the frames, outputs a frame synchronization bit signal 107, and simultaneously outputs a surplus bit designation signal indicating the position of the surplus bits. Outputs 104.

The code error detection circuit 4 detects out-of-synchronization and a code error, monitors the code error rate, and outputs an abnormal signal 106.
The signal branching circuit 5 includes a reproduction signal 103 from the receiving circuit 1 and
Upon receiving the PLO output signal 102 from the phase locked oscillation circuit 2 and the surplus bit designation signal 104 from the frame synchronization circuit 3, the monitor control signal 111 is branched. The AIS signal generation circuit 6
An AIS signal 114 synchronized with the input signal 113 is generated according to the output signal 102 and the frame synchronization bit signal 107 and output to the signal switching circuit 8. Here, the frame synchronization bit 107 is
Even if the frame synchronization of the input signal 113 is lost, the phase before the frame synchronization is lost is maintained.

The signal switching control circuit 7 receives the input signal 113 from the receiving circuit 1.
When the input disconnection signal 105 indicating whether or not the input signal is disconnected and the abnormal signal 106 from the code error detection circuit 4 are received, when the input signal disconnection or frame synchronization is lost, the reproduction signal 103 is switched to the AIS signal 114, After recovery from signal loss or frame synchronization, a protection time Tg is provided, and after confirming that the code error rate has also recovered to some extent, switching to control the signal switching circuit 8 to switch back to the reproduced signal 103 received and reproduced from the transmission path. The control signal 108 is output. The signal switching circuit 8 switches between the AIS signal 114 and the reproduction signal 103 in response to the input of the switching control signal 108, and outputs an output signal 109. The signal insertion circuit 9 inserts the monitoring signal 112 into the surplus bits according to the surplus bit designation signal 104 received from the frame synchronization circuit 3 to the output signal 109 received from the signal switching circuit 8, and further receives the monitoring signal 112 from the frame synchronization circuit 3. The frame synchronization bit is inserted according to the frame synchronization bit signal 107. Then, the output signal 1 into which the monitoring signal 112 is inserted and the frame synchronization bit signal 107 is reinserted
10 is transmitted from the transmission circuit 10 to the transmission line as an output signal 115.

In the present embodiment, the phase-locked oscillation circuit 2 oscillates in the receiving circuit 1 in synchronization with the phase of the clock signal 101 extracted from the input signal 113 from the transmission line (pull-in frequency), but the input signal 113 is interrupted. Then, it shifts to the natural oscillation state (free-running frequency), the difference between the pull-in frequency and the free-running frequency is about a few ppm, and the transition from the pull-in frequency to the free-running frequency is sufficient compared to the transmission speed Slow down. Therefore, PLO which is the output of the phase locked oscillator 2
The output signal 102 is used as the internal clock signal of the repeater and the input signal 113 is configured as if it were normal.

The AIS signal 114 is synchronized by the AIS signal generation circuit 6 so that the phase of the input signal 113 matches the phase of the frame synchronization bit signal 107, and the output signal 109 which is the output of the signal switching circuit 8 is transmitted according to the state of the input signal 113. Input signal 113 or AIS from
Since the signal is switched to the signal 114, regardless of the content of the output signal 109 of the signal switching circuit 8, the phase of the frame synchronization bit matches before and after switching, and the phase of the frame pattern also matches.

In the signal insertion circuit 9, the output signal 109 of the signal switching circuit 8 may be the reproduced signal 103 input from the transmission path and reproduced, the AIS signal 114, or the frame synchronization bit from the frame synchronization circuit 3. Signal 107 and surplus bit designation signal 104
In response to this, the frame synchronization bit is reinserted and the monitoring signal 112 is inserted into the surplus bits, the input signal 113 to the receiving circuit 1 is cut off, the reproduction signal 103 is cut off, and the AIS signal 114 is cut off.
In the transitional state before switching to
Even if the output signal 109 is interrupted, the monitor signal 112 added to the frame synchronization bit and the surplus bit is transmitted, and the phases of the two coincide before and after the signal switching.

〔The invention's effect〕

As described above, according to the present invention, even if the input signal is cut off and the output signal is switched to the AIS signal, and then the input signal is re-input and then switched back after the frame synchronization recovery protection time,
In the meantime, the frame synchronization bit can be transmitted regardless of switching and switching back of the signal, so that the frame synchronization is maintained on the receiving side even if the content of the input signal is changed, and the frame synchronization is not lost. Even if a failure due to transmission path disconnection occurs, in the intermediate repeater beyond the relay section where the failure has occurred, the failure does not spread and input signal disconnection or frame synchronization loss does not occur, only the signal content is switched to AIS signal In addition to being able to quickly search for a generated relay section, the monitoring information of a normal relay section can be transferred without an instantaneous interruption, and the effect of the failure can be prevented from spreading to the normal relay section.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Reception circuit, 2 ... Phase synchronous oscillation circuit, 3 ... Frame synchronous circuit, 4 ... Code error detection circuit, 5 ... Signal branch circuit, 6 ... AIS signal generation circuit, 7 ... Signal switching control Circuit 8, Signal switching circuit 9, Signal insertion circuit 10,
... transmitting circuit, 101 ... clock signal, 102 ... PLO output signal, 103 ... reproduction signal, 104 ... surplus bit designation signal, 10
5: Input disconnection signal, 106: Abnormal signal, 107: Frame synchronization bit signal, 108: Switching control signal, 109: Output signal (of signal switching circuit), 110: Output of signal insertion circuit Signal, 111: monitor control signal, 112: monitor signal, 113
…… Input signal, 114… AIS signal, 115 …… Output signal.

Claims (1)

(57) [Claims] 1. A fixed pulse pattern signal which is cascaded to a transmission line, monitors an input signal from the transmission line, and internally generates an output signal when an input signal is disconnected or frame synchronization is lost. A receiving circuit (1) that reproduces and outputs the input signal, self-extracts the clock signal, and monitors the disconnection of the input signal, and outputs the self-extracted clock signal from the input signal. A phase-locked oscillator (2) for generating an internal clock signal in synchronism with the input phase and automatically generating an internal clock signal when the input signal is interrupted; and synchronizing the input signal with the internal clock signal. A frame synchronization circuit (3) for outputting a frame synchronization bit signal while maintaining the phase before the synchronization loss when the frame synchronization is lost; A fixed pulse pattern signal generating circuit for generating a frame of a scan pattern signal in phase with the frame of the input signal by the frame synchronization bit signal (6)
A code error detection circuit (4) for monitoring a code error rate of a reproduced signal of the input signal and detecting frame loss of synchronization; and detecting the fixed pulse pattern signal by detecting the input signal disconnection or frame loss of synchronization. A signal switching circuit (8) for switching to the fixed pulse pattern signal instead of a reproduction signal; and a synchronization bit insertion for inserting the frame synchronization bit signal into the output signal of the intermediate repeater to the transmission line using the frame synchronization bit signal. A circuit (9) and the detection of the input signal disconnection or the loss of frame synchronization,
The signal switching circuit is controlled to switch to the fixed pulse pattern signal, and thereafter, when the input signal is cut off by the code error detection circuit or the code error rate recovers to a predetermined value after frame synchronization recovery, the signal switching circuit fixes the fixed pulse pattern signal. A signal switching control circuit for switching a pulse pattern signal back to a reproduction signal of the input signal.