JPH0479436A - Line switching system - Google Patents

Abstract

PURPOSE:To shorten the line switching time required at the time when a current line is so degraded that hitless switching is impossible by switching the discrimination period of a phase coincidence discriminating circuit from the period of the output signal of a frequency divider to the period of the output signal of a voltage controlled oscillator at the time of deviation of frame synchronism. CONSTITUTION:A switch 9 is added to a conventional example to constitute a system. When alarm signals Aa and Ab which frame synchronizing circuits la and 1b output for deviation of frame synchronism are not inputted, the switch 9 outputs the output signal of a frequency divider 6 to a phase coincidence discriminating circuit 7; but when the alarm signal Aa or Ab is inputted, the switch 9 outputs the output signal of a voltage controlled oscillator 5 to the phase coincidence discriminating circuit 7. When the transmission quality of the current line is degraded, a line switching control circuit 8 starts the line switching operation and sends a switching control signal to the transmission end to make the current line and a standby line parallel in the transmission end. Thus, line switching is completed in a short time when the current line is so deteriorated that hitless line switching is impossible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line switching system, and more particularly to a line switching system for switching between a working line and a protection line in a digital wireless communication system at a receiving end.

[Conventional technology]

In a digital wireless communication system that has a protection line in addition to the working line, when the transmission quality of the working line deteriorates, the working line and the protection line are connected in parallel at the sending end and the data signal to be transmitted is transmitted in parallel by both lines. Then, at the receiving end, the working line is switched to the protection line.

By the way, there is a difference in propagation delay time between the working line and the protection line, and this propagation delay time difference also changes over time. If the propagation delay time difference becomes larger than the time slot length of the data signal, if the two data signals transmitted on both lines are switched directly at the receiving end, bit duplication or missing bits will occur, resulting in bit errors. occurs.

In order to avoid this bit error, a hitless line switching system is known in which the phases of both data signals are compared at the receiving end, and if the phase difference is greater than one time slot length, the phase difference is corrected, and then the line is switched.

FIG. 2 is a block diagram showing an example of such a conventional line switching system.

The data signal transmitted on the working line and the data signal transmitted on the protection line are separated by frame synchronization circuits 1a and 1.
b and the buffer circuit 3 via the separation circuits 2a and 2b.
Enter. The buffer circuit 3 is controlled by the line switching control circuit 8 and corrects the phase difference by trial and error so that the phase difference between the two human input data signals is one time slot or less.

The phase match determination circuit 7 determines whether the phase difference between both data signals output from the buffer circuit 3 is one time slot or less. The line switching control circuit 8 causes the buffer circuit 3 to continue trial and error until the determination result shows that the phases match. When the determination result shows that the phases match, the line switching control circuit 8 switches the switching circuit 4, and the output of the switching circuit 4 is switched from the data signal via the working line to the data signal via the protection line.

If the working line is disconnected before the above-mentioned line switching operation is completed, the data signal via the working line becomes meaningless, and hitless line switching becomes impossible. In this case, the determination result of the phase match determination circuit 7 remains as a phase mismatch, so
The line switching control circuit 8 forcibly switches the switching circuit 4 after the buffer circuit 3 has assumed all possible states through trial and error.

Incidentally, in order for the phase match determination circuit 7 to obtain a determination result, a certain amount of time longer than one time slot of the data signal is required. Therefore, the frequency of the output signal of the voltage controlled oscillator 5, which is phase-synchronized with the clock of the data signal output by the switching circuit 4, is divided by the frequency divider 6, and the phase match determination circuit 7 uses the period of the output signal of the frequency divider 6. G is controlled so that it makes a judgment action.

[Problem to be solved by the invention]

The conventional line switching method described above is capable of determining phase matching even in a situation where the judgment result of the phase matching judgment circuit 7 remains as a phase mismatch due to disconnection of the working line or the like before the line switching operation is completed. The circuit 7 repeats the judgment operation in the period of the output signal of the frequency divider 6, and changes the states that the buffer circuit 3 can take one by one in a trial and error manner in the period of this judgment operation, and takes all the possible states. Since the switching circuit 4 is then switched, there is a drawback that it takes a long time to switch the line in a situation where hitless line switching is not possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line switching system that can complete line switching in a short time when a working line has deteriorated to such an extent that hitless line switching is impossible.

[Means to solve the problem]

[Means for Solving the Problem] The line switching system of the present invention establishes frame synchronization for each of two data signals transmitted over two wireless lines that are in a redundant relationship with each other, and generates an alarm signal when frame synchronization is lost. and at least one of the two data signals is made variable in order to correct a phase difference between the two data signals due to a propagation delay time difference between the two wireless lines. a buffer circuit that delays the data signal; a switching circuit that selects and outputs one of the two data signals after the phase difference has been corrected by the buffer circuit; A voltage controlled oscillator that synchronizes, a frequency divider that divides the output of the voltage controlled oscillator, and when the frame synchronization circuit outputs the alarm signal, selects and outputs the output signal of the voltage controlled oscillator, and outputs the output signal of the voltage controlled oscillator. When the signal is not being output, the switch selects and outputs the output signal of the frequency divider, and the switch checks whether the phases of the two data signals match after correcting the phase difference. A phase matching determination circuit that determines based on the period of the output signal, and when this phase matching determining circuit determines that the phases do not match, the delay of the buffer circuit is controlled in a trial and error manner, and when phase matching cannot be achieved through this trial and error, the phase matching is determined. and a line switching control circuit that controls selection of the switching circuit when it is determined that the switching circuit is selected.

Further, the line switching system of the present invention includes two separation circuits for separating additional bits multiplexed into the two data signals, and these separation circuits are connected to the two frame synchronization circuits and the buffer circuit. It may also be configured by being placed between the two.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment shown in FIG. 1 is constructed by adding a switch 9 to the conventional example shown in FIG.

The switch 9 outputs the output signal of the frequency divider 6 to the phase match determination circuit 7 when neither of the alarm signals Aa and Ab, which are output when the frame synchronization circuits 1a and lb are out of frame synchronization, is input, and outputs the alarm signal. When Aa or Ab is input, the output signal of the voltage controlled oscillator 5 is output to the phase match determination circuit 7.

When the transmission quality of the working line deteriorates, the line switching control circuit 8
starts the line switching operation, and first sends a switching control signal to the sending end (not shown) to connect the working line and the protection line in parallel at the sending end.

As a result, data signals to be transmitted are transmitted in parallel to the receiving end on both the working and protection lines. The two data signals transmitted on these two lines are multiplexed with wireless transmission control signals such as switching control signals and other input pits.
The frame synchronization bits of the frames for this multiplexing are also multiplexed.

The frame synchronization circuits 1, a, 1, and b establish frame synchronization by detecting frame synchronization bits from each of the data signals 2-] transmitted on both the working and protection lines. The separation circuits 2a, 2b are frame synchronization circuits 1, a,
Based on the timing of the frame synchronization bit detected in steps 1 and b, the additional bits and frame synchronization bits 1 to 1 are separated from both transmitted data signals, and only the data signal that should originally be transmitted is output. The frame synchronization circuits 1a, 1b output alarm signals Aa, Ab when the quality of the input data signal deteriorates and frame synchronization cannot be established. At this time, the separation circuits 2a and 2b cannot separate additional bits and the like.

When the line switching operation is started and the transmission quality of the working line (and protection line) has not deteriorated to the extent that frame synchronization is lost, the alarm signals Aa and Ab are not input to the switch 9, and the phase match determination circuit 7 The output signal of the frequency divider 6 is input to the frequency divider 6.

In this state, the embodiment shown in FIG. 1 operates in the same manner as the conventional example shown in FIG. 2, and performs hitless line switching. That is, in this state, the phase match determination circuit 7 can normally determine phase match/mismatch, and the buffer circuit 3 can always compensate for the propagation delay time difference between the working and backup lines. Since the buffer times fi8
3. Through the trial and error operation performed in the loop of the 76-time line switching operation path 8 of the phase match determination circuit, the phases of both data signals output from the buffer circuit 3 match. The line switching control circuit 8 confirms that the phases of both data signals match, and the switching circuit 4
The output is switched from the data signal within the working line to the data signal via the protection line, from HIRA 1 to RES.

=9 0 Now, if the transmission quality of the working line begins to deteriorate or progresses before the line switching operation is completed, and the frame synchronization on the working line side is lost, the alarm signal Aa or Ab will be input to the switch 9. , the output signal of the voltage controlled oscillator 5 is directly input to the phase match determination circuit 7.

In this state, there are many transmission errors in the data signal via the working line, and the judgment result of the phase match judgment circuit 7 remains as a phase mismatch, making hitless line switching impossible. but,
In this case, the period at which the phase matching judgment circuit 7 makes a judgment is the period of the output signal of the voltage controlled oscillator 5, and the frequency divider 6
This is much shorter than the period of the determination made using the period of the output signal. Therefore, the line switching control circuit 8 causes the buffer circuit 3 to take on possible states one after another in this short cycle, and after taking all possible states, forcibly switches the switching circuit 4.

Comparing the line switching time in the case where hitless line switching is not possible between the embodiment shown in FIG. 1 and the conventional example shown in FIG. 2, the line switching time in the embodiment shown in FIG. Assuming that n, the line switching time is reduced to 1/n of the line switching time in the conventional example shown in FIG.

〔Effect of the invention〕

As explained above, the present invention has the advantage of switching the judgment period of the phase match judgment circuit from the period of the output signal of the frequency divider to the period of the output signal of the voltage controlled oscillator when frame synchronization is lost, thereby eliminating the need for conventional line switching methods. While maintaining the hitless switching function, it is possible to shorten the line switching time required when the working line does not deteriorate to the point where hitless switching is impossible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional line switching system. la, lb...frame synchronization circuit, 2a, 2b...
Separation circuit, 3... Buffer circuit, 4... Switching circuit, 5... Voltage controlled oscillator, 6... Frequency divider, 7...
Phase match determination circuit, 8... line switching control circuit, 9...
·switch.

Claims (1)

[Claims] 1. Two frame synchronization circuits that establish frame synchronization for each of two data signals transmitted over two wireless lines that are in a redundant relationship with each other and output an alarm signal when frame synchronization is lost. , a buffer circuit that variably delays at least one of the two data signals in order to correct a phase difference between the two data signals due to a propagation delay time difference between the two wireless lines; and this buffer circuit. a switching circuit that selects and outputs one of the two data signals after correcting the phase difference, a voltage controlled oscillator whose phase is synchronized with the clock of the data signal outputted by the switching circuit, and this voltage controlled oscillator. a frequency divider that divides the frequency of the output of the voltage controlled oscillator when the frame synchronization circuit outputs the alarm signal, and selects and outputs the output signal of the voltage controlled oscillator when the alarm signal is not output, a switch that selects and outputs an output signal; a phase matching determination circuit that determines whether the phases of the two data signals match after correcting the phase difference based on the period of the output signal of the switch; A line that controls the delay of the buffer circuit in a trial and error manner when this phase match determination circuit determines that the phases do not match, and controls the selection of the switching circuit when phase matching cannot be achieved through this trial and error, and when it determines that the phases match. A line switching method characterized by comprising a switching control circuit. 2. It includes two separation circuits for separating additional bits multiplexed into the two data signals, and these separation circuits are arranged between the two frame synchronization circuits and the buffer circuit. 2. The line switching system according to claim 1, wherein: