JPH1013226A - Clock-generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an output signal of a VCXO from being unstable, when an another reference clock signal is selected. SOLUTION: A clock latch circuit 4 detects a phase of a reference clock signal, selected by a selection circuit 1 for each prescribed period and generates a clock signal S4, synchronously with the detected phase. A selection circuit 3 is operated, in response to a switching signal S3 outputted by a switching control circuit 6, and selects the reference clock signal selected by the selection circuit 1 or the clock signal S4, outputted from the clock latch circuit 4. A phase coincidence detection circuit 5 outputs a detection signal C2 when the phase of the output signal from the selection circuit 1 is coincident with the phase of the output signal S4 of the clock latch circuit 4. The changeover control circuit 6 generates the switching signal C3, to allow the selection circuit 3 to select the clock signal S4, when the selection circuit 1 selects other reference clock signal and to select the output signal of the selection circuit 1, when a phase coincidence detection signal C2 is received.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generating circuit for generating a signal synchronized with a reference clock signal.
In particular, the present invention relates to a clock generation circuit for selecting a plurality of reference clock signals.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional clock generation circuit. Here, the selection circuit 1 is controlled by the clock disconnection detection circuit 2 to control the plurality of reference clock signals S1.
To S3. Clock loss detection circuit 2
Controls the selection circuit 1 by detecting a clock loss of a plurality of input reference clock signals S1 to S3. That is, if the reference clock signal selected by the selection circuit 1 is cut off, control is performed so that another reference clock signal is selected in accordance with a predetermined priority order.

The phase comparator 7, the filter 8, and the VCXO
(Voltage controlled crystal oscillation circuit) 9 and a phase control loop (PL
L), and generates an output signal So that is dependently synchronized with the reference clock signal selected by the selection circuit 1.

Now, the selection circuit 1 receives the reference clock signal S1
And if the VCXO 9 is outputting the output signal So synchronized with the reference clock signal S1 and the reference clock signal S1 fails, the clock loss detection circuit 2 detects the clock loss of the reference clock signal S1. Then, the selection circuit 1 is instructed to switch from the reference clock signal S1 to the normal reference clock signal S2. When the selection circuit 1 selects the reference clock signal S2, the VCXO 9 outputs an output signal So that is dependently synchronized with the reference clock signal S2.

[0005]

In the conventional clock generating circuit described above, when a failure occurs in the reference clock signal which has been subjected to subordinate synchronization and is switched to another reference clock signal, the clock signal with the switched clock signal is output. If the phase difference is large, the output signal of the VCXO becomes unstable during the period until the synchronization, and there is a problem that the main signal in the device is affected.

An object of the present invention is to prevent the output signal of the VCXO from becoming unstable when the reference clock signal is switched.

[0007]

SUMMARY OF THE INVENTION A clock generation circuit according to the present invention prevents a sharp phase difference from occurring when a reference clock signal is switched. Specifically, in a clock generation circuit that generates a signal dependently synchronized with a selected reference clock signal among the plurality of reference clock signals, one of the plurality of reference clock signals is selected according to a selection signal. First selecting means, clock holding means for detecting and storing the phase of the reference clock signal selected by the first selecting means at regular intervals, and generating a clock signal synchronized with the detected phase; A second selection unit that selects one of a reference clock signal selected by the first selection unit and a clock signal output by the clock holding unit in accordance with a switching signal; and a reference clock selected by the first selection unit. A phase match detection unit that outputs a detection signal when a phase match is detected by comparing a signal with a clock signal output by the clock holding unit; and the selection signal Comprising a switching control means for generating said switching signal based on the preliminary detection signal, and a phase synchronization means for generating a signal to slave synchronization with a clock signal the second selecting means has selected.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same components as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals.

The selection circuit 1 selects one of a plurality of reference clock signals S1 to S3 under the control of a selection signal C1 sent from the clock disconnection detection circuit 2. Note that the number of input reference clock signals may be plural.

The clock loss detection circuit 2 detects a clock loss of a plurality of input reference clock signals S1 to S3, and sends a selection signal C1 to the selection circuit 1 according to the detection result.
That is, when the reference clock signal selected by the selection circuit 1 is cut off, another normal reference clock signal is selected. Further, a phase comparison circuit 7 and a filter 8
And a VCXO (voltage controlled crystal oscillation circuit) 9 to form a phase control loop (PLL), and generate an output signal So that is dependently synchronized with the clock signal selected by the selection circuits 1 and 3.

In order to prevent the output signal So from becoming unstable due to the switching of the reference clock signal, a selection circuit 3, a clock holding circuit 4, a phase coincidence detection circuit 5, and a switching control circuit 6 are provided.

The selection circuit 3 has contacts d and e, and contacts d and e according to a switching signal C3 output from the switching control circuit 6.
Select one of The reference clock signal selected by the selection circuit 1 is input to the contact d, and the clock signal S output from the clock holding circuit 4 is applied to the contact e.
4 has been entered.

The clock holding circuit 4 detects and stores the phase of the reference clock signal selected by the selection circuit 1 at regular intervals, and generates a clock signal S4 synchronized with the detected phase. As a phase detection method, for example, the timing of a reference clock signal is measured by a sampling pulse.

The phase match detection circuit 5 compares the reference clock signal selected by the selection circuit 1 with the clock signal S4 output from the clock holding circuit 4, and outputs a detection signal C2 when the phases match. The switching control circuit 6 generates a switching signal C3 based on the selection signal C1 output from the clock loss detection circuit 2 and the detection signal C2 output from the phase coincidence detection circuit 5, and sends it to the selection circuit 3.

Next, the operation of the switching control circuit 6 will be described.

For example, when the selection circuit 1 receives the reference clock signal S
1 (contact a), the selection circuit 3 selects the output signal S1 (contact d) of the selection circuit 1, and the VCXO 9 outputs an output signal So that is dependently synchronized with the reference clock signal S1.

Now, as shown in FIG. 2, since the clock cutoff of the reference clock signal S1 has occurred, when the clock cutoff detection circuit 2 causes the selection circuit 1 to select the reference clock signal S2 (contact b), the switching control is performed. The circuit 6 receives the selection signal C1 of the clock loss detection circuit 2 and immediately receives the selection signal C1.
Is switched from the contact d to the contact e. That is, the clock signal S4 output from the clock holding circuit 4 is sent to the phase comparison circuit 7.

The phase of the clock signal S4 at the beginning of the switching matches the phase of the reference clock signal S1, and the output of the phase comparison circuit 7 does not fluctuate rapidly.
Works stably.

Thereafter, when the phase coincidence detection circuit 5 detects the phase coincidence between the clock signal S4 and the reference clock signal S2, the switching control circuit 6 receives the detection signal C2 indicating the phase coincidence and immediately switches the contact of the selection circuit 3. Is switched from the contact e to the contact d. That is, the reference clock signal S2 selected by the selection circuit 1 is sent to the phase comparison circuit 7. Even at the time of this switching, since the output of the phase comparison circuit 7 does not fluctuate rapidly, the VCXO 9 can generate the output signal So that is dependently synchronized with the reference clock signal S2 while maintaining a stable state.

The same effect can be obtained by using a PLL having a low following speed in place of the clock holding circuit 4.

[0022]

As described above, according to the present invention, when the reference clock signal is switched, a sharp phase difference is prevented from being generated, whereby the VCXO is maintained in a stable state, and the output signal is not changed. Stability can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of a switching control circuit 6 shown in FIG.

FIG. 3 is a block diagram illustrating an example of a conventional clock generation circuit.

[Explanation of symbols]

 1, 3 selection circuit 2 clock disconnection detection circuit 4 clock holding circuit 5 phase coincidence detection circuit 6 switching control circuit 7 phase comparison circuit 9 VCXO (voltage controlled crystal oscillation circuit) C1 selection signal C2 detection signal C3 switching signal S1 to S3 Reference clock Signal S4 Clock signal So Output signal

Claims (2)

[Claims] 1. A clock generation circuit for generating a signal dependently synchronized with a selected reference clock signal among a plurality of reference clock signals, wherein one of the plurality of reference clock signals is selected according to a selection signal. First selecting means;
A clock holding means for detecting and storing the phase of the reference clock signal selected by the first selecting means at regular intervals and generating a clock signal synchronized with the detected phase; A second selection unit that selects one of a reference clock signal and a clock signal output by the clock holding unit in accordance with a switching signal; and a reference clock signal selected by the first selection unit and the clock holding unit. A phase matching detection unit that compares a clock signal to be output and outputs a detection signal when phase matching is detected, a switching control unit that generates the switching signal based on the selection signal and the detection signal, And a phase synchronizing means for generating a signal which is dependently synchronized with the clock signal selected by the selecting means. 2. The switching control means selects a clock signal output from the clock holding means when the first selection means selects another reference clock signal, and the phase matching detection means determines whether the phase match is detected. 2. The clock generation circuit according to claim 1, wherein said second selection means is controlled so as to select a reference clock signal selected by said first selection means when detected.