JP4592982B2 - Clock switching circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock switching circuit, and more particularly to a clock switching circuit that switches from a first clock to a second clock when an abnormality occurs in an input clock frequency.
[0002]
[Prior art]
In a digital circuit such as a digital transmission apparatus, a clock is indispensable as an operation reference for each component in the apparatus. Therefore, if an abnormality occurs in the clock, the operation of the transmission apparatus is stopped, so a countermeasure is required. As a countermeasure, in a conventional digital transmission apparatus, for example, a redundant system in which clock inputs are doubled is generally used. When a trouble occurs in one of these dual clock circuits (active system), the clock switching circuit is used to switch to the other (non-operating system).
[0003]
Conventional examples of the clock switching circuit or related circuits are disclosed in, for example, “Synchronization signal supply device” of Japanese Patent Laid-Open No. 6-141027 and “Abnormality detection circuit of phase-locked oscillator” of Japanese Patent Laid-Open No. 4-165818. Yes. The configuration of the former prior art is shown in the block diagram of FIG. This conventional synchronizing signal supply device includes clock receiving circuits 11a and 11b, receiving clock switching circuits 12a and 12b, PLL (Phase-Locked Loop) circuits 13a and 13b, distributors 14a and 14b, and a receiving clock switching control unit 15. Is done.
[0004]
In the synchronization signal supply device shown in FIG. 4, the clock receiving circuits 11a and 11b branch and output two clock inputs CLK1 and CLK2, respectively. The reception clock switching circuits 12a and 12b switch between the two clocks CLK3a and CLK3b output from the clock reception circuits 11a and 11b. The PLL circuits 13a and 13b perform frequency conversion of the clocks CLK4a and 4b selected by the reception clock switching circuits 12a and 12b. The distributors 14a and 14b divide and distribute the output clocks CLK5a and 5b of the PLL circuits 13a and 13b. As described above, each system has a redundant system, and even if a trouble (failure) occurs in one system, the system operation is guaranteed by using the other system.
[0005]
[Problems to be solved by the invention]
It is common to perform drift / slip detection in a PLL circuit. However, the conventional drift / slip detection is prepared for detecting a failure of the PLL circuit, and assumes that no abnormality occurs in the frequency of the input clock. A failure of the PLL circuit is detected by monitoring the phase of the oscillation clock (output clock) of the PLL circuit and the input clock input to the PLL circuit. Accordingly, in the conventional circuit, when a frequency abnormality occurs in the selected clock input, the phase relationship between the oscillation clock of the PLL circuit and the clock input becomes abnormal although the PLL circuit is normal. Drift / slip is detected. Furthermore, in the redundant system of the PLL circuit, both of them select the same clock, so both PLL circuits fail, and the entire system fails even though the unselected clock input side is normal. There was a problem.
[0006]
OBJECT OF THE INVENTION
In view of the above-described problems, an object of the present invention is to provide a clock switching circuit that prevents a system failure due to a PLL circuit failure.
[0007]
[Means for Solving the Problems]
A clock switching circuit according to the present invention includes a pair of clock reception circuits, a reception clock switching circuit, a PLL circuit, and a distributor to which clocks are input, respectively, and a reception clock for switching and controlling an input clock of the reception clock switching control circuit A circuit that has a switching control unit and outputs an output clock from the distributor, and outputs a switch control signal for switching the input clock of the reception clock switching circuit based on the frequency monitoring result output from the pair of PLL circuits.
[0008]
According to a preferred embodiment of the clock switching circuit of the present invention, the switching control signal for switching the input clock of the reception clock switching circuit when both the drift / slip alarm based on the input / output clocks of the pair of PLL circuits are detected. Generate. After the switching control signal is generated, the switching control signal is held for a predetermined time. This fixed time is selected to be longer than the time for the PLL circuit to recover the drift / slip after the clock signal is switched. When a drift / slip alarm is detected from only one of the pair of PLL circuits, the input clock is held and the clock is not switched.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration and operation of a preferred embodiment of a clock switching circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0010]
FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a clock switching circuit according to the present invention. In this clock switching circuit, the same reference numerals are used for the components corresponding to the components shown in FIG. 4 for convenience of explanation. In the same manner as the conventional clock switching circuit shown in FIG. 4, the clock switching circuit includes clock reception circuits 11a and 11b, reception clock switching circuits 12a and 12b, PLL circuits 13a and 13b, distributors 14a and 14b, and reception clock switching control. The unit 15 is configured.
[0011]
In FIG. 1, clock receiving circuits 11a and 11b receive external input clocks CLK1 and CLK2, respectively. The clock reception circuits 11a and 11b output the output clocks CLK3a and CLK3b to the subsequent reception clock switching circuit 12a12b. Reception clock switching circuits 12a and 12b switch between CLK3a and CLK3b, and output clocks CLK4a and CLK4b to PLL circuits 13a and 13b, respectively. PLL circuits 13a and 13b generate clocks CLK5a and CLK5b synchronized with clocks CLK4a and CLK4b, output them to distributors 14a and 14b, and generate drift / slip alarms ALM7a and ALM7b to receive clock control circuit 15. Output. These alarms ALM7a and ALM7b are drift / slip alarm signals detected by the PLL circuits 13a and 13b. The reception clock switching control unit 15 is a switching control unit that generates a switching control signal by the ALM 7a and the ALM 7b. Distributors 14a and 14b receive clocks CLK5a and CLK5b, respectively, and generate and output distribution clocks CLK6a and CLK6b, respectively.
[0012]
In the clock switching circuit of FIG. 1, the receiving circuits 11a and 11b, the receiving clock switching circuits 12a and 12b, the PLL circuits 13a and 13b, the distributors 14a and 14b, and the receiving clock switching control unit 15 themselves are well known to those skilled in the art. Detailed configurations of these circuits are omitted.
[0013]
Next, the operation of the preferred embodiment of the clock switching circuit shown in FIG. 1 will be described. As shown in FIG. 1, the clock receiving circuits 11a and 11b receive two external input clocks CLK1 and CLK2, and generate clocks CLK3a and CLK3b distributed to the reception clock switching circuits 12a and 12b. The reception clock switching circuits 12a and 12b receive the clocks CLK3a and CLK3b, switch the clocks CLK3a and CLK3b by a switching control signal from the reception clock switching control unit 15, and supply the clocks CLK4a and CLK4b to the PLL circuits 13a and 13b. Output.
[0014]
The reception clock switching control unit 15 outputs a switching control signal to the reception clock switching circuits 12a and 12b based on the frequency drift / slip alarms ALM7a and ALM7b detected by the PLL circuits 13a and 13b. PLL circuits 13a and 13b output clocks CLK5a and CLK5b synchronized with reception clocks CLK4a and CLK4b. The PLL circuits 13a and 13b detect frequency drift / slip alarms ALM7a and ALM7b. When the frequency drift / slip alarms ALM7a and ALM7b are detected, the frequency drift / slip alarms ALM7a and ALM7b are output to the reception clock switching control unit 15. The distributors 14a and 14b distribute and output output output clocks CLK6a and CLK6b obtained by dividing the clocks CLK5a and CLK5b from the PLL circuits 13a and 13b.
[0015]
Next, the operation of the reception clock switching control unit 15 will be described with reference to the flowchart of FIG. In FIG. 2, in the initial state (step S1), the clock CLK3a is selected in the reception clock switching circuit 12. At this time, it is determined whether or not the frequency abnormality of the clock CLK3a has occurred and the frequency drift / slip alarms ALM7a and ALM7b have occurred in both PLL circuits 13a and 13b (step S2). When the frequency drift / slip alarms ALM7a and ALM7b are generated (step S2: Yes), since the clock CLK3a is currently selected, switching to the non-selected clock CLK3b is performed (step S4). However, for example, when the PLL circuit 13a fails and only the frequency drift / slip alarm ALM7a occurs (step S2: No), since the failure is only in one system, the input clock is normal and the failure of the PLL circuit 13a itself. Conceivable. Therefore, the clock CLK3a that is currently selected (that is, the selected system) is selected as it is (step S3). When switching to another system is performed in step S4 described above, the frequency drift / slip alarms ALM7a and ALM7b have not recovered immediately after the switching, and there is a possibility that extra switching will occur again. For this reason, immediately after the switching in step S4 described above, the switching control signal to the reception clock switching circuit 12 in FIG. 1 is held for a preset T1 second (step S5). The holding time (T1) is set by obtaining a value having a margin in the time until the PLL circuit 13 recovers the frequency drift / slip after the input clock is switched, for example, by experiments.
[0016]
Next, the switching operation in the reception clock switching circuit 12 shown in FIG. 1 will be described with reference to the timing chart of FIG. In the timing chart of FIG. 3, (a) shows an alarm ALM 7a, (b) shows an alarm ALM 7b, and (c) shows a clock 4. In the initial state, the clock CLK4 is in a state in which CLK3a is selected. At this time, when the drift / slip alarms ALM7a and ALM7b are generated in the PLL circuits 13a and 13b, the clock CLK4 selects the clock CLK3b. These alarms ALM7a and ALM7b are considered to have occurred for T2 seconds. Since the reception clock switching control unit 15 holds the switching control signal for T1 seconds longer than the above-described T2, it is not switched to the clock CLK3a again.
[0017]
The configuration and operation of the preferred embodiment of the clock switching circuit according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention. For example, it goes without saying that the processing in the reception clock switching control unit 15 can be realized by a CPU (central processing unit) equipped with a program.
[0018]
【The invention's effect】
As understood from the above description, according to the clock switching circuit of the present invention, the following remarkable effects in practical use can be obtained. First, when the frequency of the selected (selected system) input clock becomes abnormal, it is possible to prevent the PLL circuits of both systems from detecting a frequency drift / slip alarm and causing a system failure. The PLL circuit drift / slip alarm is used to monitor the failure of the PLL circuit itself. In the conventional circuit, when a drift / slip alarm is generated in both PLL circuits, it is determined that both PLL circuits have failed. It was a system failure. Since the drift / slip detection is performed by comparing the input clock with the output clock of the PLL circuit, the drift / slip detection occurs even when the frequency of the input clock becomes abnormal. For this reason, since the input clocks of both system PLL circuits are the same signal, when the frequency of the input clock becomes abnormal, a drift / slip alarm occurs in both system PLL circuits, resulting in a system failure. However, according to the present invention, only when a drift / slip alarm of the two-system PLL circuit occurs, it is determined that the frequency of the input clock is abnormal, and the switching is generated by controlling the input clock switching signal. As a result, even if the input clock becomes abnormal in frequency, it will not cause a system failure.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a clock switching circuit according to the present invention.
FIG. 2 is a flowchart showing an operation of a reception clock switching control unit shown in FIG.
FIG. 3 is a timing chart showing an operation of the reception clock switching circuit shown in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a conventional clock switching circuit.
[Explanation of symbols]
11a, 11b Clock reception circuit 12a, 12b Reception clock switching circuit 13a, 13b PLL circuit 14a, 14b Distributor 15 Reception clock switching control unit ALM7a, ALM7b Drift / slip alarm

Claims (5)

A pair of clock receiving circuits to which the respective clocks are input, a receiving clock switching circuit, a PLL circuit and a distributor, and a receiving clock switching control unit for switching and controlling the input clock of the receiving clock switching circuit; In the clock switching circuit that outputs the output clock from the distributor,
A clock switching circuit that outputs a switching control signal for switching an input clock of the reception clock switching circuit based on both of the pair of frequency monitoring results output from the pair of PLL circuits.   The switching control signal for switching an input clock of the reception clock switching circuit is generated when both a drift / slip alarm based on an input / output clock of the pair of PLL circuits is detected. Clock switching circuit.   3. The clock switching circuit according to claim 1, wherein the switching control signal is held for a predetermined time after the switching control signal is generated.   4. The clock switching circuit according to claim 3, wherein the predetermined time is selected to be longer than a time during which the PLL circuit recovers drift / slip after the clock signal is switched.   5. The input clock is held and switching is not performed when the drift / slip alarm is detected from only one of the pair of PLL circuits. Clock switching circuit.

Images