JPH06104882A - Network synchronizing clock supply device - Google Patents

Abstract

PURPOSE:To provide the network synchronizing clock supply device capable of automatically switching to a normal input clock path by monitoring the frequency of an active reference external clock signal and the frequency of a spare external clock signal and sensing the cause of the fluctuation if there is a frequency fluctuation between the clock signal to be inputted and an output clock signal. CONSTITUTION:The device is provided with a clock selection switch 27a selecting one of the external clock signals according to a selection control signal and a network synchronizing PLL21a subordinately synchronizing with the selected external clock and generating an output clock signal. Further, it is provided with plural frequency comparison sections 24a, 25a, and 26a separately comparing the frequency of the output clock signal and the frequency of plural external clock signals and sending an abnormal detection signal when the external clock signal is abnormal and a control section 29a sending the selection control signal based on the abnormal detection signal to be sent from the plural frequency comparison sections 24a to 26a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network synchronous clock supply device used in a communication control device such as a local area network and a multimedia multiplexer.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional network synchronous clock supply device. The network synchronization clock supply device has a redundant configuration including two first and second clock supply units 100a and 100b having the same configuration. A reference external clock signal f0a and a backup external clock signal f0b are supplied to the network synchronization clock supply device, and an output clock signal synchronized with either one of the external clock signals is generated.

In the first clock supply section 100a of FIG. 4, 1a is a network synchronization PLL, which generates an output clock signal f3a synchronized with an input clock signal f0.
Frequency dividers 2a and 3a divide the output clock signal f3a to generate a comparison clock signal f2a having the same frequency as the clock signal f0 and a counting clock signal f1a used for frequency comparison. Reference numeral 4a denotes a frequency comparator, which is a clock signal f
The phase difference between 0 and the comparison clock signal f2a is counted using the counting clock signal f1a, the frequency difference between the two and either clock loss are detected, and the control unit 9a is notified.

Reference numeral 7a is a switch for switching two external clock signals, which is a reference external clock signal f0a or a spare external clock signal f0b according to a selection control signal from the controller 9a.
Select one of the. An external clock interface 8a extracts an external clock signal on the transmission path.

In the synchronization state, the network synchronization PLL 1a has a large time constant and a small loop gain in order to suppress the disturbance of the clock signal f0. , The phase of the output clock signal f3a is set and used so as not to change. The detection cycle of the frequency comparison unit 4a is the network synchronization PLL.
It is set smaller than the time constant of 1a.

The above-mentioned configuration is applied to the second clock supply section 10
The same applies to 0b, and a description thereof will be omitted.

Next, the operation of the above conventional example will be described.
In the frequency comparison unit 4a, the clock signal f0 and the network synchronization PL
The comparison phase difference obtained by dividing the output of L1a is counted, and when the phases continuously change in the same direction, it is determined that there is a difference in the frequencies of both clocks, and the control unit 9a is notified of an alarm as an abnormality detection signal. To do. It also notifies when either of the clock signals is disconnected.

It is assumed that the frequency of the reference external clock signal f0a has changed for some reason. As mentioned above,
The network synchronization PLL 1a has a large time constant and a small loop gain, while the frequency comparison unit 4a is set smaller than the time constant of the network synchronization PLL 1a, so that the network synchronization PLL 1a cannot be detected. Even a slight frequency fluctuation of the reference external clock signal f0a is detected by the frequency comparison unit 4a. The control unit 9a switches the selected clock signal f0 from the reference external clock signal f0a to the backup external clock signal f0b.

As described above, even in the above-described conventional network synchronization clock supply device, when the frequency fluctuation or disconnection of the input reference external clock is detected, the network synchronization clock signal is switched to the spare external clock signal to provide a stable network synchronization clock signal. Can be sent out.

[0010]

However, in the above-described conventional network synchronization clock supply device, since only the frequency abnormality and disconnection of the reference external clock signal input to the network synchronization PLL are monitored, a spare external device to be switched to is used. There is a problem that the normality of the frequency of the clock signal cannot be confirmed.
Further, when switching from the current clock supply unit to another clock supply unit, there is a problem that it is not possible to determine in advance whether the frequency of the output clock signal from the other clock supply unit is normal. Further, even if the detected frequency abnormality is an abnormality of the oscillator of the network synchronization PLL in the clock supply unit itself, there is a problem that it is mistakenly recognized as an abnormality of the external clock signal.

The present invention solves the various problems of the prior art as described above. The frequencies of the working reference external clock signal and the backup external clock signal are constantly monitored and the input external clock signal and the output clock signal are output. It is an object of the present invention to provide an excellent network synchronous clock supply device capable of autonomously switching to a normal input clock path by detecting the cause of the frequency fluctuation between the signal and the signal.

[0012]

In order to achieve the above object, the present invention provides a clock selecting means for selecting one of the external clock signals according to a selection control signal, and a sub-command dependent on the selected external clock signal. Phase synchronizing means for generating the output clock signal in synchronization with each other, and a plurality of means for independently comparing the frequency of the output clock signal and the frequencies of a plurality of external clock signals to send an abnormality detection signal when the external clock signal is abnormal And the control means for transmitting the selection control signal based on the abnormality detection signal transmitted from each of the plurality of frequency comparison means.

[0013]

Therefore, according to the present invention, by separately monitoring the frequencies of the external clock signals of a plurality of systems, it is necessary to switch the input clocks by causing an abnormality in the clock signal currently used as the synchronization reference. If so, the clock can be switched to a clock whose normality has been previously confirmed.

When a frequency difference with the external clock signal is detected due to an abnormality in the oscillator of the network synchronization PLL of the clock supply unit, the output of another redundant clock supply unit is detected. Since a frequency difference is also generated between the clock signal and the clock signal, it is possible to reliably detect the abnormality of the PLL of its own clock supply unit.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the present invention. Also in this embodiment, as in the conventional example, the network synchronous clock supply device has a redundant configuration including two first and second clock supply units 200a and 200b which are clock generation means having the same configuration. Therefore, the reference external clock signal f0a and the spare external clock signal f0b are supplied to this network synchronous clock supply device, and an output clock signal synchronized with either one of the external clock signals is generated.

In the first clock supply section 200a of FIG. 1, 21a is a network synchronization PLL as a phase synchronization means and generates an output clock signal f3a synchronized with an input clock signal f0. Reference numerals 22a and 23a denote frequency dividers which divide the output clock signal f3a to generate a comparison clock signal f2a having the same frequency as the clock signal f0 and a counting clock signal f1a used for frequency comparison. 24a, 25
a and 26a are frequency comparators as frequency comparing means, and the frequency comparator 24a is a reference external clock signal f.
The phase difference between 0a and the comparison clock signal f2a is counted by using the counting clock signal f1a, and the frequency difference between the two and either one of the clock interruptions are detected, and the control unit 29a serving as a control unit.
To notify. The frequency comparator 25a counts the phase difference between the spare external clock signal f0b and the comparison clock signal f2a by using the counting clock f1a, detects the frequency difference between the two and either clock break, and notifies the control unit 29a. To do. In addition, the frequency comparator 26a outputs the comparison clock signal f
The phase difference between 2a and the comparison clock signal f2b in the clock supply unit 200b is counted by using the counting clock f1a, the frequency difference between the two and either clock loss are detected, and the control unit 29a is notified.

In the synchronization state, the network synchronization PLL 21a has a large time constant and a small loop gain in order to suppress the disturbance of the clock signal f0. , The phase of the output clock signal f3a is set and used so as not to change.
The detection period of the frequency comparison units 24a, 25a, 26a is set smaller than the time constant of the network synchronization PLL 21a.

Reference numeral 27a denotes a changeover switch as a clock selecting means for selecting one of the two external clock signals, which is either a reference external clock signal f0a or a spare external clock signal f0b depending on a selection control signal from the control unit 29a. Choose one. An external clock interface 28a extracts an external clock signal on the transmission path. Reference numeral 30 is an output clock switching circuit as a clock switching means for switching the output clock signals output from the clock supply units 200a and 200b and outputting them as the network synchronization clock signal f3.

The second clock supply section 200b is exactly the same as the first clock supply section 200b.
The description is omitted.

FIG. 2 shows the frequency comparison units 24a, 25a and 2a.
It is a structural example of 6a. In FIG. 2, reference numeral 41 denotes a phase comparison unit, which compares the phase of the input clock signal fin shown in FIG. 3A with the phase of the comparison clock signal f2a from the frequency divider 23a shown in FIG. 3B. Then, a pulse train of the phase difference signal as shown in FIG. 3C is output according to the phase shift between the two. Reference numeral 42 denotes a gate circuit, which outputs the count clock signal f1a supplied from the frequency divider 22a while the phase difference signal from the phase comparison unit 41 is at a high level. A counter circuit 43 counts and outputs the count clock signal f1a from the gate circuit 42. The clock circuit 4
3 is reset when the comparison clock signal f2a is at high level. 44 is a latch circuit, which is a comparison clock signal f
When 2a is at a high level, the count value output from the counter circuit 43 is latched. 45 is also a latch circuit, which latches the count value latched by the latch circuit 44 when the comparison clock signal f2a of the next cycle is at a high level.

Reference numeral 46 is a comparator, which detects the difference between the count values latched by the latch circuits 44 and 45. When the value of the latch circuit 44 is larger than the value of the latch circuit 45, that is, when the phase difference increases in the positive direction, up
When the value of the latch circuit 44 is smaller than the value of the latch circuit 45, that is, when the phase difference increases in the negative direction, the up pulse signal indicating
Send n pulse signals.

Reference numeral 47 is an up-down counter circuit,
Upon receiving the up signal or the down signal, the comparison clock signal f2a is counted up or down and the count value is output. Reference numeral 48 denotes a decoder, which detects that there is a frequency fluctuation when the count value of either the up-count value or the down-count value from the up-down counter circuit 47 continues for a specified value or more, and controls the control section 29.
An abnormality detection signal, that is, an alarm is output to a. 49
Is a frequency divider, and supplies the value of the monitoring cycle to be counted to the up / down counter circuit 47.

When the input clock signal fin or the comparison clock signal is cut off, the phase comparison section 41 directly outputs the abnormality detection signal.

Next, the operation of the above embodiment will be described. In FIG. 1, it is assumed that the frequency of the reference external clock signal f0a has changed for some reason when the clock supply unit 200a is the current network synchronization clock transmission means. As described above, since the network synchronization PLL 21a normally has a small loop gain in the synchronization state, it does not immediately respond to the frequency fluctuation of the reference external clock signal f0a, and the phase of the output clock signal f3a changes. It does not change. On the other hand, since the detection cycle of the frequency comparison units 24a, 25a, 26a is the same as the cycle of the comparison clock signal f2a, the frequency fluctuation of the input clock signal fin is immediately detected.

The frequency variation of the reference external clock signal f0a is detected by the frequency comparison section 24a, and an abnormality detection signal is sent to the control section 29a. In this case, since only the frequency comparison unit 24a sends the abnormality detection signal, the control unit 29a can determine that the spare external clock signal f0b is normal and gives the selection control signal to the switch 27a.
The input clock signal f0 is the reference external clock signal f0.
Switching from a to the spare external clock signal f0b.

When the network synchronization PLL 21a fails, an abnormality detection signal is output from all the frequency comparison units 24a, 25a and 26a to the control unit 29a.
The a communicates with the control unit 29b of the second clock supply unit 200b, gives a switching signal to the output clock switching circuit 30, and sends the network synchronization clock to the clock supply unit 20.
Switch from 0a to the clock supply unit 200b. However, in this case, the network synchronization PL of the clock supply unit 200b is used.
L21b is assumed to be operating normally.
That is, it is premised that the probability that the network synchronization PLLs of the two systems will fail is extremely low.

Furthermore, when frequency fluctuations occur in both the reference and standby external clock signals, the frequency comparison units 24a and 25a send an abnormality detection signal, and the frequency comparison unit 26a does not send an abnormality detection signal. Therefore, the control unit 29a switches to a free-running mode by an internal oscillator (not shown) or switches to a backup reference clock signal.

As described above, according to the above embodiment, the frequencies of the two external clock signals can be monitored at the same time. Therefore, when a failure occurs in the active external clock signal, it is possible to reliably switch to the normal spare external clock signal. It has the advantage that Also, in case of a failure of the network synchronization PLL,
It is possible to distinguish from an abnormality in the external clock signal, and by switching the clock supply unit, it is possible to maintain accurate supply of the network synchronization clock signal.

When both external clock signals become abnormal, either the backup reference clock is switched or the network synchronization PLL is self-running. In this case, by using a storage program type DP-PLL or the like for the network synchronization PLL, it is possible to minimize the frequency deviation when the PLL is free running.

In the above embodiment, the external clock signal and the clock supply unit have two systems, but two or more systems of spare external clock signals are provided and the clock supply unit has three or more systems. You can also

[0031]

As is apparent from the above-described embodiment, the present invention constantly monitors the frequency of the input external clock signal, and the frequency is maintained even when a failure occurs in the current external clock signal system. Since it is possible to quickly switch to the system of the spare external clock signal whose normality has been confirmed, and to switch to self-propelled quickly even when failures occur in all the systems of external clock signals at the same time. The advantage is that it is possible to supply an extremely reliable network synchronization clock signal. Furthermore, by monitoring the outputs of the two redundant network synchronization PLLs with each other, it is possible to detect an abnormality in the network synchronization PLL of its own, and by switching the clock supply unit itself, the reliability of the clock is further increased. Have.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a network synchronous clock supply device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a frequency comparison unit.

FIG. 3 is a timing chart of signals in the frequency comparison unit of FIG.

FIG. 4 is a block diagram of a configuration example of a conventional network synchronous clock device.

[Explanation of symbols]

21a, 21b Network synchronization PLL 22a, 22b, 23a, 23b Frequency divider 24a, 24b, 25a, 25b, 26a, 26b Frequency comparison unit 27a, 27b Changeover switch 28a, 28b External clock interface 29a, 29b Control unit 30 Output clock changeover Circuit 41 Phase comparison unit 42 Gate circuit 43 Counter circuit 44, 45 Latch circuit 46 Comparator 47 Up-down counter circuit 48 Decoder 49 Frequency divider 200a, 200b Clock supply unit

Claims (2)

[Claims] 1. An output for communication control based on a selected external clock signal selected from one of a reference external clock signal or one or a plurality of spare external clock signals supplied from the outside. A redundant network synchronization clock supply device having a plurality of systems of synchronization clock generation means for generating a clock signal, wherein the synchronization clock generation means generates one of the external clock signals according to a selection control signal. A clock selecting unit for selecting, a phase synchronizing unit for generating the output clock signal in a subordinate synchronization with the selected external clock signal, and a frequency of the output clock signal and a frequency of each of the external clock signals are independently compared. And a plurality of frequency comparison means for transmitting an abnormality detection signal when the external clock signal is abnormal, and the plurality of frequency comparison means. Network synchronization clock supply apparatus characterized by comprising a control means for sending said selection control signal based on the abnormality detection signal sent from, respectively. 2. The clock generation means compares the frequency of an output clock signal transmitted from itself with the frequency of another output clock signal transmitted from another clock generation means, and outputs the output clock signal or the other. 2. The network synchronous clock supply device according to claim 1, further comprising frequency comparison means for sending an abnormality detection signal to said control means when any of the output clock signals of 1. is abnormal.