JPS6226605B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a standard clock generator that generates a clock based on a cesium atomic oscillator.

In a digital communication network, in order to organically connect various devices within the network, it is necessary to establish frequency synchronization between stations. For this purpose, a very stable clock generation source is placed in each station and an independent synchronization method is used in which they operate independently of each other, or a very stable clock generation source is placed in one station or a main station and the stations below it are synchronized. A subordinate synchronization method has been proposed in which the clock is distributed and a synchronizer is installed at a lower station to establish frequency synchronization.

Regardless of the synchronization method, a standard clock generator is required to generate a reference clock, and if digital communication is to be connected between networks or internationally, the station corresponding to the connection point is required. It is necessary to match each other's clock frequency accuracy.

Therefore, it is conceivable to introduce a cesium atomic oscillator with high frequency accuracy as a clock source. In this case, it is important to realize a standard clock generator that does not impair the performance of the cesium atomic oscillator and can cope with its failures. This type of standard clock generator has a configuration in which cesium atomic oscillators are duplicated or tripled and the output of one of them is used. FIG. 1 shows the conventional device. The outputs of the two working and standby cesium atomic oscillators 1a and 1b are selected by switching circuits 2a and 2b, and digital processing type phase synchronization circuits 3a and 3b are respectively connected.
The output terminals are made subordinate to each other, and are further configured to be duplexed (currently used and reserved) so that normal outputs can be selected to the output terminals 5a and 5b by the switching circuits 4a and 4b at the subsequent stage.

Digital processing type phase synchronization circuit 3 of this device
As shown in FIG. 2, a and 3b are voltage control crystals which divide the output of the cesium atomic oscillator input from the terminal 11 by a frequency divider 12 and supply it to the phase comparator 13, and which also have a digital control input section. The output of the oscillator 14 is divided by a frequency divider 15 and supplied to a digital phase comparator 13, which compares the phases of its two inputs and outputs the result. In the control section 16
The CPU 17 reads out the program in the memory 18, decodes and executes it, takes in the output of the digital phase comparator 13, processes it statistically, and provides a control value to the voltage controlled oscillator 14. A memory 19 is provided within the control unit 16 for reading and writing data used in the processing. The output of voltage controlled oscillator 14 is supplied to output terminal 21 .

In the conventional device shown in FIGS. 1 and 2, 2
Even in the event of a failure in the cesium atomic oscillators 1a and 1b, the digitally controlled crystal oscillator 14 can be made to run freely using the immediately preceding control data as input, and extreme frequency jumps do not occur. However, for frequency abnormalities that may occur in the cesium atomic oscillators 1a and 1b, it is not possible to determine which oscillator has the abnormality. There were deficiencies that could not be addressed. Also, cesium atomic oscillators 1a, 1b
Digitally processed phase synchronized circuit 3 even when
The outputs of a and 3b take discrete frequency values that depend on the precision of the digital control in the circuit,
There was a drawback that the output frequency was slightly different from the output frequency of the cesium atomic oscillators 1a and 1b. Furthermore, since the loop of the phase-locked circuits 3a and 3b includes a complicated control section 16, it is difficult to ensure high reliability.

FIG. 3 shows another conventional clock generator.
The cesium atomic oscillator is triplexed as 1a, 1b, and 1c, and the switching circuits 2a to 2c, as in the case of FIG.
Phase synchronization circuits 6a-6c, subsequent switching circuits 4a-
4c, and further a frequency measurement monitoring section 22,
Priority can be given to the three cesium atomic oscillators 1a to 1c, and if one oscillator causes a frequency abnormality, it is possible to detect that one oscillator. Therefore, the subsequent switching circuit 4
By a to 4c, abnormal cesium atomic oscillators can be excluded and the output of one normal oscillator can always be selected as the clock source.

However, in this conventional device, since the phase synchronized circuits 6a to 6c dependent on the clock source are configured with analog phase synchronized oscillators, when the cesium atomic oscillators 1a to 1c have a system failure, the phase synchronized oscillators 6a to 6c
A to 6c run freely with a large frequency deviation determined by the frequency stability of the built-in crystal oscillator. Furthermore, when the cesium atomic oscillators 1a to 1c are switched, the outputs of the phase synchronized oscillators 6a to 6c have a drawback that a large frequency deviation occurs transiently. Furthermore, since this device has only one system of frequency measurement and monitoring section 22, if it fails, it becomes impossible to measure the frequency deviation between the cesium atomic oscillators 1a to 1c, and a frequency abnormality occurs in the currently used cesium atomic oscillators. In this case, abnormal frequency outputs are output from the device output terminals 5a to 5c, which has the disadvantage of impairing device reliability.

In order to eliminate these drawbacks, this invention is equipped with a cesium atomic oscillator that can be triplexed at any time, and also provides a selection switch that compares and measures the mutual frequency difference between the three units and operates based on the comparison data. Furthermore, two or more systems of phase synchronized oscillators each having a phase adjustment function to reduce phase jumps during switching and whose frequency can be controlled based on the previous data when the input is interrupted are configured to be subordinate to the cesium atomic oscillator. It is.

FIG. 4 shows an embodiment of the present invention, in which cesium atomic oscillators 1a to 1d are commonly connected to two priority selection switches 23a and 23b through cesium atomic oscillator failure detection circuits 7a to 7d, respectively. These switches 23a, 23b have a function of manually setting the priority order and a function of changing the priority order in the event of a failure of the cesium atomic oscillator. They are connected to system selection switches 24a and 24b, respectively. These switches 24a and 24b are for selecting the active system output from the three systems of cesium atomic oscillator outputs, and are controlled by the control section 25.
The active system selection switches 24a and 24b are switches 26a and 26a for switching between active and standby system outputs.
These switches 26a and 26b are controlled by a control section 27, and are connected to phase synchronized oscillators 28a and 28b which have a phase adjustment function and are frequency controllable during free running. The states of the phase synchronized oscillators 28a and 28b are determined by the control unit 29.
controlled by Phase synchronized oscillator 28a, 28
b is connected to both the changeover switches 31a and 31b, respectively, and the switches 31a and 31b are connected to the control unit 3.
2 and device output terminals 5a, 5
connected to b.

The output of cesium atomic oscillators 1a to 1c is normal
It operates at a frequency of 5MHz, and its frequency accuracy is 1× for a portable oscillator like the one used in this device.
It is said to be around 10 ^-11 . However, when using a cesium atomic oscillator, the main component, the cesium atomic beam tube, has a limited lifespan (3 years), and the control circuit inside the oscillator deteriorates or malfunctions. It is necessary to take into account that frequency anomalies exceeding ^-11 may occur, and that frequency anomalies in particular may not be detected by a cesium atomic oscillator alone.

Therefore, in order to detect frequency abnormalities in the cesium atomic oscillators, at least three oscillators are operated and their frequencies are compared. In this example, 4
It is equipped with three cesium atomic oscillators 1a to 1d, three oscillators 1a to 1c are in operation, and one oscillator 1d is used when one of the oscillators 1a to 1c in operation has a failure or when there are signs of a failure. It is used as a standby oscillator that enters the operating state in certain cases. Each of the fault detection circuits 7a to 7d is a cesium atomic oscillator 1a.
~1d output interruption, control system abnormality, etc. are detected. The priority selection switches 23a and 23b each manually select the four cesium atomic oscillators 1a to 1d to obtain three systems of cesium atomic oscillator output as their outputs, and in this example, the priority among the three systems is selected. can be set. These three systems of signals selected by switches 23a and 23b are constantly compared by frequency measurement monitoring units 22a and 22b, and priority is given to systems in the order of frequencies closer to the average frequency of the three systems of signals. At the same time, the presence or absence of abnormal values is monitored, and selection switch 2 is
4a and 24b are obtained. The operator switches the assigned priority order to switches 23a and 23b.
This priority data is set manually in the control unit 25.
given to. The priority order may be directly set in the control unit 25.

The frequency measurement monitoring units 22a and 22b are, for example, the fifth
As shown in the figure, the frequencies of the three systems of signals applied to the input terminals 34a to 34c are V ₁ , V ₂ ,
When V ₃ , frequency deviation measurement circuits 35a to 35
Mutual frequency deviation rate δ ₁₂ , δ ₂₃ , δ ₃₁ δ ₁₂ = (V ₁ − V ₂ )/V ₀ (1) δ ₂₃ = (V ₂ − V ₃ )/V expressed by c as follows: ₀ δ ₃₁ = (V ₃ − V ₁ )/V ₀ However, V ₀ 〓V ₁ 〓V ₂ 〓V ₃ is measured, and the data processing circuit 36 statistically processes the measurement results to determine the priority order, and also The presence or absence of the frequency is identified and a selection switch control signal is displayed and output from the terminal 37. For example, V ₁ ≠
In the case of V ₂ = V ₃ , the measurement results of δ ₁₂ = −δ ₃₁ ≠ O, δ ₂₃ = O are obtained, so input V ₁ other than the combination of V ₂ and V ₃ that minimizes the absolute value of the deviation rate can be judged as the worst.

In addition, an upper limit δ is set for the absolute value of the mutual frequency deviation rate.
If l (for example, 1×10 ^-11 ) is provided, |δij|≧
When δl (i, j = 1, 2, 3), one system other than i and j is |δ ₁₂ |, |δ ₂₃ |, |δ ₃₁ |<
In the case of δl, one system other than the combination that does not give the maximum value can be determined to have the first priority.

Priority active system selection switch 24a, 24b
The outputs of three systems from the priority selection switches 23a and 23b are respectively input, and under normal conditions, the system with the first priority is selected and output.
When there is an abnormality in the selected cesium atomic oscillator or the frequency exceeds the above-mentioned limit value, the fault information from the fault detectors 7a to 7d and the frequency measurement monitoring sections 22a and 22b is transferred to the switch control section 25, and the control is performed. Section 25 is selection switch 2
4a and 24b to automatically switch to the second priority output.

A maintenance person judges the operating status of the cesium atomic oscillators 1a to 1d and the data history of the frequency measurement monitoring units 22a and 22b, and manually operates the setting switches 23a and 23b when it is necessary to change the priority order. be able to.

In addition, if one of the three oscillators is removed as a preventive maintenance measure and the standby oscillator 1d is incorporated into the operating system, the standby oscillator 1d should be powered on and the standby system should be The operating system oscillator group is changed by a priority changeover switch, for example 23b. Next, the standby frequency monitoring section 22b
The frequencies are compared by , the changed priority order is determined, and the priority order setting switch 23b is again manually operated to change the priority order to the new priority order. Furthermore, by manually operating the priority order setting switch 23a of the active system, the priority order can be changed to the above order, and the active system can also be moved to a new state.

The cesium atomic oscillator output with the first priority is obtained as the output of the selection switches 24a and 24b, but
Two systems of phase synchronized oscillators 28a and 28b are subordinated to this via active/standby changeover switches 26a and 26b. Control signals for the switches 26a and 26b are issued by the switch control section 25 when the frequency measurement monitoring sections 22a and 22b are abnormal. The configuration of the phase synchronized oscillator is shown in FIG. 6, for example. The signal applied to the input terminal 38 is multiplied by n by a multiplier 39, and the signal from the voltage-controlled crystal oscillator 41 having an output frequency V ₀ is multiplied by n by the multiplier 42, and the resulting signal is combined with the phase detector. 43, and the error signal is fed back to the control terminal of the voltage controlled oscillator 41 via the low-pass filter 44 and changeover switch 45 during normal times.

In this way, since it operates as an analog phase-locked circuit during normal times, a signal with high frequency accuracy synchronized with the cesium atomic oscillator can be obtained from the output terminal 46 of the oscillator 41. Furthermore, since the phase comparison is performed at a frequency n times higher, a phase jump at the input is compressed to 1/n, thereby providing a phase adjustment function. That is, if n=8, the signal applied to the input terminal 38 is switched by the selection switch 24a or 24b, and the input signal phase corresponds to one cycle at worst.
Even if there is a jump of 200 ns, the signal appearing at the output terminal 46 will be reduced to a phase jump of 25 ns (=200/8) or less in the worst case. Moreover, the jump is smoothed by the action of the low-pass filter 44.

On the other hand, the output voltage of the low-pass filter 44 during normal operation is applied to the analog voltage memory 47, the voltage is digitized and the memory is updated, and an analog voltage that substantially matches the output voltage of the low-pass filter 44 is output from the memory 47. Get to the terminal. This voltage changes over time to compensate for characteristic changes within the phase-locked circuit loop, mainly frequency aging of the voltage controlled crystal oscillator 41, and the like. The memory 47 is A/
It consists of a D converter, a reversible counter, and a D/A converter.

Fault detector 7 is used when there is an abnormality in the three cesium atomic oscillators in the operating system or during replacement work for maintenance.
The signals from a to 7d are transferred to the switch control section 29, the switch 45 is operated by the signal from the control section 29, and the output voltage of the analog memory 47 is applied to the control terminal of the voltage control oscillator 41 to make the switch 45 free-running. state, and oscillate at almost the same frequency as normal. The control voltage from the analog memory 47 during free running is processed and generated based on data during normal operation, and can correct changes in characteristics within the loop such as inherent frequency aging of the voltage controlled oscillator 41.

When switching the cesium atomic oscillator, the phase comparator 4
3 suddenly changes, and the output from the output terminal 46 of the phase-locked oscillator undergoes a transient frequency shift due to this influence. In addition, the phase synchronized oscillators 28a, 28
Even when the signal b is allowed to run freely, a minute frequency change depending on the quantization step of the analog memory 47 occurs.

FIG. 7 shows an example of actual measurement values in the case of the embodiment of the present invention, and in _FIG . 43, and shows the phase change and frequency change determined by the loop constants of the phase synchronized oscillators 28a and 28b. In this example, the loop's natural frequency is 0.02 [rad/sec] and the attenuation constant is 1.56, resulting in a maximum phase change of 1.1×10 ^-3
The maximum frequency jump amount can be reduced by increasing the multiplier order n of the phase adjustment multiplier 39 or reducing ωn.

Figure 7B shows data when the analog memory 47 enters the free-running state at time _t1 when the frequency-related quantization step is ^3.92 The slope corresponds to the quantization step described above. Furthermore, by reducing the quantization step, the frequency error in the free-running state can be reduced.

The changeover switches 31a, 31b are activated by a signal from the control unit 32 when the active phase synchronized oscillators 28a, 28b fail, and transfer the outputs of the other phase synchronized oscillators 28a, 28b, which are always in a normal operating state, to the device output terminals 5a, 5b. It has the function of obtaining

As mentioned earlier, the priority setting is switch 2.
It may be performed directly to the control unit 25 without having to be performed by 3a and 23b. The switches 24a and 24b do not necessarily have to be prioritized. In addition, a phase control loop for a signal multiplied by n is provided in the phase synchronized oscillators 28a and 28b, and the phase is adjusted by this loop.
a, 26b, and its output divides the frequency by n, and a phase control loop for synchronizing the oscillator is provided, and the phase synchronized oscillator 28a, 28b
It can also be used as the output. Furthermore, this phase synchronized oscillator 2
8a and 28b may be constructed digitally.

As explained above, in the present invention, three or more cesium atomic oscillators are operated, their frequencies are constantly compared, and the one with the frequency closest to the average of the output frequencies of each oscillator is used as the reference oscillator. If this configuration is selected, and a highly stable analog phase-locked oscillator with the function of reducing phase jumps during switching is subordinated, a device output signal with high frequency accuracy can be obtained, and the influence of the change can be avoided even when the priority is changed. There is an advantage that it can be reduced. Furthermore, since the phase-locked oscillator has a memory outside the control loop, even if all the cesium atomic oscillators fail, there is an advantage that a device output with the same frequency accuracy as in normal operation can be obtained.

Furthermore, since all parts other than the cesium atomic transmitter are duplicated, maintenance is easy and the device has the advantage of extremely high reliability. Since a standard clock device with high reliability and frequency accuracy can be realized in this way, it can be used as a device for generating reference clocks for network synchronization systems in digital networks, and it can also be used to ensure sufficient quality and reliability even when connections are made between networks. Secured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional duplex standard clock device, FIG. 2 is a block diagram showing a digitally processed phase synchronized oscillator, which is an element of FIG.
Figure 4 is a block diagram showing a conventional triplex standard clock generator, Figure 4 is a block diagram showing an embodiment of the standard clock generator according to the present invention, and Figure 5 is the frequency measurement monitoring section of Figure 4. 6th block diagram showing an example of
The figure is a configuration diagram showing an example of the phase-locked oscillator in Figure 4,
FIG. 7 is a diagram illustrating actual measurement results of device output frequency changes during priority switching and self-running in an embodiment of the device of the present invention. 1a-1d: Cesium atomic oscillator, 5a, 5
b: Device output terminal, 7a to 7d: Cesium atomic oscillator failure detector, 22a, 22b: Frequency monitoring section, 23a, 23b: Priority selection switch, 2
4a, 24b: active system selection switch, 25: selection switch control section, 26a, 26b: active standby changeover switch, 29: phase synchronization state control section, 32: changeover switch control section, 34: analog voltage memory.

Claims (1)

[Claims] 1 Equipped with three or more cesium atomic oscillators that are always in operation and one or more standby cesium atomic oscillators, a setting switch that selects the output of three systems from among them, and a frequency between the outputs of the selected three systems. A frequency measurement monitoring unit that measures and processes the deviation, a working system selection switch that has the function of selecting one system of cesium atomic oscillator output based on the frequency comparison result, and is located after the above setting switch; The active/backup changeover switch is synchronized with the output of the active/backup changeover switch during normal times after phase adjustment, and has a memory that stores control data.In the event of a failure in the entire cesium atomic oscillator system, the frequency can be controlled using the previous control data and it can run freely. A standard clock generator equipped with two or more systems each of a phase-locked oscillator and a working/standby changeover switch placed after the phase-locked oscillator.