JPS6072415A - Synchronism fault detecting circuit of phase locked loop - Google Patents

Abstract

PURPOSE:To eliminate the defect that a PLL lock fault detecting circuit responds too much to the operation of a switch by providing a voltage discriminating device detecting a prescribed level of an output voltage of a phase comparator in a phase locked circuit, an integration circuit integrating an output voltage of the voltage discriminating device and a memory circuit storing an output of the integration circuit. CONSTITUTION:The voltage discriminating device 12 and the memory circuit 14 correspond to the voltage discriminating device 10 and the memory circuit 11 of a conventional circuit. Moreover, the integration circuit 13 consists of a simple CR circuit having a time constant tau or the like. The integration circuit 13 suppresses a very fast change in the output voltage of the voltage discriminating device 12 and selects a comparatively slow change and gives the result to the memory circuit 14. The time required for the switching operation of the switch 8 is very short normally and the relocking of the PLL as the result is finished in a very short time. An output voltage change of PD based on a fault of the PLL is normally slow against the result. Thus, the discrimination of fault at the operation of the switch is made ineffective by utilizing this point.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This article 7I relates to a synchronization abnormality detection circuit for a phase-locked circuit (hereinafter referred to as 1) Ll, and particularly relates to a synchronization abnormality detection circuit for a phase-locked circuit (hereinafter referred to as 1) Ll, and particularly for detecting a synchronization abnormality in a phase-locked circuit (hereinafter referred to as 1)Ll. The present invention relates to a synchronization abnormality detection circuit configured to be insensitive to the operation of a switch in a selectively coupled PLL.

[Technology background]

A PLL is a circuit that has the function of generating an output signal that is phase-synchronized with an input signal. It is widely used in various types of consumer equipment, including communication equipment, for the purpose of converting it to other frequencies.

A PLL generally has a configuration as shown in FIG. In the figure, 1 is an l/n frequency divider, 2 is a phase comparator (PD),
3 is a low-pass P wave generator (LP'F), 4 is a voltage controlled oscillator (v
CO), 5 is an x/m frequency divider. Here, r and m are natural numbers.

PD2 divides the input signal (ωL) into l/n by l/n frequency divider 1.
The signal frequency-divided into l/m and the output signal (ω0) of vCO4
Compare each phase of the signal frequency-divided to 1/rn by frequency divider 5,
It outputs an error voltage according to the phase difference. The output voltage of PD 2 is smoothed by LPF 3, and the control voltage for vCO4 controls the oscillation Jjd wave number of VCO4.

Since PD2, LPF3, and vC04 constitute a closed roof, the oscillation frequency of VCO4 is automatically controlled so as to always maintain a constant relationship with the input signal frequency.

In recent years, communication devices, broadcasting devices, and the like that require high frequency stability have begun to use atomic oscillators as reference frequency sources instead of conventional highly stable crystal oscillators. The output frequency of an atomic oscillator is typically 5 MHz', 1
Since the standard frequency value such as 0 MI (z) is determined, in order to obtain a convenient frequency for each device, a means to convert it to the required frequency while maintaining the frequency stability of the atomic oscillator is required. .PLL is one suitable means to be used for such purpose.

On the other hand, atomic oscillators have the drawback of being less reliable than conventional crystal oscillators due to their circuit configuration. Therefore, if both high frequency stability and high M reliability are required, the core atomic oscillator may be duplicated, etc.
There are many cases in which redundant configurations are adopted.

FIG. 2 shows an example of a frequency conversion circuit having the above-described redundant oscillator configuration. In the figure, 6 and 7 are atomic oscillators, and for convenience, 6 is the current (N) and 7 is the reserve (K). Further, 8 is a switch, 9 is a switching control circuit, and PLL circuits 1 to 5 are the same as those shown in FIG.

In the configuration shown in Figure 2, the current atomic oscillator (N)
The output of is selected by the switch 8 and applied to the PLL.

On the other hand, if an abnormality occurs in each atomic oscillator, an abnormality signal ALM is sent to the switching control circuit 9. Switching control circuit 9
has a logic function that outputs a switching control signal to select a valid standby oscillator (E) when an abnormality is detected in the active atomic oscillator (N). As a result, a normal signal can always be obtained from the switch 8. However, if an abnormality occurs in the PLL itself, such a redundant oscillator configuration becomes meaningless, so it is especially important to detect an abnormality in the PLL, that is, when the PLL is out of synchronization. come.

The synchronous/asynchronous state of the PLL can be determined by monitoring the output voltage of the phase comparator PD.

Figure 3 (-) is an example of the PD output voltage in the asynchronous state of PLL.d In the asynchronous state of PL,L,
The pressure at output 1 of the PD is constant at the upper limit voltage or lower limit voltage as shown in the figure, or it is slow or depends on x/n of the input frequency' and 7
It oscillates between the upper limit voltage and the lower limit voltage at the difference frequency (beat) between 1/m of the 00 frequency. The former occurs when there is no input signal to the PLL, and the latter occurs when there is an input signal but V
If the retraction is incomplete due to an oscillation abnormality of C.0, etc.
arise. - The conventional PLL synchronization abnormality detection circuit monitors 1 PD output by setting a threshold value within the upper and lower limits of the PD% pressure described above.

An example of the circuit is shown in FIG. 3(h). In the figure, reference numeral 10 denotes a voltage determiner to which the above-mentioned □ threshold value is set, and 11 denotes a memory circuit, which is the output of the voltage determiner 10 (marked in bold). - If the PD voltage exceeds the threshold even once, the voltage determiner 10 operates, and its output is held in the memory circuit 11. From the VC where this memory circuit is installed, pb
Chattering of the output of the detection circuit is prevented even in the event of an abnormality such as an oscillation between 1 and 6□ between the upper and lower voltage limits. However, if the conventional PLL synchronization abnormality detection circuit shown in Fig. 3 (A) is applied to the frequency conversion circuit as shown in the plan, the switching device 7Z will fail due to an abnormality in the current atomic oscillator (N). Even when the atomic oscillator □ (E) is activated and switched to the spare atomic oscillator (E), the PD output voltage fluctuates transiently (41), which is a drawback that it is determined to be abnormal. This is due to the operation of the switching device, in particular, when the input is switched momentarily, the PLL starts pulling control again, and the PD output voltage transiently changes to its upper or lower limit. I am by.

Therefore, after a certain draw-in time after the entry change, P
Even if LL is in the normal = operating state, the voltage judge lO of the PLL synchronization abnormality detection circuit will determine that it is in the asynchronous 1st period state, so the hold function of the memory circuit 11 will hold the : The abnormality detection state will be abnormal. In particular, in a system where multiple frequency conversion circuits are provided as shown in Figure 1, and the PLL synchronization and abnormality detection circuit in the active system switches to the backup system when a synchronization abnormality is detected, in practice, the atomic oscillator In many cases, it is not possible to use the spare side of the system, resulting in an unreasonable situation in which the redundant configuration does not function effectively.

[Object and structure of the invention]

As described above, an object of the present invention is to eliminate the drawback that the PLL synchronization abnormality detection circuit overreacts to the operation of the switch, as in the case where the K PLL is placed after the switch that selects multiple signal sources. Therefore, the PLL is only used for the time until the re-drawing of the PLL is completed due to switching
This provides a means to limit the synchronization abnormality detection function of the LL.

Accordingly, the configuration of the present invention provides a system including a plurality of signal sources, a switch for selecting one of the plurality of signal sources, and a phase synchronization circuit disposed after the switch.
A voltage determiner that detects a predetermined level of the output voltage of the phase comparator in the phase-locked circuit, an integrating circuit that integrates the output voltage of the voltage determiner, and a memory circuit that holds the output of the integrating circuit. It is characterized by having

[Embodiments of the invention]

The details of the present invention will be explained below with reference to examples.

FIG. 4 is a block diagram of one embodiment of the PLL synchronization abnormality detection circuit according to the present invention, and FIGS. 5(a) to 5(C) are time charts thereof.

In FIG. 4, 12 is a voltage judger, 13 is an integration circuit,
14 is a memory circuit. The voltage determiner 12 and the memory circuit 14 correspond to the voltage determiner 10 and the memory circuit 11 of the conventional circuit shown in FIG. 3Cb). Further, the integrating circuit 13 can be configured, for example, by a simple CR1 path having a time constant τ.

The integrating circuit 13 blocks extremely fast changes in the output voltage of the voltage determiner 12 and separates relatively slow changes.
It is transmitted to the memory circuit 14. Normally, switch 8 (Figure 2)
The time required for the switching operation is extremely short, and the resulting P
The LL retraction operation also ends in a very short time. On the other hand, based on PLL abnormalities (PD output voltage changes are normally slow), by utilizing this point, it is possible to invalidate the abnormality judgment when the switching device operates. can be converted into

Next, the circuit operation will be explained in detail according to the time chart shown in FIG. In addition, FIG. 5(α) shows the output signal waveform of the voltage judger 12, FIG. 5(h) shows the output signal waveform of the η(divider circuit 13), and FIG. This is the time chart shown in .

@H# represents the normal level, and 'L'' represents the abnormal level.

Region ■ in the figure is when the switching device is operating. Since the input of the PLL is switched depending on the operation of the switching device, the output voltage of the voltage determiner 12 is , changes extremely rapidly between "■1" and "L" levels. Incidentally, the time constant τ of the integrating circuit 130 is set to be sufficiently large for this change time. Therefore, as shown in (b), the output level of the integrating circuit 13 cannot fall below the operating threshold value predetermined for the memory circuit 14. As a result, the memory circuit 14 is prevented from operating, and as shown in (C), the memory circuit 14 does not output a signal level "L" indicating abnormality determination.

A region ◎ indicates a case where an abnormal phenomenon occurs in which the PD output voltage remains constant at the upper limit or lower limit level. In this case, the time delay (τ) due to the integration action of the integration circuit 13
However, the output voltage of the integrating circuit 13 eventually exceeds the operating threshold of the memory circuit, and the memory circuit 14 operates.
The output level is "L" level indicating abnormality determination.

Note that this state also appears when the circuit is started, but in this case a reset operation is performed to cancel the abnormality determination.

The region indicates the case where the 760 frequency is too far away from the frequency synchronized to the input frequency, making frequency pull-in impossible and causing the PD output voltage to oscillate between the upper and lower limits. In this case, as in the case of region (B), the output level of the integrating circuit 13 exceeds the threshold value at the first change (that is, because the value of the time constant τ is appropriately set), and the memory circuit 1
4 operates, and a signal level "L" representing an abnormality determination is output.

In this way, abnormality and normality are distinguished from each other based on the difference in the form of PD output voltage change corresponding to the mode of some abnormal phenomena in the PLL. In other words, when using a highly stable oscillator as the VCO, the VCO17) frequency change is small, so the PD output voltage is gated,) the JEJ period,
Since the cycle is sufficiently long compared to the period of P9 electrician change when the switch is activated, it is possible to distinguish between the two abnormal phenomena by setting the time constant τ of the integrating circuit 130 to an intermediate value between the two. becomes. In this embodiment, the integrating circuit is placed at the rear of the voltage determiner, but the same operation can be achieved even if the integrating circuit is placed in reverse.

〔Effect of the invention〕

□As described above, according to the present invention, it is possible to eliminate abnormality determination in the case of switch operation with a simple circuit configuration, and it is suitable for a PLL circuit combined with a redundant configuration signal source. A PLL synchronization abnormality detection circuit is obtained, and the reliability of the system can be significantly improved.

[Brief explanation of the drawing]

Figure 1 shows a general configuration example of a PLL, Figure 2 shows an example configuration of a frequency conversion circuit including a redundant configuration, and Figure 3 (a) shows the output voltage of a PLL in an asynchronous state. 3(h) is a diagram showing the configuration of a conventional PLL abnormal synchronization detection circuit, FIG. 4 is a diagram showing the configuration of an embodiment of the circuit of the present invention, and FIG. 5(α), ( b) and (c) are time charts of the embodiment circuit shown in FIG. 4, respectively. In the figure, l is a 1/L frequency divider, and 2 is a phase comparator PD. 3 is a low frequency F wave generator LPF, and 4 is a voltage controlled oscillator VCO. 5 is an x/m frequency divider, 6 and 7 are atomic oscillators, 8 is a switch, 9 is a switching control circuit, 12 is a voltage determiner, 13 is an integration circuit, and 14 is a memory circuit.

Claims (1)

[Claims] In a system comprising a plurality of signal sources, a switch for selecting one of the plurality of signal sources, and a phase-locked circuit disposed after the switch, a phase comparator in the phase-locked circuit may A phase-locked circuit comprising: a voltage determiner that detects a predetermined level in an output voltage; an integrating circuit that integrates the output voltage of the voltage determiner; and a memory circuit that holds the output of the integrating circuit. Synchronization abnormality detection circuit.