JPH10290161A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the PLL circuit to conduct high speed tracing at rising of a clock supply section in the circuit and at restoration of an input clock and to provide an output of a stable clock against frequency fluctuation with less jitter when the clock supply section is made stable. SOLUTION: The PLL circuit has a high speed tracing PLL 1 having characteristics with a wide capture range and a short lockup time and a low speed stable PLL 2 having characteristics of less jitter and stabilizing an output of a VCOXO 3 against frequency fluctuation of an input clock, and a timer circuit 8 and a PLL selection control circuit 6 are used to allow the high speed tracing PLL 1 to conduct locking at resetting or at detection of interruption of the input clock and to select the low speed stabilizing PLL 2 so as to provide a stable output with less jitter after the lapse of locking end time, that is, after the lockup time of the high speed tracing PLL 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit, and more particularly to a PLL circuit provided in a clock supply unit in a data transmission device.

[0002]

2. Description of the Related Art In a data transmission apparatus, a PLL circuit is mounted on a clock section in the apparatus, and generates a timing used in the transmission apparatus in synchronization with a timing from a clock supply apparatus or the like in a station. Have been used to

FIG. 4 is a block diagram of a typical PLL circuit. A VCXO (voltage controlled crystal oscillator) 17 generates a clock used in a transmission apparatus. This V
The output clock of CXO 17 is frequency-divided by frequency divider 19 and becomes one input of phase comparator 15. The other input of the phase comparator 15 is supplied with a frequency-divided clock of the input clock by the frequency divider 18, and the phase comparator 15 compares the phases of both clocks. This phase comparison output has a high-frequency component removed by the loop filter 16 and becomes a voltage corresponding to the phase error component, and this voltage is used as a control voltage of the VCXO 17.

The lock-up time (the time during which the loop locks, that is, the time during which the frequency and phase are locked), the capture range (the frequency range in which the state can be locked from the unlocked state), and the lock range (the locked state), which are the characteristics of the entire PLL circuit. Frequency range that deviates from the state)
Although determined by characteristics such as the gain of the phase comparator 15 and the filter 16, the PLL circuit mounted on the clock supply unit in the transmission device basically has a loop gain of less to reduce the jitter of the output clock. Low and narrow lock range characteristics are required.

[0005] However, when the clock supply unit starts up or when the clock supply unit is restored from the absence of an input clock, the lock-up time becomes long, and it takes time to output an accurate clock. Therefore, a data error or the like occurs in the main signal transmission unit using the output clock of the clock supply unit.

In order to solve such a problem, for example, in Japanese Unexamined Patent Publication No. Hei 6-38116, a VCXO having a small conversion gain until synchronization pull-in (lockup) is used, and after a predetermined time elapses, the VCXO is synchronized. A technique is disclosed in which VCXO is switched to use a converter having a large conversion gain after pull-in is completed, thereby achieving high-speed locking and high accuracy of a PLL circuit.

[0007]

However, according to the technique disclosed in this publication, two VCXOs having different conversion gain characteristics are used.
It merely shows that the switching is performed, and it is disclosed that the switching timing is switched only after a certain time elapses by the timer.
Therefore, at the time of the switching, the loop is disturbed (equivalent to the occurrence of disturbance), and therefore, there is a disadvantage that the stability is lacking.

Accordingly, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to follow up at the time of starting up a clock supply unit in a transmission apparatus and at the time of recovery of an input clock. It is an object of the present invention to provide a PLL circuit which enables stable operation without jitter after locking, and enables smooth transition from a high-speed following state to a locked state.

[0009]

According to the present invention, there is provided a first phase locked loop which forms a loop during a steady operation, and a first phase locked loop which has a higher speed and a shorter lockup time than the first phase locked loop. 2 phase-locked loops, and selection control means for selectively switching between the first and second phase-locked loops, wherein the selection control means switches the second phase-locked loop in response to a loop pull-in instruction. The first phase locked loop is selected and activated, and after the lapse of a predetermined time, and at the timing when the difference between the two phase comparison outputs in the first and second phase locked loops becomes substantially minimum, the first phase locked loop is selected. A PLL circuit characterized by the following is obtained.

The selection control means includes a timer means for measuring the predetermined time in response to the loop pull-in instruction, and a difference between the two phase comparison outputs in the first and second phase locked loops being minimized. And means for performing switching in accordance with the detection output and the time output by the timer means.

The operation of the present invention is described below. At the time of start-up or restarting after a clock is cut off, a PLL capable of high-speed follow-up with a large gain is operated. Selection switching control to operate the PLL of FIG. By doing so, a stable PLL circuit that performs high-speed tracking and has no jitter can be obtained.
By setting the switching timing of L to a timing at which the difference between the phase comparison outputs in both PLLs becomes substantially minimum, a stable operation without disturbance of the system can be achieved even at the time of switching.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, VCXO3 is an input voltage Vi.
Is an oscillator having the characteristic of f (vi), and outputs a frequency of fo at the time of v0. Filter is 2
Absorbs high frequency components when switching the type of PLL. P
The LL circuit switching selector 5 switches the output of the high-speed tracking type PLL 1 and the output of the low-speed stable type PLL 2 under the control of the PLL circuit selection control circuit 6.

The high-speed tracking type PLL 1 has a wide capture range and a short lock-up time. The comparator 12 constituting the PLL 1 is a comparator having a high comparison frequency and a wide capture range characteristic, and the filter 10 is a loop filter having a high gain (gain) and a short lock-up time characteristic. .

The low-speed stable PLL 2 has a characteristic that the lock range is narrow, the gain is low, and the holding function is high (the lock-up time is long). The phase comparator 13 constituting the PLL 2 performs comparison at a low comparison frequency and has a narrow lock range, and the filter 11 has a low gain and a large time constant.

The input clock disconnection detecting circuit 9 detects the disconnection of the input clock fi and notifies the high-speed lockup timer circuit 8 of the disconnection information. The high-speed lock-up timer circuit 8 has a timer that counts a time equal to the lock-up time of the high-speed tracking type PLL 1 (time sufficient for the PLL 1 to lock).
A signal of (reset signal + lock-up time of high-speed tracking type PLL1) or a signal of (clock interruption duration + lock-up time of high-speed tracking type PLL1)
Output to the circuit selection control circuit 6.

In the timing extraction circuit 7, the P of each PLL
From the pulse output by C (phase comparator), a timing having the least difference in voltage is extracted, and the timing is notified to the PLL circuit selection control circuit 6.

The reason why the timing having the least difference between the pulse voltages is extracted is as follows. That is, each of the phase comparison output pulses is converted into a DC by the loop filters 10 and 11 to generate a control voltage of the VCXO. When the level difference between the pulses is minimum, the voltage having the least difference in the DC level by the loop filter is obtained. Is obtained, the difference between the control voltages of VCXO is minimized at the time of switching, and switching can be performed stably. Therefore, in this case, the loop filter 1
It is also possible to detect the level difference between the output voltages of 0 and 11 and to switch the output voltage at the minimum.

The PLL circuit selection control circuit 6 controls the switching selector 5 for switching between the high-speed tracking type PLL 1 and the low-speed stable type PLL 2 based on the signal from the timing extraction circuit 7 and the signal from the timer circuit 8.

The frequency dividers 20 to 23 generate loop frequencies used in the respective PLLs.

The operation of the block shown in FIG. 1 will now be described with reference to FIGS.
This will be described with reference to the timing chart of FIG. FIG. 2 is a timing chart showing the operation at the time of reset, that is, at the time of start-up of the package of the transmission device in which the PLL circuit is mounted. FIG. 3 is a timing chart when the input clock of the package in which the PLL circuit is mounted is cut off.

The detailed operation of the present invention will be described with reference to FIG. First, at the time of startup, a reset signal as shown in FIG. 2A is input to the high-speed lock-up timer circuit 8 from a clock supply unit in the device. In the timer circuit 8, a signal indicating the selection of the high-speed tracking PLL 1 is input to the PLL circuit selection control circuit 6 during the reset time and the lock-up timer of the high-speed tracking PLL 1. That is, the timer circuit 8 outputs the reset signal to the high-speed tracking type PL.
This means that it has recovery protection for the lock-up time of L1.

The PLL circuit selection control circuit 6, which has received the instruction to select the high-speed tracking type PLL 1 from the timer circuit 8, forcibly sends a control signal to the PLL circuit switching selector 5 to select the high-speed tracking type PLL 1 regardless of the timing. Send out.

As shown in FIG. 2E, while the high-speed tracking type PLL 1 is in the selected state, it operates as a PLL circuit having a short lock-up range and a high gain. However, if the gain remains high, it is impossible to output a stable fo against the jitter of the input clock and a sudden change (step input). Then, switching to a low-speed stable PLL 2 having a narrow lock range and a low gain is performed to stabilize the entire PLL circuit. That is, the high-speed tracking type PLL circuit selection time is deleted by the timer circuit 8, and the low-speed stabilizing PLL
The signal indicating the selection of 2 is input to the PLL circuit selection control circuit 6.

However, immediately switching to the low-speed stable type PLL circuit causes an unnecessary transient response to the VCXO, so that the timing extracting circuit 7 has a timing with a relatively small voltage difference, for example, as shown in FIG. Thus, the timing at which the output of each PC becomes low level is extracted, and the PLL circuit selection control circuit 6 uses the timing signal to
The switching control signal is transmitted to the selector 5 and the low-speed stable PL
Switching to the L circuit 2 is performed to switch the characteristics of the entire PLL circuit.

The operation of the high-speed tracking type PLL 1 will be described. At the time of reset or at the time of reset release, the phase and frequency of the input clock fi and the output fo of the VCXO3 are different. The input clock is divided by the frequency divider 20 into 1 / a
The frequency is divided to generate a comparatively fast comparison frequency fpi, which is input to the phase comparator 12, and the other input of the phase comparator 12 is obtained by dividing the output fo of the VCXO3 by 1 / c by the frequency divider 22. Enter fpo.

In the phase comparator 12, the input clock and VC
The phase of the output of the XO3 is compared. A phase comparator having a wide capture range for the initial start-up is selected, and setting is performed so that the pull-in is performed even if there is a considerable difference in the frequency. Before the pulse including the phase difference (frequency difference) generated by the phase comparator 12 is input to the VCXO 3, the pulse is passed through a filter to remove a comparison frequency component and the like. And increase the change in the output of VCXO3. Further, since the comparison frequency is high, high-speed pull-in is performed.

Next, the operation of the low-speed stable PLL 2 will be described. The frequency fpi obtained by frequency-dividing the input clock by 1 / a by the frequency divider 20 is further frequency-divided by 1 / b by the frequency divider 21, and a lower frequency comparison frequency is input to the phase comparator 13. The input fo of the other phase comparator 13 is connected to the output fo of the VCXO3 by the frequency divider 22.
And the loop signal divided by 1 / cd by the divider 23 is input. The output of the phase comparator 13 is passed through the filter 11. By reducing the gain of this filter, jitter is suppressed, and a stable VCXO3 output is realized.

Since the comparison frequency is low and the loop gain is low, pulling in takes a long time.
After L1 is pulled in, input clock fi and VC
Since there is almost no phase difference with the output fo of the XO3, there is no problem.

[0030]

Next, an embodiment of the present invention will be described with reference to FIG.

In FIG. 1, the high-speed tracking type PLL 1 has a characteristic that the lock-up time is 50 ms and the gain is high. The low-speed stable PLL 2 has characteristics that the lock range is narrow and the gain is low. FIG. 2 shows the state at reset, that is, this PL.
6 is a timing chart showing an operation at the time of starting up a clock package of a transmission device on which an L circuit is mounted.

The detailed operation of the present invention will be described using the start-up operation. First, at the time of startup, a reset signal as shown in FIG. 2A is input to the high-speed lock-up timer circuit 8 from a clock supply unit in the device. In the timer circuit 8, during the (reset time +50 ms), the high-speed following PL
A low-level signal indicating the selection of L1 is input to the PLL circuit selection control circuit 6. That is, the timer circuit has 50 mS recovery protection of the reset signal.

The PLL circuit selection control circuit 6, which has received the high speed tracking type PLL1 selection command signal from the timer circuit 8, forces the PLL circuit switching selector to select the high speed tracking type PLL1 regardless of the timing. Send a control signal. Therefore, as shown in FIG. 2E, during the selection state of the high-speed tracking type PLL 1, the circuit operates as a PLL circuit having a short lock-up range and a high gain.

At this high level, a stable VC against input clock jitter and sudden fluctuations (step input)
Since the output of the XO is impossible, when the high-speed PLL 1 finishes pulling in a certain amount of frequency, the lock range is switched to the low-speed stable type PLL 2 having a narrow gain and a low gain to stabilize the entire PLL circuit. I do. That is, the high-speed following PLL circuit selection time is released by the timer circuit 8, and a high-level signal indicating selection of the low-speed stabilization PLL 2 is input to the PLL circuit selection control circuit 6.

However, the instantaneous switching to the low-speed stable PLL circuit is a timing at which the voltage difference is relatively small in the timing extracting circuit 7 because an unnecessary transient response is given to the VCXO. As described above, the timing at which the outputs of both PCs are both low is extracted, and using the timing signal, the PLL circuit selection control circuit 6 sends a switching control signal to the selector 5 to switch to the low-speed stable PLL 2. Is performed, and the entire PLL circuit is switched to a PLL circuit having a stable VCXO output characteristic with less jitter.

[0036]

As described above, the PLLs having different characteristics are provided, and these are switched at the timing of the phase difference between the output pulse of the timer and the comparator, so that the high-speed pull-in at the time of startup and the pull-in after the pull-in are performed. The configuration of the clock supply unit in the transmission device that realizes stable output with less jitter becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart at the time of reset according to the embodiment of the present invention.

FIG. 3 is a timing chart when a clock is cut off in the embodiment of the present invention.

FIG. 4 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 high-speed tracking type PLL 2 low-speed stable type PLL 3 VCXO (voltage control type crystal oscillator) 4, 10, 11 filter 5 PLL circuit switching selector 6 PLL circuit selection control circuit 7 PC (comparator) output timing extraction circuit 8 Timer 9 Input clock loss detection circuit 12, 13 Phase comparator 20-22 Divider

Claims (8)

[Claims] A first phase-locked loop forming a loop during a steady operation; a second phase-locked loop having a faster lock-up time and a shorter lock-up time than the first phase-locked loop; And a selection control means for selectively switching a second phase locked loop, wherein the selection control means selectively activates the second phase locked loop in response to a loop pull-in instruction, for a predetermined period of time. A PLL circuit wherein the first phase-locked loop is selected after a lapse of time and at a timing when the difference between the two phase comparison outputs in the first and second phase-locked loops becomes substantially minimum. 2. The timer according to claim 2, wherein the selection control unit measures the fixed time in response to the loop pull-in instruction.
Detecting means for detecting a timing at which the difference between the two phase comparison outputs in the first and second phase locked loops is minimized, and means for switching in response to the detected output and the timed output by the timer means; The PLL circuit according to claim 1, further comprising: 3. The apparatus according to claim 2, wherein the detecting means is configured to detect a DC level difference between the two phase comparison outputs and detect that the difference is substantially minimized.
The PLL circuit as described in the above. 4. The PLL circuit according to claim 2, wherein said detection means is configured to detect that a level difference between comparison output pulses as the two-phase comparison output is minimized. 5. The PLL circuit according to claim 1, wherein the predetermined time is a time during which the second phase locked loop is locked. 6. The PLL circuit according to claim 1, wherein the loop pull-in instruction is an external reset signal. 7. The P according to claim 1, wherein the loop pull-in instruction is a detection signal from a clock disconnection detecting means for detecting a disconnection of an input clock signal.
LL circuit. 8. The apparatus according to claim 1, wherein the second phase-locked loop is configured to operate by a clock pulse having a higher frequency than that of the first phase-locked loop. PLL circuit.