JPH09191247A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the pull-in range. SOLUTION: A VCO 3 oscillates a signal of a frequency in response to an oscillated frequency control voltage from an LPF2. A frequency conversion section 4 multiplies or divides the frequency of the oscillated signal. A control section 13 sets a multiplication coefficient and a division coefficient. However, an initial set coefficient is given to the start of operation. Plural kinds of coefficients used for setting are stored in a 2nd memory section 10. A variable range of an oscillated frequency control voltage of the VCO 3 is stored in a 1st memory section 7 and in the case of supervision based on the entire veriable range, which a current control voltage is within the variable range, it is discriminates to be synchronizing state and when the voltage is at the outside of the variable range, it is discriminated to be an asynchronizing state. A detection section 8 detects a level from an A/D converter section 6 and a discrimination section 9 discriminated whether the level corresponds to the synchronizing state or to the asynchronizing signal state. A control section 13 changes the coefficient to the frequency conversion section 4 to be a coefficient bringing the state within the variable range from the initial setting coefficient when the detected level indicates the outside of the variable range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit (phase locked loop circuit), and more particularly to a PLL circuit that mainly generates a system clock signal used for digital processing of video signals, The present invention relates to a PLL circuit having an expanded pull-in range and a system clock with high stability.

[0002]

2. Description of the Related Art Conventionally, PLL circuits have been used in various fields, and one of them is generation of a system clock used for digital processing of video signals. FIG. 4 is a basic configuration diagram of a PLL circuit that generates the system clock. The input horizontal synchronizing signal Sh is used as a reference signal, and the reference signal Sh and the comparison signal from the frequency divider 24 are compared in phase by the phase comparator 21. The phase difference signal obtained by the in-phase comparison is converted into an oscillation frequency control voltage by an LPF (low pass filter) 22. The VCO (voltage controlled oscillator) 23 is controlled by the oscillation frequency control voltage from the LPF 22 and outputs the system clock CK. The output CK of the VCO 23 is frequency-divided (1 / K) by the frequency divider 24 and fed back to the phase comparator 21 as a comparison signal. Output of VCO23 by this closed loop
CK becomes a signal synchronized with the input horizontal synchronization signal, and this synchronization is maintained under high stability.

[0003]

However, the above-mentioned PLL is used.
In the case of the circuit, the pull-in range for the frequency change of the reference signal is related to the frequency variable width of the VCO 23 and cannot be pulled in beyond the variable width. On the other hand, under the diversification of video signals, video signals of various specifications having different horizontal frequencies are input to the display monitor. Therefore, when these video signals are digitally processed, it is necessary to generate a system clock according to the horizontal frequency, but if the horizontal frequency exceeds the frequency variable width of the VCO 23, the required clock cannot be obtained. Becomes

On the other hand, as one of the methods of expanding the pull-in range, there is a method of configuring the VCO with an LC.
This method has a drawback in that the output frequency becomes less stable as the variable range is expanded, which makes it unsuitable for digital systems that require high accuracy. The present invention has been made from such a background, and an object of the present invention is to provide a PLL circuit capable of obtaining a system clock having a wide range of frequencies while maintaining the stability of the VCO.

[0005]

SUMMARY OF THE INVENTION The present invention is a voltage controlled oscillator controlled by an oscillation frequency control voltage to oscillate a clock signal, and a frequency of a clock signal from the voltage controlled oscillator multiplied or divided to obtain a required frequency. , A frequency converter that outputs the clock signal, a frequency divider that divides the clock signal output from the frequency converter and outputs as a comparison signal, and an input horizontal synchronization signal as a reference signal and the reference signal and the frequency divider. A phase comparator that compares the phase of the comparison signal from the frequency divider, a low-pass filter that converts the signal related to the phase difference from the phase comparator to the oscillation frequency control voltage, and an oscillation frequency control voltage from the low-pass filter. An A / D conversion unit for converting into digital data, a first memory unit for storing a variable range of an oscillation frequency control voltage of the voltage controlled oscillator, Based on the detection unit for detecting the level of the digital data from the / D conversion unit and the variable range of the oscillation frequency control voltage of the first memory unit, whether the level detected by the detection unit is within the variable range. , Or a level outside the variable range, a second memory unit storing a plurality of types of coefficients including an initial setting coefficient for the frequency conversion unit, and the A / D conversion unit. A control unit that controls the frequency conversion unit, the first memory unit, the second memory unit, the detection unit, and the determination unit based on the conversion data, and the conversion data from the A / D conversion unit is oscillated. The present invention provides a PLL circuit in which when the frequency control voltage is out of the variable range, a coefficient for the frequency converter is selected from the other coefficients from the initial setting coefficient.

[0006]

Operation: The phase comparator and the low-pass filter are the conventional PL
The operation is similar to that of the L circuit. The voltage controlled oscillator oscillates a system clock signal having a frequency according to the oscillation frequency control voltage from the low pass filter. The frequency of the signal oscillated by the voltage controlled oscillator is multiplied or divided by the frequency converter. The control unit sets the multiplication coefficient and the frequency division coefficient for the frequency conversion unit. However, an initial setting coefficient is given at the initial stage of operation. A plurality of types of coefficients used for the above setting are stored in the second memory unit.

The variable range of the oscillating frequency control voltage of the voltage controlled oscillator is stored in the first memory section. If the present control voltage is within the variable range when monitoring based on the entire variable range. Synchronous state, asynchronous state if out of the variable range. The level of the converted data from the A / D conversion section is detected by the detection section, and the determination section determines whether the same level is in the synchronous state or the asynchronous state. The control unit is A / D
When the conversion data from the conversion unit is outside the variable range of the oscillation frequency control voltage, the coefficient for the frequency conversion unit is within the variable range from the initial setting coefficient based on the data related to the coefficient of the second memory unit. Change to a coefficient.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a main part showing an embodiment of a PLL circuit according to the present invention, and FIG. 2 is an operation flowchart for explaining FIG. In FIG. 1, Sh is a horizontal synchronizing signal as a reference signal (hereinafter referred to as “reference signal Sh”), 1 is a phase comparator for performing a phase comparison between the reference signal Sh and the comparison signal from the frequency divider 5, 2 Is a low-pass filter (hereinafter referred to as “LPF”) that converts the phase difference signal from the phase comparator 2 into an oscillation frequency control voltage, and 3 is a voltage that is oscillation controlled by the oscillation frequency control voltage from the LPF 2 and that oscillates a clock signal. The controlled oscillator (hereinafter referred to as "VCO") 4 is composed of a multiplier 4a for multiplying the frequency of the clock signal oscillated by the VCO 3 and a frequency divider 4b for frequency division, and locked (synchronized) with the reference signal Sh. System clock signal CK (hereinafter,
A frequency conversion unit for outputting a "clock signal"), 5
Is a frequency divider that divides the clock signal CK from the frequency conversion unit 4 and outputs it as a comparison signal.

Reference numeral 6 is an A / D converter for converting the oscillation frequency control voltage from the LPF 2 from analog to digital data, and 7 is stored for a plurality of types in which the variable range of the oscillation frequency control voltage of the VCO 3 is divided stepwise. 1 is a first memory unit, 8 is a detection unit that detects the level of digital data from the A / D conversion unit 6, and 9 is based on the data related to the variable range of the oscillation frequency control voltage of the first memory unit 7. A discriminating unit that discriminates whether the level detected by the detecting unit is a level within a predetermined variable range, a level lower than the predetermined variable range, or a level higher than the predetermined variable range, 10 is an initial setting coefficient for the frequency converting unit 4, A second memory unit storing a plurality of types of coefficients, 11 is a counter that counts the frequency of the reference signal Sh, and 12 is a frequency division ratio set in the frequency divider 5 for the reference signal Sh. The third memory unit 13 is a control unit that controls the frequency conversion unit 4, the first memory unit 7, the detection unit 8 and the determination unit 9, the second memory unit 10, and the like.

The specific contents of the first memory section 7 will be described below. The first memory unit 7 stores data relating to a plurality of types of ranges. This range means a range to be monitored, and if these are referred to as a first range, a second range, ..., And the like, the first range is defined as the narrowest range near the center of the VCO3 frequency variable range. And the second range is the same as the first
The range that is wider than the range and the third range are a plurality of types of data in which the range is expanded stepwise, such as a range that further widens the second range. For example, if the variable range of the oscillation frequency control voltage of the VCO 3 is in the range of 0 to 5V, and if its stable operation range is 2 to 3V near the center (2.5V), this "2 to 3V" is the first range. The second range is defined by expanding the range to "1.5 to 3.5 V" with respect to the first range, and hereinafter referred to as "1 to 4 V" and "0.5 to 4.
"5 V" ... Expanded stepwise as the third range, the fourth range ... The reason for dividing the range in this way is to bring the locked state as close as possible to the center of the frequency variable range of the VCO 3 to ensure stable operation.

The operation of the present invention will be described below. The ST number in parentheses in the following description indicates each step in the operation flowchart of FIG. When the operation of this circuit is started, the control unit 13 uses the initial setting coefficient of the second memory unit 10 to multiply the multiplier 4a.
And frequency divider 4b are initialized (ST1). In principle, this initial setting coefficient can be arbitrarily set, but if the frequency of the reference signal Sh is within the original variable frequency range of the VCO 3, it is not necessary to multiply or divide its output frequency. Since it may be operated as a PLL circuit having the same configuration as the conventional one, the multiplication coefficient (M) of the multiplier 4a and the frequency divider 4b.
The frequency division coefficient (1 / N) may be set to "1".

Now, assuming that a reference signal Sh of a certain frequency is input to the phase comparator 1 (ST2), the oscillation frequency control voltage is A through the phase comparator 1 and LPF2 having the same function as that of the conventional PLL circuit. It is sent to the / D conversion unit 6. Same A / D
The converter 6 converts the oscillation frequency control voltage into digital data, sends it to the detector 8 via the controller 13, and the detector 8 detects its level (ST3). The control unit 13 monitors the level detected by the detection unit 8. This monitoring range is set to the narrowest first range at the first stage, and the frequency conversion unit locks in this range. Four
Is given, and if this is not possible, the process moves to the next stage, which is the second range, and then the third range. As described above, it is the above-mentioned first memory unit 7 that defines this range.

As described above, the A / D converter 6 outputs the reference signal.
When the conversion data corresponding to Sh is input, the level detected by the detection unit 8 is based on the first range, that is, the range of “2 to 3 V” (cited below in the above example) when the above example is cited. The determination unit 9 determines whether or not it is within the first range (ST4). If the result of this determination is within the first range, the current coefficient (initial setting) is maintained (ST4-Y). Being within this range means that the VCO 3 is in the locked state near the center within the variable range, and it is not necessary to change the current setting coefficient for the frequency conversion unit 4. On the other hand, when the detection level is not in the first range, it is determined whether the level is on the lower side or the higher side than the first range (ST5). In this determination, if the detection level is on the lower side of the first range, the coefficient is lowered (ST6), and if it is on the higher side, the coefficient is raised (ST7).

This coefficient is composed of a multiplication coefficient (M) for the multiplier 4a and a frequency division coefficient (1 / N) for the frequency divider 4b, and these two are combined to give (M / N) = L. To Hereinafter, this "L" is referred to as the frequency conversion unit 4
"Coefficient" given to. Therefore, the second memory unit 10
A plurality of types of coefficients (L1, ... Ln) are stored in the memory, the coefficients are sequentially read out from the lowest coefficient, and the frequency conversion unit 4 is set. Then, for each coefficient setting, it is determined whether or not the lock is made within the first range which is the current monitoring range (decision unit 9) (ST8), and if locked, the coefficient at that time is set (ST8-
Y). On the other hand, in the case of monitoring in the first range, the following situation may occur. In FIG. 3, (A) shows the output of the frequency conversion unit 4 when the coefficients L1 and L2 are given with the first range as the monitoring range. As described above, the first range is the narrowest monitoring range. Therefore, when the coefficient L1 is not locked within the first range and the coefficient is raised to L2, a discontinuous blank range 21 may occur between the two.

When the frequency to be set is in this blank range, the frequency is out of the monitoring range and the coefficient cannot be determined.
Therefore, when not locking within the first range (ST8-
N), the control unit 13 expands the monitoring range to the second range (1.5
~ 3.5 V) (ST9). In this monitoring range, the coefficient is increased from the lower side, and it is judged for each coefficient whether or not it is locked within the second range (judgment unit 9) (ST10). If locked, set the coefficient at that time (ST10-Y).
If the lock does not occur even within this second range, the range is expanded to the third range (1 to 4 V) (ST10-N, ST
9), monitor whether or not they are locked while setting the respective coefficients. After that, the monitoring range is expanded to the set range. Since the range after the second range has a wide monitoring range, the blank range as shown in FIG. 3A does not occur (and the range is set as such).

In FIG. 3B, the monitoring range is the third range (1 to 1).
4V), and shows the output of the frequency conversion unit 4 when the coefficients L1 and L2 are given. As shown in the figure, the monitored ranges are overlapped, and there is no blank range as in the case of FIG. As a result, the coefficient is not fixed, and the VCO 3 is locked as long as it remains within the variable range of the VCO 3 itself (ST10-Y). As described above, since the monitoring range is locked while gradually expanding from the narrow side, the oscillation operation of the VCO 3 can be brought close to the center of the variable range, and a more stable operation state can be achieved.

Next, the frequency division ratio of the frequency divider 5 will be described.
If the horizontal frequency of the input signal changes, the frequency divider 5
If the frequency division ratio is also not adjusted, the phase comparison by the phase comparison unit 1 cannot be performed accurately. This frequency division ratio can be predetermined for the frequency of the reference signal Sh. So counter 11
The frequency of the reference signal Sh is counted at, the data of the corresponding frequency division ratio is read from the third memory unit 12 based on the count result, and the frequency division ratio of the frequency divider 5 is set with the same data. The control unit 13 controls the frequency conversion unit 4 to control the frequency division ratio setting.
This is done together with the coefficient setting of. Thereby, the phase comparison of the phase comparison unit 1 is properly performed.

[0018]

As described above, according to the present invention, in the PLL circuit for generating the system clock used for digital processing of the video signal or the like, the frequency converter for multiplying or dividing the frequency of the VCO oscillation output is provided. Moreover, since the multiplication or frequency division coefficient is made variable, the pull-in range of the PLL circuit can be expanded. Further, the coefficient setting is also set and controlled so as to be locked in the stable region of the VCO. This makes it possible to obtain a stable system clock having a wide frequency range with one VCO even when digitally processing video signals of various specifications having different horizontal frequencies and the like in a wide range.
From the above, the present invention contributes to improving the performance of the PLL circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is an operation flowchart for explaining FIG.

FIG. 3 is a diagram for explaining the present invention, and is a relational diagram of a frequency converter output with respect to a coefficient.

FIG. 4 is a principal block diagram showing a basic configuration example of a conventional PLL circuit.

[Description of Codes] Sh Horizontal sync signal (reference signal) 1 Phase comparator 2 LPF 3 Voltage controlled oscillator 4 Frequency converter 4a Multiplier 4b Divider 5 Divider 6 A / D converter 7 First memory unit 8 Detection unit 9 Discrimination unit 10 Second memory unit 11 Counter 12 Third memory unit 13 Control unit

Claims (5)

[Claims] 1. A voltage controlled oscillator controlled by an oscillation frequency control voltage to oscillate a clock signal, and a frequency of a clock signal from said voltage controlled oscillator is multiplied or divided.
A frequency converter that outputs a clock signal of the required frequency,
A frequency divider that divides the clock signal output from the frequency conversion unit and outputs it as a comparison signal and the input horizontal synchronizing signal as a reference signal are used as a reference signal to perform a phase comparison between the reference signal and the comparison signal from the divider. A phase comparator, a low-pass filter that converts a signal related to a phase difference from the phase comparator into the oscillation frequency control voltage, and an A / D conversion unit that converts the oscillation frequency control voltage from the low-pass filter into digital data. A first memory unit that stores a variable range of the oscillation frequency control voltage of the voltage controlled oscillator; a detection unit that detects the level of digital data from the A / D conversion unit; and the first memory unit. A discriminating unit for discriminating whether the level detected by the detecting unit is within the variable range or outside the variable range based on the variable range of the oscillation frequency control voltage of A second memory unit that stores a plurality of types of coefficients including initial setting coefficients for the frequency conversion unit, and the frequency conversion unit, the first memory unit, and the first memory unit based on the conversion data from the A / D conversion unit. And a control unit for controlling the detection unit and the determination unit, the A / D
A PLL circuit, wherein when the conversion data from the conversion unit is out of the variable range of the oscillation frequency control voltage, a coefficient for the frequency conversion unit is selected from other coefficients from the initial setting coefficient. 2. The selection of another coefficient from the initial setting coefficient is such that the coefficient is lowered when the detection level is lower than the level within the variable range, or is increased when the detection level is higher than the level within the variable range. The PLL circuit according to claim 1, wherein 3. The storage data of the first memory unit is a range defined based on the center of the variable range of the oscillation frequency control voltage, and is gradually widened from the narrowest range. The conversion data from the A / D converter is monitored with the narrowest range as a reference in the initial stage of operation, and when the conversion data is outside the same reference range, the plurality of types 2. The PLL circuit according to claim 1, wherein the coefficient setting control is performed by sequentially shifting to a wider range and locking each range. 4. The PLL circuit according to claim 1, wherein the frequency conversion unit includes a multiplier and a frequency divider. 5. A counter for counting the frequency of the reference signal and a third memory section for storing a frequency division ratio setting control signal of the frequency divider for the frequency are provided, and count data from the counter and a third data section are provided. 2. The PLL circuit according to claim 1, wherein the control unit sets the frequency division ratio of the frequency divider based on the data stored in the second memory unit.