JP2000049604A - Phase locked loop device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase locked loop device whose pull in time does not become long and in which a capture range can be enlarged. SOLUTION: A phase locked loop device is provided with a plurality of phase locked loops 1, 2 and 3, a decision circuit 10 deciding the phase locked loop whose phase is locked the most in a plurality of phase locked loops and outputting the number information and a selector 11 selecting and outputting the output signal of VCO in the phase locked loop circuit corresponding to number information. Thus, a PLL device whose pull in time is similar to that of individual PLL circuits as a whole and which has a large capture range can be realized by using a plurality of PLL circuits different in the capture ranges.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase locked loop device, and more particularly to a phase locked loop device capable of expanding a capture range.

[0002]

2. Description of the Related Art Conventionally, a phase locked loop circuit (hereinafter referred to as a PLL) has been disclosed.
Means for expanding the capture range of the circuit) include a method of optimizing the gain and damping factor of the PLL servo system, and a method of adding a phase and frequency comparison mode to the phase error detector.

[0003]

In the conventional PLL circuit as described above, for example, the former has a problem that the range of expanding the capture range is limited, and the latter has a problem that the capture range is widened but the self-propelled center is increased. If the frequency and the frequency of the received signal are largely shifted, there is a disadvantage that the phase pull-in time becomes long. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art, and to provide a phase-locked loop device capable of increasing a capture range without increasing a pull-in time.

[0004]

According to the present invention, in a phase locked loop apparatus, a plurality of phase locked loop means and, among the plurality of phase locked loop means, a phase locked loop means having the highest phase synchronization are determined. And determining means for outputting the number information and selecting means for selecting and outputting the output signal of the oscillating means of the phase-locked loop means corresponding to the number information. According to the present invention, by using a plurality of PLL circuits having different capture ranges, the pull-in time as a whole is the same as that of each PLL circuit, and a PLL having a large capture range is obtained.
L device is feasible.

[0005]

Embodiments of the present invention will be described below in detail. FIG. 1 is a block diagram showing a configuration of a PLL circuit to which the present invention is applied. In this embodiment, three PLL blocks PLLA1, PLLB2, PLLC3
You are using Frequency synthesizers 4, 5, and 6 are provided for each of the PLL blocks, and a clock signal from a clock signal generation circuit (not shown) is input evenly.
The output signals from the frequency synthesizers 4, 5, and 6 are
It is supplied as a reference signal for the L block 5. As will be described later, the frequencies of the reference signals output from the frequency synthesizers 4, 5, and 6 are set to different values corresponding to the free running frequencies of the PLL blocks 1, 2, and 3 alone.

The input signal is composed of three PLL blocks 1, 2,.
3 are equally input to the phase comparators 12, 13, 14. Each of the PLL blocks 1, 2, and 3 is synchronized with an input signal by an external control signal GATE, or
Whether to synchronize with the reference signals output from the frequency synthesizers 4, 5, and 6 provided for each LL block is switched.

The output of each of the phase comparators 12, 13, and 14 is limited to a band required for PLL control by loop filters 15, 16, and 17, and output to VCOs (voltage controlled variable frequency oscillators) 18, 19, and 20. Is entered. VCO 18, 1
The output signals 9 and 20 are output to the outside and returned to the phase comparators 12, 13 and 14, so that phase servo is performed, thereby functioning as a PLL. In addition, for the details of each block of the PLL circuit, a known arbitrary circuit system can be adopted.

The outputs of the loop filters 15, 16, and 17 are branched, and the corresponding envelope detectors 7,
8 and 9 are input. Envelope detectors 7, 8, 9
Is a circuit that generates and outputs an envelope signal of the phase error signal output from the loop filters 15, 16, and 17, and specifically includes a detection circuit, for example, a rectifier circuit and a low-pass filter circuit.

The envelope signals output from the envelope detectors 7, 8, and 9 are input to a level comparator 10, where the signal having the lowest envelope level, ie, the signal having the lowest envelope level, is output. A signal whose phase is synchronized is determined and selected. Then, the level comparator 10 outputs, for example, a 2-bit signal indicating the number of the selected PLL circuit.

The selector 11 outputs a signal having a low envelope level (most P level) based on an output signal from the level comparator 10.
LL synchronized) is selected, and an output signal is output. A latch circuit is built in for the selection signal from the level comparator 10, and an externally or internally generated TRI
The G signal is used. This TRIG signal is, for example, GA
This is a latch pulse that rises a predetermined time after the rise of the TE signal, and controls the selector 11 by latching the output signal of the level comparator 10. Incidentally, the latch circuit may be omitted, and the selector 11 may always be controlled by the output signal of the level comparator 10.

FIG. 2 is a waveform diagram showing an example of the output signal waveform of each loop filter and envelope detector of FIG. The horizontal axis indicates the time after the GATE signal is switched so as to be synchronized with the input signal, and the vertical axis indicates the phase error signal. The middle line of the vertical axis is the point where the phase error (error voltage) is zero.

The output signal A1 of the PLLA loop filter 15 indicates a state in which the settling is long (insufficient synchronization).
The output signal B1 of the LB loop filter 16 shows a state of good synchronization, and the output signal C1 of the PLL loop filter 17 shows a state of divergence.

The right side of FIG. 2 shows an example of the output signal waveform of each envelope detector when the left side waveform is input. A TRIG signal is given after a predetermined time, for example, a pull-in time of each PLL circuit, from the GATE signal, and a signal having the smallest value of the envelope signal at this time, PLLB is selected here, and the output signal of the VCO 19 of the PLLB is output to the outside. Is output.

FIG. 3 is an explanatory diagram showing the relationship between each PLL circuit and the capture range of the entire device. PLLA
The free-running frequency of the VCO 18 is fa, and the VCO 1 of the PLLB is
9, the free-running frequency of PLLC VCO 20 is fc, the capture range of PLLA is La, P
Assuming that the LLB capture range is Lb and the PLL capture range is Lc, the capture ranges of the PLL circuits 1, 2, and 3 are set such that the ends of the ranges overlap on the frequency axis as shown in the figure. Further, each of the frequency synthesizers 4, 5, and 6 in FIG. 1 has a free running frequency fa, fb, f
c, and in the standby state, each P
The VCO of the LL circuit is locked to fa, fb, fc.

By setting the capture range of each PLL circuit in this way, the input signal can be
If the PLL circuit is within the capture range of the L circuit, the PLL circuit locks within a predetermined time. Therefore, the characteristics of the entire PLL circuit of FIG. 1 are such that the pull-in time is the same as that of each PLL circuit, and the capture range is as shown in FIG. As shown by Lt in FIG.

Although the embodiments of the present invention have been disclosed above, the present invention may have the following modifications. In the embodiment, an example in which three PLL circuits are used has been disclosed.
The number of LL circuits is arbitrary. Further, in the embodiment, the example in which the ends of the respective capture ranges overlap is disclosed, but the overlap width is arbitrary, and the larger the overlap width, the smaller the width of the entire capture range,
Retraction time is shorter. The capture ranges of the individual PLL circuits do not need to be equal, but may be different.

Furthermore, a first PLL circuit having a narrow capture range but a short pull-in time and a second PLL circuit having a wide capture range but a long pull-in time are combined, for example, by using respective free-running frequencies. And the capture range of the first PLL circuit is
A configuration that is completely included in the capture range of the PLL circuit is also conceivable. With this configuration, the input signal near the free-running frequency can be locked in a short time, and the signal far from the free-running frequency can be locked although it takes time.

[0018]

As described above, in the present invention,
By setting the capture ranges of a plurality of PLL circuits so as to overlap each other and selecting a locked PLL circuit from the settling state of the phase error signal from the phase error detector during the period after the phase lock command, the entire circuit The effect is that the capture range can be widened. In this case, the settling time is extended,
Or PLL that increases PLL jitter
There is also an effect that basic performance is not impaired.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit to which the present invention is applied.

FIG. 2 is a waveform diagram showing an example of an output signal waveform of each loop filter and envelope detector of FIG. 1;

FIG. 3 is an explanatory diagram showing a relationship between each PLL circuit and a capture range of the entire device.

[Explanation of symbols]

1, 2, 3 PLL circuit, 4, 5, 6 frequency synthesizer, 7, 8, 9 envelope detector, 10 level comparator, 11 selector, 12, 13, 14 phase comparator, 15, 16 , 17 ... Loop filter, 18, 1
9, 20… VCO

Claims (3)

[Claims] 1. A plurality of phase-locked loops to which an input signal is supplied, and a phase-locked loop having the highest phase synchronization among the plurality of phase-locked loops is determined, and the number information is output. A phase-locked loop, comprising: a determination unit that performs, based on number information of the determination unit, a selection unit that selects and outputs an output signal of an oscillation unit of the phase-locked loop unit corresponding to the number information apparatus. 2. The method according to claim 1, wherein the determining means includes: an envelope detecting means for generating an envelope signal of phase error information of each of the phase locked loop means; and a phase most synchronized based on output values of the plurality of envelope detecting means. 2. The phase-locked loop device according to claim 1, further comprising a level comparison unit that outputs number information of the locked loop circuit. 3. The plurality of phase-locked loops are arranged such that at least one end of each capture range on the frequency axis overlaps with the end of the capture range of another phase-locked loop. The phase-locked loop device according to claim 1, wherein