JP2839949B2 - PLL circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit used in a storage device or the like that decodes and reproduces a data signal recorded on a medium.

[Prior Art] For example, in a time disk device or the like, a PLL circuit used for reproducing a recorded data signal generally has a configuration shown in FIG.

In FIG. 7, a phase comparator 1 compares a data signal 5 with a phase of an oscillation clock 10 output from a voltage-controlled oscillator (hereinafter referred to as a voltage-controlled oscillator) 4, and determines that the phase of the data signal 5 is the phase of the voltage-controlled oscillator clock 10. If it is more advanced, it outputs the INC signal 6 for that time, and conversely, if it is late, it outputs the DEC signal 7.

Upon receiving the INC signal 6 and the DEC signal 7, the charge pump 2 performs a charging operation according to the INC signal 6, and performs a discharging operation according to the DEC signal 7. Loop filter 3 is
The output 8 of the charge pump 2 is integrated and smoothed to generate a voltage-controlled oscillator control voltage 9.

The voltage controlled oscillator 4 outputs a voltage controlled oscillator clock 10 having a frequency corresponding to the voltage controlled oscillator control voltage 9.
In this way, the PLL circuit operates to make the phase of the voltage controlled oscillator clock 10 coincide with the phase of the data signal 5.

By the way, the phase comparator 1 may use a frequency phase comparator in addition to a normal phase comparator.

The frequency phase comparator is used when pulling in synchronization, etc.
For example, as shown in FIG.
It can be composed of a NAND 24 and a frequency dividing circuit 21.

The data signal 5 is input to the CK terminal of the flip-flop 22, and a voltage is applied to the CK terminal of the flip-flop 23 by the frequency dividing circuit 21 (here, a frequency dividing circuit 3) so that the frequency of the input data signal 5 becomes equal to that of the input data signal 5. A divided clock 25 obtained by dividing the control oscillator clock 10 is input.

 The operation of this circuit will be described with reference to FIG.

If the phase of the data signal 5 is ahead of the frequency-divided clock 25, first, INC
The signal 6 rises and the rising edge of the divided clock 25 causes DE
As the C signal 7 rises, the NAND output 26 goes low, the flip-flops 22 and 23 are reset, and the INC signal 6 and the DEC signal 7 fall.

Conversely, when the phase of the data signal 5 is behind the frequency of the divided clock 25, the DEC signal 7 rises at the rising edge of the divided clock 25, the INC signal 6 rises at the rising of the data signal 5, and the NAND output 26 is “L”
Level, the flip-flops 22 and 23 are reset, and the INC signal 6 and the DEC signal 7 fall.

The frequency dividing ratio of the frequency dividing circuit is determined by the data signal pattern (sync pattern) at the time of synchronization pull-in, and differs depending on the recording code system. 2-7 RLLC sync pattern is “1000100
0 ... "and the 1-7RLLC sync pattern is a" 10001000 ... "3T pattern.

For this reason, the frequency divider circuit divides the frequency by 4 in 2-7RLLC and 1-7RLLC.
LC divides by 3.

[Problem to be Solved by the Invention] In the above-described conventional technology, only one of a normal phase comparator and a frequency phase comparator is provided as a phase comparison unit used at the time of synchronization pull-in.

For this reason, the phase synchronization characteristic may become unstable depending on the quality of the input data signal.

That is, for example, when a normal phase comparator is used for synchronization pull-in, it is easy to mislock to the higher order frequency of the sync pattern, and if the frequency variable range of the voltage controlled oscillator is limited to prevent the mislock, the capture range becomes narrow. There were problems such as becoming.

In addition, when the frequency phase comparator is used for synchronization pull-in, it is difficult to mislock and the capture range is wide,
There was a problem in comparison characteristics when data was missing or boiling occurred.

Therefore, the present invention provides a PLL capable of exhibiting good phase synchronization characteristics for data signals having different qualities.
A first object is to provide a circuit.

It is a second object of the present invention to provide a PLL circuit applicable to a plurality of different encoding schemes, particularly, both the recording encoding schemes of 1-7RLLC and 2-7RLLC.

[Means for Solving the Problems] In order to achieve the first object, the present invention provides a PLL circuit including a phase comparator and a frequency phase comparator as a phase comparison unit, A phase synchronization method characterized in that either a phase comparator or a frequency phase comparator is used as a phase comparator according to quality.

Further, the present invention provides a PLL for achieving the first object.
A first PLL circuit, comprising: a phase comparison unit and a frequency phase comparator which can be used by switching any one of them as a phase comparison unit.

Further, the present invention, in order to achieve the second object, provided with a frequency phase comparator, a PLL circuit used for reproduction of a data signal recorded on a recording medium, wherein the frequency phase comparator, A variable frequency divider that can divide the input oscillation clock by a plurality of frequency division ratios, and a frequency / phase comparator that compares the frequency and phase of the frequency-divided oscillation clock divided by the variable frequency divider with the input synchronized signal A second PLL circuit is provided.

In the first PLL circuit, the frequency phase comparator includes a variable frequency dividing circuit capable of dividing the oscillation clock by a plurality of frequency dividing ratios, and a frequency-divided oscillation clock divided by the variable frequency dividing circuit. A frequency-phase comparison circuit for comparing the frequency and the phase with the signal to be synchronized may be provided.

In addition, the present invention also provides at least a PLL LSI having a phase comparator, a charge pump, and a voltage-controlled oscillator built therein, wherein one of the phase comparator output signal and an external input signal is selectively provided. A first PLL LSI having a selector for outputting the charge pump input signal is provided.

Further, the present invention provides a second PLL LSI which incorporates at least a first or second phase comparison unit and is used for reproducing a data signal recorded on a recording medium.

Further, the present invention further provides the first or second PL.
There is also provided a storage device having the L circuit or the first or second PLL LSI, particularly a magnetic disk device.

[Operation] According to the phase synchronization method according to the present invention, at the time of synchronization pull-in, either the phase comparator or the frequency phase comparator is used as the phase comparison unit in accordance with the quality of the signal to be synchronized, so that there is much data loss. In the case of a data signal, the movement synchronization characteristic can be stabilized using a phase comparator.

Further, according to the first PLL circuit of the present invention, the phase synchronization method can be favorably realized.

In the second PLL circuit according to the present invention, since the variable oscillation circuit can divide the input oscillation clock, which is compared with the input synchronized signal by the frequency / phase comparison circuit, at a plurality of division ratios, Frequency phase comparison can be performed on the pattern. Accordingly, the second PLL circuit is 1-7RL
It can be used for different recording code systems such as LC, 2-7RLLC.

Further, the first PLL LSI according to the present invention can select any of the phase comparison unit output signal and the external input signal as the charge pump input signal, so that the charge pump can be operated without operating the phase comparison unit. Testing can be performed.

Therefore, it is easy to use the PLL circuit formed as an LSI. Further, the output of another phase comparator can be directly input to the charge pump, and the application range of the PLL LSI can be expanded.

Further, according to the second PLL LSI according to the present invention, one type of PLL LSI can cope with devices having different input data signal qualities and devices employing different coding schemes.

Hereinafter, an embodiment of the PLL circuit according to the present invention will be described.

 FIG. 1 shows a configuration of a PLL circuit according to the present embodiment.

As illustrated, the PLL circuit according to the present embodiment includes a frequency phase comparator 101, a charge pump 102, a phase comparator 103,
It comprises a charge pump 104, a loop filter 3, a VCO (voltage controlled oscillator) 4, a control signal generation circuit 107, and a changeover switch 115.

The charge pump 104 is configured such that the output current can be switched between two levels in accordance with the current switching signal 121 output from the control signal generation circuit 107.
When 121 is at "H" level, the current is switched to a larger current, and when it is at "L" level, the current is switched to a smaller current.

The changeover switch 115 is controlled by a comparator changeover signal 122. When the comparator changeover signal 122 is at “H” level, the charge pump output 113 on the frequency-phase comparator side is
When "L" level, charge pump output of phase comparator
114 is selected and transmitted to the loop filter 3.

The comparator selection signal 120 is a signal for selecting a phase comparator to be used at the time of synchronization pull-in. When selecting a frequency / phase comparator according to the quality of an input data signal, the comparator selection signal 120 is set to “H” level, and when a phase comparator is selected. Is set to “L” level. That is, for example, when the input data signal has data missing or boiling, the phase comparator is selected as the “L” level. In the synchronous tracking state, the input data signal is not a sync pattern having a constant frequency but random recording data, so that the phase comparator is selected as “L” level.

The gain switching signal 119 is a signal for switching the loop gain of the PLL circuit, and switches between a synchronization pull-in state and a synchronization tracking state.

Normally, after completion of synchronization pull-in, the PLL circuit lowers the loop gain so as not to lose synchronization, and enters a synchronization tracking state.

As described above, in the PLL circuit according to the present embodiment, in the synchronization pull-in state, the changeover switch 115 is set to the frequency / phase comparator or the phase comparator side according to the quality of the input data signal, and the charge pump 104 is set to the large current state. In this case, the switch 115 is set to the phase comparator side in the synchronous tracking state, and the charge pump 104 is set to the low current state to set the low gain phase comparator.

These switching controls are performed by the control signal generation circuit 107. FIG. 10A shows input / output correspondence in the control signal generation circuit 107, and FIG. 10B shows the state of the PLL circuit selected as a result.

The control signal generation circuit 107 can be composed of, for example, a NAND 201 and an inverter 202 as shown in FIG.

The switching between the frequency phase comparator and the phase comparator according to the quality of the input data signal in the synchronization pull-in state is performed, for example, by selecting the frequency phase comparator in the initial state and switching to the phase comparator when a synchronization error or the like occurs. It can be realized by a method or the like.

Further, the charge pump 104 can be realized by, for example, a circuit shown in FIG.

In FIG. 3, transistors Q301 to Q305 are current mirror circuits, and switches 301 and 302 are turned ON / OFF by INC signal 111 and DEC signal 112, and the INC and DEC currents are multiplied by the current mirror ratio of reference current I301 or I302. Is output.

The reference current is set as I301> I302, and the switch 303 is switched by the current switching signal 121 (see FIG. 1).

When the current switching signal 121 is at “H” level, I301 is selected and the output current is increased. When the current switching signal 121 is at “L” level, I302 is selected.
Is selected and the output current decreases.

Note that the PLL circuit according to the present embodiment may be integrated and manufactured as a phase-locked LSI.

In this case, since the loop filter 3 requires an analog element, it is preferable to use an external circuit in order to make its characteristics settable outside the LSI.

Next, a description will be given of the frequency-phase comparator when the PLL circuit according to the first embodiment is applied to an input data signal of a different recording encoding system.

In this case, the frequency / phase comparator 101 includes a variable frequency dividing circuit 401, flip-flops 402 and 403, and a NAND
Consists of four.

 Then, the frequency dividing ratio is determined by the variable frequency dividing circuit 401.

In this frequency phase comparator, the variable frequency dividing circuit 401 variably divides a frequency dividing circuit having a fixed frequency dividing ratio in a normal frequency phase comparator, thereby generating a signal 405 for realizing frequency phase comparison for different sync patterns. Enable input.

 The configuration of the variable frequency dividing circuit 401 is shown in FIG.

As illustrated, the variable frequency dividing circuit 401 includes flip-flops 501, 502, and 503, NANDs 504 to 513, and inverters 514 and 515.
The frequency division ratio is determined by the frequency division ratio switching signals 405a and 405.
By setting b, the frequency can be switched to 3, 4, or 8 frequency division.

Here, a truth table showing the operation of the variable frequency dividing circuit 401 is shown in FIG.
Shown in Figure 1. In the figure, “n” indicates the next timing of “n−1”.

As described above, if this variable frequency dividing circuit is used, 3T, 4T,
Frequency phase comparison can be performed for any of the sync code recording patterns of 8T.

For example, the present invention can be applied to 1-7 RLLC having a 3T sync pattern, 2-7 RLLC having a 4T sync pattern, and 2-7 RLLC of an edge separation type having an 8T sync pattern used in an optical disk device or the like.

In addition, since the flip-flop and the logic gate are used alone without using a programmable counter or the like, high-speed operation is possible, and high frequencies can be handled.

Next, a case where the PLL circuit according to the first embodiment is manufactured as an LSI will be described.

In this case, it is manufactured as a phase-locked LSI that enables external input to the charge pump.

 FIG. 6 shows the configuration of this phase-locked LSI.

In the figure, the portion within the broken line corresponds to the phase-locked LSI. In the present embodiment, the loop filter 3 requires an analog element, and is an external circuit so that its characteristics can be set outside the LSI.

As shown in the figure, by adding charge pump input changeover switches 601 and 602 to a normal PLL circuit, external input signals 603 and 604 can be directly input to the charge pump.

As described above, by allowing an external input, a combination with an external phase comparator can be enabled, and the application range of the LSI can be expanded.

Further, since the charge pump can be directly operated by enabling the external input, the charge pump can be tested without operating the phase comparator.

As described above, according to the present embodiment, either the frequency phase comparator or the phase comparator can be selected as the phase comparator at the time of synchronization pull-in, so that the comparator suitable for the data signal quality can be selected. , It is possible to always perform good synchronization pull-in.

Further, since the frequency division ratio of the frequency / phase comparator can be made variable, frequency / phase comparison can be performed for various sync patterns, and the invention can be applied to different recording code systems.

Further, in the phase-locked LSI, since external input to the charge pump can be made possible, it can be used in combination with an external phase comparator, and testing of the LSI can be facilitated.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a PLL circuit that can exhibit good phase synchronization characteristics for data signals having different qualities.

Further, it is possible to provide a PLL circuit applicable to different recording coding systems such as 1-7RLLC and 2-7RLLC.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration of a control signal generation circuit, FIG. 3 is a block diagram showing a configuration of a charge pump, FIG. 4 is a block diagram showing a configuration of a frequency-phase comparator, FIG. 5 is a circuit diagram showing a configuration of a variable frequency dividing circuit, and FIG. 6 is a block diagram showing a configuration of a phase-locked LSI capable of being externally input to a charge pump. FIG. 7, FIG. 7 is a block diagram showing a configuration of a PLL circuit according to the prior art, FIG. 8 is a block diagram showing a configuration of a frequency / phase comparator according to the prior art, and FIG. 9 is a frequency / phase comparator according to the prior art FIG. 10A is an explanatory diagram showing input / output correspondence of a control signal generation circuit according to an embodiment of the present invention, and FIG. 10B is an explanatory diagram showing a circuit state for a control signal of a PLL circuit. FIG. 11 is an explanatory diagram showing the operation of the variable frequency dividing circuit. . 3 ... loop filter, 4 ... VCO, 101 ... frequency phase comparator, 102 ... charge pump, 103 ... phase comparator,
104 charge pump, 107 control signal generation circuit, 11
5… Changeover switch, 401… Variable frequency divider circuit, 402,40
3… Flip-flop, 404… NAND, 601… Charge pump input switch.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Toru Karasawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi Video Engineering Co., Ltd. Inside Hitachi Semiconductor Design & Development Center (72) Inventor Fuka Ooi 2880 Kozu, Odawara-shi, Kanagawa Prefecture Inside Odawara Plant, Hitachi, Ltd. (56) References JP-A-2-89421 (JP, A) JP-A-2-134024 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03L 7/08-7/14 G11B 20/14

Claims (1)

(57) [Claims] A frequency phase comparator and a phase comparator to which a data signal and an oscillation clock are commonly input, two charge pumps, a loop filter, a voltage controlled oscillator, and a signal input to the loop filter. A switch that selects one of the outputs of the two charge pumps, and a control circuit that controls the selection of the switch. If there is a deterioration in the quality of the output, the PLL circuit controls the switch to select the output of the phase comparator, and otherwise controls the switch to select the output of the frequency phase comparator. .