JPH02134024A - Mobile frequency stabilizing system - Google Patents

Abstract

PURPOSE:To make a mobile frequency stable for a frequency phase synchronizing circuit by setting a control voltage inputted to a VSYNC generating means to a constant value at moving state. CONSTITUTION:Upon the detection of a frequency phase synchronizing circuit brought into the moving state, a control voltage switching signal (CXVC) generating means 16 sets a control voltage switching signal CXVC fed to a synchronous clock (VSYNC) generating means 15 and supplies the result to a control voltage (VC) switching means 18. When the signal CXVC is turned on, the switching means 18 supplies the reference control voltage of a reference control voltage source 17 to the VSYNC generating means 15, which is stably in moved at a constant frequency corresponding to the reference control voltage being the constant value. Thus, the mobile frequency of the frequency phase synchronizing circuit is made stable.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for stabilizing the free-running frequency of a frequency-phase synchronized circuit after stopping an external clock signal, the free-running frequency of a frequency-phase synchronized circuit with the same circuit configuration is stabilized, and each The purpose is to prevent variations in free-running frequency between circuits, and the PLI is equipped with a frequency phase comparator, two phase comparators, a D/A conversion means, a filter for generating a control voltage, and a clock generation means for the same month. - a frequency phase synchronized circuit that generates a synchronization clock synchronized with an external clock signal; A voltage source for supplying a prescribed reference control voltage and a voltage source provided between the filter and the synchronization clock generation means or between the D/A conversion means and the filter, and supplied to the synchronization clock generation means when the control voltage switching signal is on. means for switching the control voltage to a control voltage based on the reference control voltage.

[Industrial application field]

The present invention includes a frequency phase comparator and a phase comparator, and P
L L (Phase 1ocked 1oop)
The present invention relates to a free-running frequency stabilization method for stabilizing the free-running frequency after the external clock signal is stopped in a frequency-phase synchronized circuit that generates a single-use lock signal whose frequency and phase are synchronized with an external clock signal.

[Conventional technology]

When an external clock signal is applied, the frequency-phase synchronized circuit emits a periodic clock signal whose frequency and phase are synchronized with the external clock signal, and when the external clock signal stops, it runs freely at a frequency determined by the circuit parameters. This free-running clock signal is also used as various signal sources.

FIG. 5 is a block diagram showing the configuration of such a frequency phase synchronization circuit.

In the figure, 21 is a frequency phase comparator, which receives an external clock signal (hereinafter referred to as WSYNC signal) inputted from the outside and a synchronization clock signal (hereinafter referred to as WSYNC signal) inputted from the frequency divider (described later) of the frequency phase synchronization circuit. , VSYNC, signal) (specifically, the phase difference based on the frequency difference), and when the vsyNcr signal has a lower frequency than the WSYNC signal, that is, VSYNCr
When the signal is delayed in phase from the WSYNC signal, an INcI signal with a time width proportional to the frequency (phase) difference is generated, and when the signal is at a high frequency, that is, VSYNC,
When the signal is ahead of the WSYNC signal in phase, a DEC signal with a time width proportional to the frequency (phase) difference is generated.

22 is a phase comparator, which combines the WSYNC signal and a synchronization clock signal (hereinafter referred to as VSYNC) input from a frequency divider to be described later.
), and the VSYNCp signal is
When the phase is lagging behind the SYNC signal, an INCp signal is generated with a time width proportional to the lagging phase difference, and when the phase is leading than the SYNC signal, an INCp signal is generated with a time width proportional to the leading phase difference.
C. Generate a signal.

23 is a multiplexer (hereinafter referred to as MPX);
t, l control signals (hereinafter referred to as WGE signals) are off (L
level), the I generated by the frequency phase comparator 21
When the NC and DECf signals are selected and the WGIE signal is on (H level), the INC signal generated by the phase comparator 22 is selected.
p and DECp signals are selected and output as INC and DEC signals.

24 is a charge pump circuit that supplies a charging current to the filter at the next stage for the duration of the INC signal, and discharges the filter current for the duration of the DI:,C signal.

When both the INc signal and the DEC signal are on, the output impedance is high. Therefore, when the frequency phase synchronized circuit becomes free-running, the phase comparator 22 generates lNCl,
Since both the and DECp signals are turned on, the charge pump circuit 24 has a high output impedance.

25 is a filter, as shown in the figure, a transistor 251
, 252. Filter resistance 253, 254.255
．． 256 and filter capacitors 257 and 258, and receives charging and discharging currents from the charge pump circuit 24 and generates a control voltage VC. Note that the equivalent capacity of the filter 25 will be indicated by CE, and the equivalent resistance will be indicated by R6. Also,
The control voltage VC when based on the INC and DEC signals of the frequency phase comparator 21 is denoted by ■Ct, and the phase comparator 2
The case based on the INC and DECp signals of 2 is denoted by VC.

26 is a voltage controlled oscillator (hereinafter referred to as VCO), which receives a control voltage VC (VCl or VC
A high frequency clock signal HC, which changes in proportion to the voltage level of p) (if the control voltage is VC2) or Hcp (
(when the control voltage is vCp).

A frequency divider 27 divides the frequency of the high frequency clock signal HC or HCp inputted from the VCO 26 to generate a VSYNCf or VSYNCp signal, and feeds it back to the frequency phase comparator 21 and the phase comparator 22.

In the frequency phase synchronized circuit configured in this manner, the frequency phase comparator 21-MPX23-charge pump circuit 24-filter 25-vc.

26 - Frequency divider 27 - Loop of frequency phase comparator 21 and phase comparator 22 - MPX 23 - Charge pump circuit 24
The loops of - filter 25 - VCO 26 - frequency divider 27 - phase comparator 22 each form a PLL.

Next, the operation shown in FIG. 5 will be explained. Initially, the WGE signal is set to off (L level), and the MPX 23 selects the frequency phase comparator 21 side.

The frequency phase comparator 21 uses the WSYNC signal and the frequency divider 27
Compare the frequency of the generated V S Y N C with the signal, and find that V S Y N Ct IJ<W S Y N C
When the frequency is lower, the frequency difference (lag phase difference)
When the frequency is high, a DECrfi signal with a time width proportional to the frequency difference (leading phase difference) is generated.

When the WGE signal is off, the MPX 23 selects the INC and DEC1 signals generated by the frequency phase comparator 21 and supplies them to the charge pump circuit 24.

The charge pump circuit 24 supplies a charging current to the filter 25 to charge the capacitor C4 when the signal INC is supplied, and discharges the charge in the capacitor CE when the signal DEC is supplied. lNCf signal and DECt
When both signals are off (L level), that is, WSY
When the frequencies of the NC signal and ■5YNC signal match,
The amount of charge on capacitor CA does not change.

The filter 25 generates a control voltage VC, whose output level changes according to a time constant C4R1 upon being charged and discharged by the charge pump circuit 24, and supplies it to the VCO 26.

The VCO 26 receives this control voltage vCf and generates a high frequency clock HCf whose frequency changes in accordance with the voltage level.
is generated and input to the frequency divider 27.

The frequency divider 27 divides the frequency of this HC, generates the VSYNC2 signal, and feeds it to the frequency phase comparator 21.

The frequency phase comparator 21 includes MPX23. Charge pump circuit 24. Filter 25. Since the loop of the VCO 26 and the frequency divider 27 forms a PLL, the frequency divider 27, ie, the frequency phase synchronization circuit, generates the VSYNCf signal synchronized with the frequency of the WSYNC signal.

This frequency synchronization operation is based on the input W S Y N C
Since the signal clock is sufficiently completed within about 20 clocks, the WGE signal remains off (L level) for a period equivalent to 20 cycles of the WSYNC signal, and then is turned on (II level). As a result, the MPX 23 selects the phase comparator 22 side.

The phase comparator 22 compares the phase of WSYNC (No. 3) and the WSYNCp signal generated by the frequency divider 270, and
, when the phase of VSYNCp is behind the phase of WSYNC, an INCP signal with a time width proportional to the delayed phase difference is generated, and when the phase of VSYNCp is ahead of the phase of WSYNC, an INCP signal is generated that is proportional to the leading phase difference. DECp of the time width
Generate a signal.

When the WGE signal is on, the MPX 23 selects the INCp and DECp signals generated by the phase comparator 22 and supplies them to the charge pump circuit 24.

When the charge pump circuit 24 is supplied with the INCp signal, it supplies a charging current to the filter 25 to charge the capacitor C4, and when it is supplied with the DECp signal,
Discharge the charge in capacitor CE. lNCl, signal and D
When both ECp signals are off (L level), that is,
When the phases of the WSYNC signal and the VSYNC signal are lost, the amount of charge on the capacitor CE does not change.

The filter 25 is charged and discharged by the charge pump circuit 24, generates a control voltage VC whose output level changes according to its time constant CER, and supplies it to the VCO2[3.

VC026 receives this control voltage ■Cp and generates a high frequency clock signal H whose frequency changes in accordance with the voltage level.
Cp is generated and supplied to the frequency divider 27. The frequency divider 27 divides this HCp to generate a vsyNC,1s signal, and feeds it back to the phase comparator 22.

Phase comparator 22. MPX23. Charge pump circuit 24
．． Filter 25. Since the loop of the VCO 26 and the frequency divider 27 forms a PLL, the frequency divider 27, that is, the frequency phase synchronization circuit, generates the VSYNC signal, which has the same frequency and phase as the WSYNC signal. Ru.

When the WSYNC signal is stopped, the frequency phase synchronized circuit runs free at a frequency determined by the parameters of the circuit, in particular the control voltage VC generated by the filter 25.

Since the frequency and phase synchronized circuit operates as explained above, it is used as a circuit that generates a VSYNCp signal whose frequency and phase are synchronized with an external WSYNC signal.
Clock signals during free running are also used as various signal sources.

For example, in a magnetic tape device, if magnetism remains in the write head, it will cause distortion in the reconstructed waveform during playback.
In order to reduce the reproduction waveform distortion caused by the read head by 1, it is necessary to prevent the write head from becoming magnetized. Therefore,
A degauss circuit is provided in the write circuit so that the write head is degaussed after writing.

A frequency phase synchronized circuit is used as a circuit that generates a clock signal whose frequency and phase are synchronized with the write signal. It runs free at a frequency determined by the parameters.The clock and cross signals generated by this frequency phase synchronization circuit during free running are used as the signal source for the degauss circuit.

[Problem to be solved by the invention]

As mentioned above, the frequency phase synchronization circuit is externally synchronized! IJI
In addition to being used as a circuit that generates a clock signal having the same frequency and phase as the clock signal (1υ1), it is also used as a signal source that uses a free-running clock signal (hereinafter referred to as FCLK signal).

When used as a signal source using free-running frequency, its F
If the free-running frequency of the CLK signal is not stable, various problems will occur. For example, when used as a signal source for a degauss circuit in a magnetic tape device, if the oscillation frequency fluctuates, the write head will not be degaussed properly, causing distortion in the waveform reproduced by the read head and deteriorating the S/N ratio. This inconvenience arises. Therefore, it is necessary to sufficiently stabilize the frequency of the frequency phase synchronized circuit when it is free running.

However, frequency phase synchronized circuits are semiconductors (Ic and 1
Since it is composed of three ports, the parameters of the same circuit element vary depending on temperature, changes over time, etc., and even in the same circuit, the parameters vary for each frequency and phase synchronized circuit.

For this reason, the free-running frequency of a 101 frequency phase synchronized circuit will vary for each frequency phase synchronized circuit even if the circuit configuration is the same, and even in the same frequency phase synchronized circuit, it will fluctuate due to fAK, changes over time, etc. There was a problem.

When a frequency-phase synchronized circuit is used in a mass-produced product, even if the circuit configuration is the same, if the free-running frequency varies, the quality of the product will vary. It is inconvenient to adjust the free running frequency of each device in order to eliminate this variation because it reduces productivity.

An object of the present invention is to provide an improved free-running frequency stabilization method that stabilizes the free-running frequency of frequency-phase synchronized circuits with the same circuit configuration to a constant value and eliminates self-frequency fluctuations between circuits. shall be.

[Means to solve the problem]

In a frequency phase synchronized circuit, the two signals INC and DEC generated from the frequency phase comparator and phase comparator are both on (H level) during free running, so the output side of the charge pump circuit becomes high impedance. The PLL loop is then broken. Therefore, the control voltage VC generated by the filter determines the frequency of the voltage controlled oscillator (VCO), that is, the free-running frequency of the FCLK signal generated by the frequency divider.

However, the common emitter amplification factor can fluctuate by a factor of about 10 at worst due to variations in the parameters of the I transistors that make up the filter, especially variations in the current amplification factor, temperature changes, etc. Therefore, even with the same circuit configuration, the filter output voltage between each frequency phase synchronized circuit (control voltage VC) is the worst i for a power supply of about 5■
It varies by about v.

Therefore, variations occur in the frequency of the voltage controlled oscillator VCO and the free running frequency of the FCLK signal output from the frequency divider.

Therefore, if the control voltage VC output by the filter is made constant during free running, that is, the voltage controlled oscillator V
By stabilizing the input voltage of CO, the free running frequency of the frequency phase synchronized circuit can be stabilized to a constant value.

Based on this idea, the present invention achieves the same frequency phase by stabilizing the control voltage VC output by the filter or by directly inputting a constant reference voltage to the voltage controlled oscillator ■CO during free running. This is to stabilize the free running frequency of the U1 circuit.

Hereinafter, the means employed in the present invention to solve the above-mentioned problems will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 11 is a frequency phase comparator, 12 is a phase comparator, 13 is a D/A conversion means, 14 is a filter, and 15
is synchronization clock generation means (hereinafter referred to as VSYNC generation means), which constitutes a conventional frequency and phase synchronization circuit.

The frequency phase comparator 11 compares the frequencies of an external synchronizing clock signal (WSYNC signal) and a periodic clock signal (VSYNCt signal) generated by the VSYNC generating means 15, and calculates the difference in high and low frequencies, that is, the lead/lag phase difference. A frequency difference signal DS having a time width corresponding to is generated.

The phase comparator 12 compares the phase difference between the WSYNC signal and the synchronization clock signal (VSYNC, signal) generated by the VSYNC generating means 15, and generates a phase difference signal DS having a time width corresponding to the lead/lag phase difference. occurs.

The D/A conversion means 13 receives the frequency signal DS from the frequency phase comparator 11 or the phase difference signal D from the phase comparator 12.
S, and generates a D/A conversion signal DAt or DA having an output level corresponding to the time width. The operation of switching the D/A conversion target performed by the D/A conversion means 13 to the frequency phase comparator 11 or the phase comparator 12 is performed by a synchronization control signal (WGE signal).

The filter 14 receives DA or D from the D/A conversion means 13.
A. Upon receiving the signals, filter them and apply the control voltage V
C or VC.

The VSYNC generating means 15 receives the control voltage VC or -Cp from the filter 14 and generates a synchronizing clock signal VSYNCr or VSYNCp whose frequency changes in proportion to the voltage level.

Reference numeral 16 denotes a control voltage switching signal generation means (hereinafter referred to as CXVC generation means), which detects that the frequency phase synchronization circuit enters a free-running state and switches the control voltage supplied to the VSYNC generation means 15. signal CXv,
occurs.

A reference control voltage source 17 supplies a constant reference control pressure VS that defines the free running frequency of the synchronous circuit.

Reference numeral 18 denotes control voltage switching means (hereinafter referred to as VC switching means), which is provided between the filter 14 and the VSYNC generation means 15 or between the D/A conversion means 13 and the filter 14 as shown by the broken line. CX from means 16
When the vC signal is on, in the former case, the reference control voltage VS
is supplied to the VSYNC generating means 15, and in the latter case, the reference control voltage VS is supplied to the filter 14, and when the CXv signal is off, the control voltage VC from the filter 14 is supplied to the VSYNC generating means 15 in the former case, and the reference control voltage VS is supplied to the filter 14 in the latter case. In this case, the D/A converter 13 supplies the DA double signal to the filter 14 .

In this configuration, the frequency phase comparator 11. D/A conversion means 13. Filter 14. VC switching means 18 and VS
The loop of the YNC generating means 15 and the phase comparator 12.
D/A conversion means 13. Filter 14. VC switching means 1
8 and the loop of the VSYNC generating means 15 are respectively P
It forms LL.

[For production]

The operation of the present invention shown in FIG.
A case where the signal is located between the filter 14 and the VSYNC generating means 15 will be explained.

At the start of operation, the WGE signal is set to off (L level). Thereby, the D/A conversion means 13 selects the frequency phase comparator 11 and performs D/A conversion.

The frequency phase comparator 11 compares the frequencies of the external WSYNC signal and the VSYNCf signal generated by the VSYNC generating means 15, and generates a frequency difference signal DS having a time width corresponding to the difference in high and low frequencies (lead/lag phase difference). , occurs.

The D/A conversion means 13 receives the frequency difference signal DSf from the frequency phase comparator 11 and generates a D/A conversion signal DAt having an output level proportional to its time width. The filter 14 filters the D/A conversion signal L)Ar received from the D/A conversion means 13 to generate a control voltage VC. At the start of operation, the C generated by the cxvc generating means 16
Since the Xvc signal is off, the control voltage VC7 is supplied to the VSYNC generating means 15 through the switching means 18.

The VSYNC generating means 15 receives the control voltage VC2 from the filter 14, generates a VSYNC signal whose frequency changes in accordance with the voltage level, and feeds it to the frequency comparator 11.

Frequency comparator 11. D/A conversion means 13. Filter 14
．． Since the loop of the switching means 18 and the VSYNC generating means 15 forms a PLL, the 5YNC generating means 15 generates a VSYNC signal synchronized with the frequency of the external wsyNC signal. .

The WGE signal is set from OFF to ON (H level) at the timing at which this frequency synchronization operation is reliably completed (known in advance through experiments, etc.).

Thereby, the D/A conversion means 13 selects the phase comparator 12 and performs D/A conversion.

The phase comparator I2 outputs the WSYNC signal and the VSYNCp generated by the VSYNC generating means 15 (■5YN at the time of switching).
A phase difference signal DSp having a time width corresponding to the lead/lag phase difference is generated and sent to the D/A converter 13.

Hereinafter, as in the case of the frequency phase comparator 11 described above, D
The /A conversion means 13 generates a D/A conversion signal DAp having an output level proportional to the time width of the phase difference signal DSp.

The filter 14 receives the D/A from the D/A conversion means 13.
The conversion signal DAp is filtered to generate a control voltage ■Cp, which is supplied to the vsyNC generating means 15 through the switching means 18.

VSYNC generating means 15 receives control voltage vCp from filter 14 and generates a VSYNCp signal whose frequency changes in proportion to the voltage level.

Phase comparator 12. D/A conversion means 13. Filter 14.
Since the loop of the switching means 18 and the VSYNC generating means 15 forms a PLL, the VsYNC generating means 15 generates a VSYNCp signal whose frequency and phase are synchronized with the WSYNC signal.

Using the VSYNCp signal whose frequency and phase are synchronized with the WSYNC signal generated as described above, a desired operation is performed, for example, an operation of writing data onto a magnetic tape.
When this operation is completed, the νJ5YNC signal is stopped.

When the WSYNC signal is stopped, the synchronization operation by the PLL is no longer performed, so the frequency and phase synchronization circuit enters a free-running state.

When the cxvc generating means 16 detects that the frequency phase synchronized circuit enters a free-running state due to, for example, stopping this WSYNC signal, it generates, that is, turns on, a CXvc signal that switches the control voltage supplied to the VSYNC generating means 15.・The signal is supplied to the VC switching means 18. In this case, it is desirable to generate the CX9 signal after a certain period of time after the frequency-phase synchronized circuit enters the free-running state (the reason will be described later).

When this CXvc signal is turned on, the switching means 18
The reference control voltage VS of the reference control voltage source 17 and the VSYNC generating means 15 are supplied.

The VSYNC generating means 15 stably runs free at a constant frequency corresponding to the constant value of the reference control voltage VS.

By the way, the level of the control voltage ■Cp outputted from the final filter 14 in which the frequency phase synchronized circuit continues its free-running state varies for each frequency phase synchronized circuit due to variations in the parameters of the constituent elements of the filter 14. however,
Immediately after entering the free-running state, the value of the constant control voltage VC is discharged at a constant value, so the range of variation after a certain period of time has passed is small.

Therefore, the CXv generated from the cxvc generating means 16
c signal timing after a certain period of time after the frequency phase synchronization circuit enters the free-running state (for example, V S Y during free-running).
If the N C signal (ie, several clocks after the FCLK signal) is selected, even if there is variation in the control reference voltage VC that reaches the R end, the level difference from the reference control voltage VS will be small, thereby preventing the occurrence of transients. can do.

Next, the operation when the VC switching means (1) 8 is provided between the D/A converting means 13 and the filter 14 will be explained.

When the filter 14 is an active filter, when its input voltage is kept constant, its output voltage (control voltage VC) becomes a constant level. In particular, active filters using operational amplifiers stabilize the output voltage. That is, in the active filter 14, by stabilizing its input voltage, the output voltage (control voltage VC9) of the filter 14 can be sufficiently stabilized. Further, the same applies when the filter 14 is a pensive filter.

Therefore, the VC9J conversion means 18 is replaced by the D/A conversion means 13.
and the filter 14, and the reference control voltage VS is provided between the filter 14 and the filter 14 during free running.
Even if the voltage is supplied to the input side of the filter 14, a stable control voltage can be obtained, and the free-running frequency of the frequency-phase synchronized circuit can be stabilized to a constant value.

The frequency phase synchronization operation of the frequency phase synchronization circuit in this case is the same as that in the case where the switching means 18 described above is provided between the filter 14 and the VSYNC generation means 15. Further, since the operation of entering the free-running state and switching the control voltage to the reference voltage VS is performed in the same manner as the above-mentioned switching operation, a description thereof will be omitted.

As mentioned above, when the frequency phase synchronization circuit is free-running, ■5YNC
Since the control voltage input to the generating means 15 is set to a constant value, the free running frequency of the frequency phase synchronization circuit can be stabilized to a constant value. As a result, the circuit groove bottoms are the same, and variations in the free running frequencies of the respective frequency phase synchronized circuits can be significantly reduced.

Further, when the oscillation output of the frequency phase synchronization circuit during free running is used as a signal source for the degauss circuit of the magnetic tape device, it is possible to eliminate variations in the degaussing effect of the write head between devices and stabilize the degaussing effect.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 2 to 4. FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIGS. 3 and 4 are operation timing charts of the embodiment.

In the following embodiments, it is assumed that the switching means 18 is provided between the filter 14 and the VSYNC generating means 15. It is also assumed that the frequency and phase synchronization circuit generates a VSYNC signal synchronized with the write clock signal of the magnetic tape device (indicated by the same WSYNC signal), and during free running, it is supplied to the degauss circuit to demagnetize the write head.

(A) Configuration of Example In FIG. 2, frequency phase comparator 111 phase comparator 1
2. D/A conversion means 13. Filter 14VSYNC generating means 15. CXVC generation means 16° reference control voltage source 17
and 1ζ for the VC switching means 18 are as explained in FIG.

The frequency phase comparator 11 receives a write clock signal (WSYNC signal) input from the outside and the vSYNC generating means 1.
The frequency difference (phase difference) with the VSYNCr signal generated from 5 is compared, and the VSYNC1 signal is
When the frequency is lower than the signal, i.e. V S Y
When the NCr signal is delayed in phase from the WSYNC signal, the time width is proportional to the frequency (phase) difference.
When the f signal is generated and has a high frequency, that is, VS
When the YNCr signal is ahead of the WSYNC signal in phase, the DEC has a time width proportional to the frequency (phase) difference.
Generate a signal.

The phase comparator 12 compares the phase difference between the WSYNC signal and the VSYNCp signal generated by the VSYNC generating means 15, and when the VSYNCp signal is delayed in phase from the WSYNC signal, the phase comparator 12 compares the phase difference between the WSYNC signal and the VSYNCp signal generated by the VSYNC generation means 15. IN
When a Cp signal is generated and has a leading phase, a DEC signal with a time width proportional to the leading phase difference is generated.

In the D/A conversion means 13, 131 is a multiplexer (hereinafter referred to as MPX), and when the synchronization control signal (WGE signal) is off ([, level), the frequency phase comparator 11
Select the INC and DEC1 signals generated by WGE
When the signal is on level), the phase ratio! , the INCp and DEC signals generated by the two devices 12 are selected and output as INC and DEC signals.

A charge pump circuit 132 supplies a charging current to the filter 14 for the time width of the INC signal, and discharges the current of the filter 14 for the time width of the DEC signal. INC signal and D
When both EC signals are on, the output and impedance are high. Therefore, when the frequency phase synchronized circuit becomes free-running, the frequency (INC and D generated by the comparator 11)
Since the B and C signals are both turned on, the charge pump circuit 132 has a high output impedance.

Filter 14 includes transistors 141 .
142. Filter resistor 143, 144.145.1
46 and filter capacitors 147 and 148, it receives the charging and discharging current from the charge pump circuit 132 and outputs the control voltage VC (lNCf and DEC of the frequency phase comparator 11).
, if based on the signal ■Cf, lNC of the phase comparator 22
2 and VCp when based on the DECp signal. Note that the equivalent capacitance of the filter 14 will be indicated by CE, and the equivalent resistance will be indicated by R1.

In the VSYNC generating means 15, 151 is a voltage controlled generator I&2? j < v co ), and the high frequency clock signal 11Cr changes in proportion to the voltage level of the control voltage VC or base voltage S input from the filter 14 and the switching means 18 (in case the control voltage is VC). or IIC
p (if the control voltage is VC) or I]0 (if the reference voltage is VS).

152 is a frequency divider which divides the high frequency clock signal HC or IICp input from the VCO 151 and divides it into V S Y
It generates the NC or VSYI'JCp signal and feeds it to the frequency phase comparator 21 and phase comparator 22. Furthermore, during free running, the free running clock signal FCLK is generated by frequency-dividing the high frequency clock signal HC.

In this configuration, the frequency phase comparator 11-MPX13
1 - Charge pump circuit 132 - Filter 14 - Switching means 18 - VCO 151 - Frequency divider 152 - Loop of frequency phase comparator 11 and phase comparator 11 - MPX 131 -
The loops of charge pump circuit 132, filter 14, switching means 18, VC○151, frequency divider 152, and phase comparator 12 each form a PLL.

In the cxvc generating means 16, 161 is an inverter which receives the WSYNC signal and generates its inverted signal (hereinafter *WS
YNC signal) is generated.

162 is a ppc generator, which generates VSYN using various known methods.
C signal is received, and a narrow width (■5YN
A pulse signal rpc of 1/6 of the pulse width of the C signal is generated.

163 is an AND circuit which generates a count pulse PC when an AND condition of the PPC signal, *WSYNC signal and VSYNC signal is satisfied, that is, when these three signals are all on.

164 is a counter, and the count pulse PC is connected to the CLK terminal.
count the number of pieces, and set it to a predetermined value (for example, 5 pieces).
When counting, a carry signal is generated from the CARr2Y terminal. R3T is a reset terminal that receives the WGE signal and is reset when it turns off (L level). E
N is an enable terminal which receives the CXVc signal and is enabled when it is off (L level) and disabled when it is on (H level).

An inverter 165 inverts the carry signal from the counter 164 to generate a CXvc signal.

If a free-running frequency is specified, the reference control voltage VS of the reference control voltage source 17 is set to a voltage value that allows the free-running frequency to be obtained. In order to ensure smooth control voltage switching, this free-running frequency is desirably located between the control voltage level during synchronization and in the original free-running state.

The VC switching means 18 is composed of an analog switch to enable high-speed switching.

(B) Operation of the Embodiment The operation of the embodiment will be explained with reference to the operation timing charts of FIGS. 3 and 4.

When a controller (not shown) applies a WSYNC signal to the frequency phase synchronization circuit 11, the control circuit (not shown) initially outputs the WSYNC signal.
The GE signal is turned off (L level) (at time T0 in FIG. 3). As a result, the MPXI 31 uses the frequency phase comparator 11
side ((al, (bl) in FIG. 3). Also, the counter 164 is reset.

On the other hand, in the cxvc generating means 16, since the WGE signal is off, the AND circuit 163 does not generate the count pulse CP. Therefore, the CXvc signal is not generated and maintains the off L level state ((
C)). This causes the switching means 18 to switch the filter 14
selects the control voltage VC output by the selector and supplies it to the VCO 151. Also, counter 164 is enabled.

The frequency comparator 11 compares the frequencies of the WSYNC signal and the VSYNC signal generated by the frequency divider 152, and when VSYNCf is a lower frequency than WSYNC,
lNC with a time width proportional to the frequency difference (lag phase difference)
f signal is generated, and when the frequency is high, a DECf signal with a time width proportional to the frequency difference (advanced phase difference) is generated.

When the WGE signal is on, the MPX l 31 selects the INC and DEC signals generated by the frequency comparator 11 and supplies them to the charge pump circuit 132.

The charge pump circuit 132 supplies a charging current to the filter 14 to charge the capacitor CE when the signal INC is supplied, and discharges the charge in the capacitor CE when the signal DEC is supplied. lNCf signal and DE
When both C and signals are off (L level), that is, W
When the frequencies of the SYNC signal and the VSYNC signal match, the amount of charge in the capacitor C5 does not change.

Filter 4 is charged and discharged by charge pump circuit 132 and generates control voltage VC, whose output level changes according to its time constant ciRi, and supplies it to VCO 151 through switching means 18.

(Part a of Fig. 3(d)) The VCO 151 receives this control voltage VC, and generates a high-frequency clock HC whose frequency changes in accordance with the voltage level.
, and input it to the frequency divider 152.

A frequency divider 152 divides the frequency of this HC, generates a VSYNC2 signal, and feeds it back to the frequency phase comparator 11.

The frequency phase comparator 11 is an MPX 131. Charge pump circuit 132. Filter 14. Switching means 18. VC
Since the loop of O151 and the frequency divider 152 forms a PLL, the frequency divider 152, that is, the frequency phase synchronization circuit outputs VSYNC synchronized with the frequency of the WSYNC signal.
An N Cr signal is generated.

This frequency synchronization operation is sufficiently completed within about 20 input WSYNC clocks, so the controller (not shown) holds WSYNc (i) off (L level) for a period of 20 cycles, and then Turn on the signal (H
(T1 time point in Figure 3). As a result, the MPX 23 selects the phase comparator 22 side ((a) and (bl) in FIG. 3).

The phase comparator 12 compares the phase of the WSYNC signal and the VSYNCpi signal generated by the frequency divider 152, and
When the phase of WSYNC lags behind the phase of WSYNC, an INC signal with a time width proportional to the delayed phase difference is generated,
When the phase of VSYNC is ahead of the phase of WSYNC, DEC and Shingetsu are generated with a time width proportional to the leading phase difference.

When the WGE signal is on, the MPX 131 selects the INc and DECp signals generated by the phase comparator 12 and supplies them to the charge pump circuit 132.

The charge pump circuit 132 supplies a charging current to the filter 14 to charge the capacitor C6 when the INCp signal is supplied, and discharges the charge in the capacitor C4 when the DEC signal is supplied. INCp signal and D
When both ECp signals are off (L level), that is,
When the phase of the second 3U1 signal PS (!: timing signal TS) fails, the amount of charge in the capacitor CE does not change.

The filter 14 is charged and discharged by the charge pump circuit 132, and generates a control voltage Cp whose output level changes according to its time constants C and RE, and supplies it to the VCO 151 through the switching means]8 (the third Figure + (b part of jl).

The VCO 151 receives this control voltage VC, generates a high frequency clock signal HCp whose frequency changes in accordance with the voltage level, and supplies it to the frequency divider 152. Frequency divider 15
2 divides the frequency of this HCp to generate a signal multiplied by V SYN Cp and feeds it back to the phase comparator 22 .

Phase comparator 12. MPX131. Charge pump circuit 1
32. Filter 14. Since the loop of the switching means 18VCO 151 and the frequency divider 152 forms a PLL, the WSY
VSYNC, in which the frequency and phase of the NC signal are synchronized,
, a signal is generated.

The VSYNCp signal synchronized with the frequency and phase of the WSYNC signal generated as described above is used to write data onto a desired magnetic tape, and when this write operation is completed, a controller (not shown)
Sending out the signal is stopped (point 12 in FIG. 3).

When the WSYNC signal is stopped, the frequency phase comparison 731
1 and phase comparison Rg 12 output each INC and DE
Since all C signals are on, the charge bomb circuit 13
2 results in high output impedance. As a result, the synchronization operation by the PLL cannot be performed, and the frequency and phase synchronization circuit enters a free-running state.

When the WSYNC signal is issued, *WSYNC signal and VSYN
Since the C signals are never turned on at the same time, the count pulse PC is not generated from the cxvc generating means 16 (
Figure 4 (a), (b), before T2 time point of tel). However, if the WSYNC signal is stopped at time point 12, the *WSYNC signal is always on (II level), so the VSYNC signal, that is, the free running clock signal (FC
The AND condition of the three signals *WSYNCFCLK generated by the inverter 161 and the pcC generated by the pcc generator 162 is satisfied every time the pulse signal PC (PC, PC2, etc.) is generated. occurs (after time T2 in FIG. 4 (bl to (e)).

The counter 164 counts count pulses PCI and the like generated by the AND circuit 163, and generates a carry signal when a predetermined number (for example, five) is counted. Impark 165 inverts this carry signal and generates a CXvc signal. As a result, the CXvc signal turns on (1 level) at time 13 after time td after the WSYNC signal stops ((c) in FIG. 3), and the counter 164
When the Xvc signal is turned on, it is disabled and the counting operation is stopped.

The VC switching means 18 supplies the reference control voltage VS to the VCO 151 when the cxvc signal is turned on. VC
The control voltage supplied to O151 decreases between T2 and T1 according to the discharge characteristics of the filter 14 (Fig. 3fd).
c) When the reference control voltage VS is received at time T, the value of VS is held from then on. If the reference control voltage VS
If the control voltage is not applied, the control voltage decreases until time T4 according to the discharge characteristics of the filter 14, and thereafter remains at a substantially constant level (d, e in FIG. 3(C)).

The VCO 151 generates an HF signal that stably oscillates at a constant frequency with respect to this constant reference control voltage VS.

The frequency divider 152 divides the frequency of this HF to generate a frequency-stabilized FCLK signal. This FCLK signal is applied to a degauss circuit (not shown) to demagnetize the write head.

The free-running frequency of the FCLK signal generated in this way is stabilized to a constant level, and there is no variation between the respective frequency phase synchronization circuits, so that the demagnetization effect between the respective magnetic tape devices can be stabilized.

The embodiment in which the switching means 18 is provided between the filter 14 and ■C0151 has been described above, but when the switching means 18 is provided between the charge pump circuit 132 and the filter 14, the self-propelled Frequency stabilization takes place.

Furthermore, in order to generate the Cxvc signal with a predetermined td time delay from the stop time T2 of the WSYNC signal, a single shot circuit with a pulse width corresponding to the predetermined delay time is used with the count pulse PC generated by the AND circuit 173 as a trigger. The CXvc signal may be generated at the trailing edge.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) Since the control voltage input to the VSYNC generating means during free running is set to a constant value, the free running frequency of the frequency phase synchronized circuit can be stabilized to a constant value.

(2) According to the above (1), it is possible to significantly reduce the variation in the free running frequency of each frequency phase synchronized circuit having the same circuit configuration.

(3) According to (2) above, when the oscillation output of the frequency phase synchronization circuit during free running is used as the signal source for the degauss circuit of the magnetic tape device, variations in the degaussing effect of the write head between each device can be eliminated, and the degaussing effect can be improved. It can be stabilized.

FIG. 4 shows the control voltage switching signal generating means (C
FIG. 5 is an explanatory diagram of the configuration of a conventional frequency and phase synchronization circuit.

In FIG. 1 and FIG. 2, 11... frequency phase comparator, 12... phase comparator,
13... D/A conversion means, 132... Charge pump circuit, 14... Filter, 15... Synchronization clock (VSYNC) generation means, 151... Voltage controlled oscillator (VCO), 16.・・Control voltage switching signal (CX
VC) generating means, 17... reference control voltage source, 18...
- Control voltage (VC) switching means.

[Brief explanation of the drawing]

Claims (1)

[Claims] 1. Frequency phase comparator (11) and phase comparator (12)
, a D/A conversion means (13) that selects both of these comparators and converts their outputs into D/A; a filter (14) that filters the D/A conversion output to generate a control voltage; A frequency-phase synchronization circuit that includes a synchronization clock generation means (15) that generates a synchronization clock signal with a frequency corresponding to a control voltage, and generates a synchronization clock signal synchronized in both frequency and phase with an external clock signal using a PLL. In the free-running frequency stabilization method, (a) detecting that the frequency phase synchronization circuit enters the free-running state, and generating a control voltage switching signal for switching the control voltage supplied to the synchronization clock generation means (15); (b) a reference control voltage source (17) that supplies a constant reference control voltage that defines the free-running frequency of the frequency phase synchronized circuit; (c) a filter (14); Synchronization clock generation means (1
5) or between the D/A conversion means (13) and the filter (14).
), and when the control voltage switching signal is on, the control voltage switching means (18) switches the control voltage supplied to the synchronization clock generation means (15) to a control voltage based on the reference control voltage. A free-running frequency stabilization method is provided. 2. The free-running frequency stabilization system according to claim 1, wherein the control voltage switching signal generating means (16) generates the control voltage switching signal after a certain period of time after the frequency phase synchronized circuit enters the free-running state. method.