JP2006253869A - Phase synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a phase synchronization circuit which can produce an output signal synchronized with the phase of an input signal while suppressing frequency variation of the output signal even when the input signal is interrupted. <P>SOLUTION: The phase synchronization circuit comprises a phase comparator 1 for comparing the phase of an input signal IN and a comparison signal, a charge pump 2, a low-pass filter 3, a free-running circuit 4, a voltage controlled oscillator 5, and a frequency divider 6. The free-running circuit 4 comprises an input interruption detection circuit 11, an analog selector 12, a constant voltage generation circuit 13, a capacitor 14, and a switching section 15. The switching section 15 is turned on with a detection signal in synchronized state from a synchronization detection circuit 16 and the output signal from a low-pass filter 3 is held by the capacitor 14. The voltage held by the capacitor 14 is employed as a control voltage when the input signal is interrupted, the capacitor 14 is separated by a step-out detection signal and then the out signal from the constant voltage generation circuit 13 is employed as a control voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a phase synchronization circuit for generating an output signal synchronized with the phase of an input signal from a voltage controlled oscillator.

  Various configurations of a phase locked loop (PLL) are already known, and FIG. 12 shows a conventional general phase locked loop that can maintain a free-running state. In the figure, 101 is a phase comparator, 102 is a charge pump, 103 is a low-pass filter (or loop filter), 104 is a free-running circuit, 105 is a voltage controlled oscillator (VCO), and 106 is a frequency divider. , IN is an input signal, OUT is an output signal, fr is an input signal frequency (or reference frequency), fo is an output signal frequency, fp is a comparison frequency, and the input signal frequency fr is different from the output signal frequency fo Further, the frequency divider 106 divides the output signal frequency fo to make it the same frequency as the input signal frequency fr.

  The phase comparator 101 outputs a signal corresponding to the phase difference between the input signal IN having the frequency fr and the comparison signal having the frequency fp and inputs the signal to the charge pump 102. The output signal of the charge pump 102 is input as a control voltage to the voltage controlled oscillator 105 via the low-pass filter 103 and the free-running circuit 104, and the output signal OUT having a phase synchronized with the phase of the input signal IN is not shown. And is fed back to the phase comparator 101 via the frequency divider 106. Note that the low-pass filter 103 generally has an active filter configuration using an operational amplifier. The free-running circuit 104 selects the output signal of the low-pass filter 103 when the input signal IN is normal, and uses it as the control voltage of the voltage controlled oscillator 105. When the disconnection of the input signal IN is detected, the free-running circuit 104 selects a predetermined voltage. Thus, the control voltage of the voltage controlled oscillator 105 is used.

  FIG. 13 is an explanatory diagram of a conventional free-running circuit 104 connected between the low-pass filter 103 and the voltage-controlled oscillator 105, and includes an input break detection circuit 111, an analog selector 112, a constant voltage generation circuit 113, and the like. It has the structure containing. The analog selector 112 is controlled by the detection signal from the input disconnection detection circuit 111. When the input signal IN is normal, the analog selector 112 selects the low-pass filter 103 side, and when the input disconnection detection circuit 111 detects the disconnection of the input signal IN, The analog selector 112 is controlled to use the constant voltage from the constant voltage generation circuit 113 as the control voltage of the voltage controlled oscillator 113. In this case, the self-running state is irrelevant to the input signal IN.

  FIG. 14 shows an example of a self-running circuit integrated into an integrated circuit, and the constant voltage generation circuit 113 is shown as a battery. Also, the input break detection circuit 111 is configured by a monostable multivibrator, and R1 and C1 set the time constant so that the output signal of the monostable multivibrator has a period longer than at least the period of the input signal IN. It is for setting. Therefore, in a normal state where the input signal IN having the frequency fr is continuously input to the terminal B, a high level H signal is output from the terminal Q. In the case of an input signal IN disconnection, a low level L signal indicating an input disconnection detection is output from the terminal Q after a time according to the above time constant.

  The analog selector 112 inputs the voltage of the constant voltage generation circuit 113 to the terminal X0, inputs the output signal of the low-pass filter 103 to the terminal X1, and inputs the terminal Q of the monostable multivibrator of the input break detection circuit 111 to the terminal A. Input the output signal. A control voltage for the voltage controlled oscillator 105 is output from the terminal X. The analog selector 112 switches between the input terminals X0 and X1 and the output terminal X. When the logic level of the signal is expressed by H and L, when A = H, X1 → X, A = When L, selection switching from X0 to X is performed. That is, when the input signal is normal, the output signal of the low-pass filter 103 is input as the control voltage of the voltage controlled oscillator 105, and when the input signal is disconnected, the constant voltage from the constant voltage generation circuit 113 is input to the voltage controlled oscillator. This is input as a control voltage 105. When this constant voltage is used as a control voltage, a self-running state in which a signal not directly related to the input signal phase is output is obtained.

  FIG. 15 is an operation explanatory diagram corresponding to the presence or absence of the self-running function, (A) shows the case without the self-running function, (B) shows the case of the ideal state with the self-running function, (C) shows a case where there is a self-running function and a frequency shift is included. The frequency of the input signal IN input to the phase comparator 101 is the reference frequency fr, the frequency of the signal from the frequency divider 106 is the comparison frequency fp, the output signal of the charge pump 102 and the output signal of the low-pass filter 103 ( The VCO (voltage controlled oscillator 105) control voltage) and the free-running circuit output when the free-running function is provided are shown for the pull-in state, the synchronization state, the input cut-off state, and the free-running state.

  In the case of no self-running function, as shown in FIG. 15A, when the input signal is interrupted, that is, when the reference frequency fr becomes zero, the phase comparator 101 detects the signal phase of the comparison frequency fp. The phase comparison output signal is determined to be delayed in the signal phase of the reference frequency fr, the output signal of the low-pass filter 103 rapidly decreases, and the output signal frequency of the voltage controlled oscillator 105 becomes lower than the center frequency. Therefore, when the input signal is interrupted, the output signal frequency is greatly deviated compared to the synchronized state. Thereafter, when the input signal is recovered, the output signal frequency of the voltage controlled oscillator 105 is greatly different from the input signal frequency, and the time until the synchronous pull-in state is reached becomes longer. In addition, the exact display about the fall of the comparison frequency fp in (A) of FIG. 15 is abbreviate | omitted.

  Therefore, as described above, the free-running circuit 104 is provided, and when the input signal is interrupted, the output signal frequency of the voltage-controlled oscillator 105 is controlled so as to be approximately the center frequency of the pull-in range, so that the free-running state This prevents a large shift in the output signal frequency. As a result, the resynchronization pull-in speed can be increased. The operation when this free-running circuit 104 is provided is shown in FIGS. 15B and 15C. In the ideal state, as shown in FIG. As a result, the output of the low-pass filter is reduced, but there is no delay in the detection of the input signal and the constant voltage from the free-running circuit 105 is substantially the same as the control voltage immediately before the input signal is disconnected. The running circuit output hardly changes, and the voltage controlled oscillator 105 can maintain the output signal frequency that is the same as or slightly different from the output signal frequency before the input signal is cut off, By recovering the signal, it is possible to immediately return to the synchronized state.

  However, in actuality, in the case of an input signal disconnection to the phase comparator 101, due to the time required for the input disconnection detection by the input disconnection detection circuit 111 (see FIG. 13), as shown in FIG. The control voltage according to the decrease in the output signal is input to the voltage controlled oscillator 105. Therefore, at the timing indicated as input disconnection detection, the control voltage of the voltage controlled oscillator 105 decreases corresponding to the signal decrease indicated as the low-pass filter output, so that the output signal frequency of the voltage controlled oscillator 105 varies greatly.

As a self-running circuit of the aforementioned phase synchronization circuit, the output signal of the low-pass filter is held by the holdover circuit upon detection of the input signal disconnection, and this stored value is input to the voltage controlled oscillator as the control voltage to disconnect the input signal. In the configuration that maintains the previous output signal frequency, the level of the output signal of the low-pass filter after the time required to detect the input disconnection has dropped, so even if it is held in the holdover circuit, the low-pass filter immediately before the input signal disconnection It is no longer the output signal of the filter. Therefore, the input signal input to the input disconnection detection circuit is configured to be input to the phase comparator after being delayed by the delay circuit for the time required for the input signal disconnection, and the output signal of the low-pass filter when the input signal disconnection is detected, There has been proposed a configuration in which a voltage is controlled by a voltage controlled oscillator by being held by a holdover circuit (see, for example, Patent Document 1).
JP-A-8-84074

  In general, the output signal frequency fo of the phase synchronization circuit is higher than the input signal frequency fr input to the phase comparator 101. For this purpose, a frequency divider 106 is provided to divide the frequency of the signal input to the phase comparator 101 so as to be the same. From such a frequency relationship, slight fluctuations in the input signal frequency fr correspond to a plurality of cycles with respect to the output signal frequency fo. Accordingly, in order to suppress the change in the output signal frequency fo, a free-running circuit 104 that outputs a constant voltage is provided. However, as shown in FIG. There is a problem that the output signal frequency fo varies due to a large change.

  The present invention solves the above-mentioned problems, and aims to suppress fluctuations in the output signal frequency due to input signal disconnection, thereby speeding up normal recovery by recovering the input signal.

  A phase locked loop circuit according to the present invention includes a phase comparator that compares the phases of an input signal and a comparison signal, a charge pump that inputs an output signal of the phase comparator, and a low-pass filter that inputs an output signal of the charge pump. A self-running circuit that inputs the output signal of the low-pass filter, a voltage-controlled oscillator that inputs the output signal of the self-running circuit as a control voltage, and a frequency of the output signal of the voltage-controlled oscillator matches the frequency of the input signal In the phase synchronization circuit including the frequency divider, the free-running circuit includes an input disconnection detection circuit that detects disconnection of the input signal, a constant voltage generation circuit, an output signal of the low-pass filter, and a constant voltage generation circuit. The output signal is switched by the detection signal from the input disconnection detection circuit, and the analog selector that inputs the control voltage to the voltage controlled oscillator and the output signal of the low-pass filter are maintained. A structure in which a capacitor for.

  The self-running circuit also detects an input disconnection detection circuit that detects an input signal disconnection, a constant voltage generation circuit, an output signal of a low-pass filter, and an output signal of the constant voltage generation circuit from a detection signal from the input disconnection detection circuit. An analog selector that inputs the control voltage to the voltage controlled oscillator, a synchronization detection circuit that detects whether or not the synchronization state is present based on the phase difference between the input signal input to the phase comparator and the comparison signal, and A switching unit that is turned on by a detection signal of a synchronization state from the synchronization detection circuit, and a capacitor that receives and holds the output signal of the low-pass filter via the switching unit that is turned on can be provided.

  The phase locked loop of the present invention includes a phase comparator for comparing the phases of an input signal and a comparison signal, a charge pump for inputting an output signal of the phase comparator, and a low-pass filter for inputting an output signal of the charge pump. A free-running circuit that inputs the output signal of the low-pass filter, a voltage-controlled oscillator that inputs the output signal of the free-running circuit as a control voltage, and a frequency of the output signal of the voltage-controlled oscillator to the frequency of the input signal In the phase synchronization circuit including the frequency divider for matching, the free-running circuit calculates the amplitude value of the output signal of the input disconnection detection circuit, the constant voltage generation circuit, and the low-pass filter that detects the disconnection of the input signal. The voltage limit oscillator, the output signal of the amplitude limit circuit, and the output signal of the constant voltage generator circuit are switched by the detection signal from the input break detection circuit, and the control power is supplied to the voltage controlled oscillator. And a analog selector for inputting a.

  The phase locked loop of the present invention includes a phase comparator for comparing the phases of an input signal and a comparison signal, a charge pump for inputting an output signal of the phase comparator, and a low-pass filter for inputting an output signal of the charge pump. A free-running circuit that inputs the output signal of the low-pass filter, a voltage-controlled oscillator that inputs the output signal of the free-running circuit as a control voltage, and a frequency of the output signal of the voltage-controlled oscillator to the frequency of the input signal In the phase synchronization circuit including the frequency divider for matching, the free-running circuit calculates the amplitude value of the output signal of the input disconnection detection circuit, the constant voltage generation circuit, and the low-pass filter that detects the disconnection of the input signal. An amplitude limiting circuit for limiting, a synchronization detection circuit for detecting whether or not a synchronization state is detected based on a phase difference between an input signal input to a phase comparator and a comparison signal, and a synchronization state by the synchronization detection circuit The detection signal, and an analog selector for switching from the output signal of the constant voltage generating circuit in the output signal of the amplitude limiting circuit.

  The output signal of the low-pass filter is held by a capacitor, and when the input signal is cut off, the voltage held by the capacitor is used as the control voltage of the voltage controlled oscillator, thereby suppressing fluctuations in the output signal frequency when the input signal is cut off. Can do. Also, by limiting the range of the control voltage in the synchronous state, the control voltage until the input signal disconnection detection and the constant voltage from the constant voltage generation circuit can be made substantially the same, so the output when the input signal is disconnected Variations in signal frequency can be suppressed.

  Referring to FIG. 3, the phase synchronization circuit of the present invention includes a phase comparator 1 that compares the phases of the input signal IN and the comparison signal, a charge pump 2 that receives the output signal of the phase comparator 1, and the charge A low-pass filter 3 for inputting the output signal of the pump 2, a self-running circuit 4 for inputting the output signal of the low-pass filter 3, a voltage-controlled oscillator 5 for inputting the output signal of the free-running circuit 4 as a control voltage, A phase locked loop circuit including a frequency divider 6 for causing the frequency fo of the output signal of the voltage controlled oscillator 5 to coincide with the frequency fr of the input signal IN. The free-running circuit 4 detects the disconnection of the input signal IN. The input disconnection detection circuit 11, the constant voltage generation circuit 13, the output signal of the low-pass filter 3 and the output signal of the constant voltage generation circuit 13 are switched by the detection signal from the input disconnection detection circuit 11. An analog selector 12 that is input to the control oscillator 5 as a control voltage, a synchronization detection circuit 16 that detects whether or not a synchronization state is established based on the phase difference between the input signal IN and the comparison signal input to the phase comparator 1, and the synchronization A switching unit 15 that is turned on by a detection signal in the synchronization state from the detection circuit 16 and a capacitor 14 that receives and holds the output signal of the low-pass filter 3 via the switching unit 15 that is turned on are provided. Yes.

  FIG. 1 is an explanatory diagram of Embodiment 1 of the present invention, where 1 is a phase comparator, 2 is a charge pump, 3 is a low-pass filter, 4 is a free-running circuit, 5 is a voltage controlled oscillator (VCO), and 6 is a minute Reference numeral 11 denotes an input disconnection detection circuit, 12 denotes an analog selector, 13 denotes a constant voltage generation circuit, and 14 denotes a capacitor. Further, IN is an input signal, OUT is an output signal, fr is an input signal frequency (reference frequency), fo is an output signal frequency, and fp is a divided output signal frequency (comparison frequency).

  The basic configuration of the phase locked loop (PLL) that outputs the output signal 0UT synchronized with the phase of the input signal IN from the voltage controlled oscillator 5 is the same as that of the conventional example, but the output of the low-pass filter 3 is connected to the free-running circuit 4. The signal, that is, the control voltage of the voltage controlled oscillator 5 is held by the capacitor 14. By holding the output signal of the low-pass filter 3 immediately before the input signal is interrupted by the capacitor 14, until the analog selector 12 switches the control voltage of the voltage controlled oscillator 5 to the constant voltage from the constant voltage generating circuit 13, The voltage held in the capacitor 14 can be input as a control voltage to the voltage controlled oscillator 5 to suppress fluctuations in the output signal frequency fo of the voltage controlled oscillator 4.

  FIG. 2 is a diagram for explaining the operation of the configuration shown in FIG. 1. The reference frequency fr, the comparison frequency fp, the output signal of the charge pump 2, the output signal of the low-pass filter 3, input to the phase comparator 1 The control voltage of the VCO (voltage controlled oscillator) output from the running circuit 4 is shown for the pull-in state, the synchronization state, the input disconnection state, and the free-running state, respectively, and the phase difference between the reference frequency fr and the comparison frequency fp is large. In the synchronized state in which the phase difference is zero or within a predetermined range from the retracted state, the control voltage maintains a substantially constant value. When the input signal is interrupted, the output signal of the low-pass filter 3 is gradually lowered by being held by the capacitor 14. Therefore, until the analog selector 12 of the free-running circuit 4 switches to the voltage from the constant voltage generation circuit 13 (input cut-off state), the free-running circuit output (VCO control voltage) is detected from the input cut-off ( In the period up to (indicated by an arrow), the output is only slightly reduced in response to the gradual decrease in the low-pass filter output, and therefore the fluctuation of the frequency fo of the output signal OUT due to the input interruption can be suppressed.

  FIG. 3 is an explanatory diagram of the second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same names, 15 denotes a switching unit, and 16 denotes a synchronization detection unit. FIG. 4 is an operation explanatory diagram corresponding to FIG. 2 in the second embodiment. In the second embodiment, the capacitor 14 is configured to add the output signal of the low-pass filter 3 via the switching unit 15, and the signals of the reference frequency fr and the comparison frequency fp are input to the synchronization detection circuit 16. When the phase difference is zero or within a predetermined range, it has a function of determining that it is in a synchronized state, and in other cases it is determined that it is out of synchronization. In the case of connection to the low-pass filter 3 and determination of out-of-synchronization, the switching unit 15 is controlled to be turned off, and the capacitor 14 is disconnected from the low-pass filter 3.

  Accordingly, the capacitor 14 is disconnected from the low-pass filter 3 in the pull-in state before the synchronous state is reached, so that the low-pass filter output corresponds to the phase difference from the phase comparator 1. It changes stepwise according to the output signal and becomes substantially flat in the synchronized state, and the capacitor 14 is connected to the low-pass filter 3 by the switching unit 5, and the output signal of the low-pass filter 3 is held by the capacitor 14. To do. When the input is cut off, the voltage held by the capacitor 14 gradually decreases as shown as the low-pass filter output, and even at the point of time when the input cut is detected indicated by the arrow, the analog selector 12 is detected by this input cut detection. Therefore, the output signal frequency fo of the voltage controlled oscillator 5 can be set to substantially the same output signal frequency as that in the synchronized state. That is, even when the input is interrupted, a large fluctuation in the output signal frequency fo of the voltage controlled oscillator 5 can be suppressed. In the retracted state, the capacitor 14 is disconnected from the low-pass filter 3 by the switching unit 15, so that the loop gain of the feedback loop is the loop gain in the conventional example that does not include the capacitor 14. The normal pull-in characteristics can be obtained.

  The synchronization detection circuit 16 can apply various configurations for determining a synchronization state when the phase difference between the reference frequency fr and the comparison frequency fp is within a predetermined range. For example, the output detection signal OUT Whether the synchronization state or the out-of-synchronization state is based on the counter that counts, the synchronous range and asynchronous range determined by the logical processing of the counter output and the comparison frequency fp, and the rising timing of the input signal of the reference frequency fr It can also be set as the structure determined.

  FIG. 5 is an explanatory diagram of the detection operation of an example of the synchronization detection circuit, showing the definition of the synchronization range, the LOCK signal output as the synchronization detection signal, and the UNLOCK signal output as the out of synchronization detection signal. The definition is such that the output signal OUT is counted by a counter (not shown) of the synchronization detection circuit 16 (see FIG. 3), and the count value 0 to 1577 indicates one cycle of the comparison frequency fp. NORMAL PULSE having a value within a range of 939 to 0 to 639 as a synchronization range is output.

  In the case of the LOCK signal output indicating the synchronization state, the rising edge of the signal of the reference frequency fr in the synchronization state is within the range of NORMAL PULSE, and the LOCK / UNLOCK signal is at the high level indicating the synchronization state. In the case of UNLOCK signal output indicating an out-of-synchronization state, the rising edge of the fr (reference frequency) signal in the asynchronous state is within the range of DRIFT PULSE indicating the out-of-synchronization range, and the LOCK / UNLOCK signal indicates the out-of-synchronization state. Become low level. Therefore, the synchronization detection circuit 16 determines that the synchronization state is established when the phase difference between the signal of the reference frequency fr and the signal of the comparison frequency fp falls within a predetermined range, and the LOCK / UNLOCK signal is sent to the switching unit 15. In addition, it can be configured to be on when high and off when low.

  FIG. 6 shows an example of the configuration of the capacitor 14 and the switching unit 15 of the free-running circuit. (3) is the low-pass filter 3 side, (12) is the analog selector 12 side, and (16) is the synchronization detection circuit 16. The switching unit 15 is configured by an integrated circuit. The above-mentioned LOCK / UNLOCK signal is input from the synchronization detection circuit 16 to the terminal A, the capacitor 14 is connected to the terminal X1, and the terminal X is connected to the low-pass filter 3 side. This terminal X is connected to the terminal X0 when the terminal A is at a low level in an asynchronous state, and the switching unit 15 is turned off. At the high level indicating the synchronous state, it is connected to the terminal X1, the switching unit 15 is turned on, and the capacitor 14 is connected to the low-pass filter 3.

  FIG. 7 is an explanatory diagram of a main part of the third embodiment of the present invention, and the same reference numerals as those in FIGS. Reference numeral 18 denotes an amplitude limiting circuit, and a phase comparator, a charge pump, and a frequency divider are not shown. The amplitude limiter circuit 18 limits the amplitude range of the output signal of the low-pass filter 3, that is, the control voltage of the voltage controlled oscillator 5, thereby suppressing fluctuations in the frequency of the output signal even when the input signal is interrupted. is there.

  FIG. 8 is an operation explanatory view similar to FIG. 2 and FIG. 4 described above, and similarly to FIG. 1 and FIG. 3, the reference frequency fr, the comparison frequency fp, and the output signal of the charge pump input to the phase comparator 1. And the output signal of the low-pass filter 3 and the free-running circuit output (VCO (Voltage Controlled Oscillator) control voltage) are shown for the pull-in state, the synchronization state, the input cut-off state, and the free-running state. In a synchronized state where the phase difference between the reference frequency fr and the comparison frequency fp is large and the phase difference is zero or within a predetermined range, the control voltage input to the voltage controlled oscillator 5 maintains a substantially constant value. To do.

  When the input signal is interrupted, the output signal of the low-pass filter 3 rapidly decreases as shown as the low-pass filter output. Since the change of the output signal of the low-pass filter 3 is limited by the amplitude limiting circuit 18, the value is in accordance with the limit value, and during that time, the input disconnection detection circuit 11 performs the input disconnection detection at the timing indicated by the arrow. Since the analog selector 12 is controlled and the constant voltage from the constant voltage generation circuit 13 is used as the control voltage of the voltage controlled oscillator 5, the fluctuation of the output signal frequency fo of the voltage controlled oscillator 5 becomes a slight value.

  FIG. 9 shows an example of the configuration of the amplitude limiting circuit 18 described above. U1A and U2A are operational amplifiers, R7 to R9 are resistors, D1 and D2 are diodes, V2 and V5 are reference voltages, and V3, V4. V6 and V7 indicate operating voltages, (3) indicates the low-pass filter 3 side, and (12) indicates the analog selector 12 side. When the output signal of the low-pass filter 3 exceeds the reference voltage V2, the operational amplifier U1A enters a low-level output state, and configures an upper limit limiting unit that suppresses the upper limit of the output signal of the low-pass filter 3 via the diode D1. When the output signal of the low-pass filter 3 drops below the reference voltage V5, the amplifier U2A enters a high-level output state and constitutes a lower limit limiting unit that suppresses the lower limit of the output signal of the low-pass filter 3 via the diode D2. The positive and negative output signals of the filter 3 can be limited to amplitude values according to the reference voltages V2 and V5.

  FIG. 10 is an explanatory diagram of a main part of the fourth embodiment of the present invention. The same reference numerals as those in FIGS. 1, 3, and 7 denote the same parts, and the phase comparator 1, the charge pump 2, the frequency divider 7 and the like. The illustration is omitted for. As shown in FIG. 7, in the state where the amplitude limiting circuit 18 is always connected between the low-pass filter 3 and the analog selector 12, when the synchronization pull-in range becomes narrow, the synchronization detection circuit 16 detects the synchronization state. Stops the amplitude limiting function of the amplitude limiting circuit 18, and operates the amplitude limiting function by detecting the synchronization state. The reference frequency fr, comparison frequency fp, charge pump output, low-pass filter output, and free-running circuit output (VCO control voltage) in the fourth embodiment are the same as those shown in FIG.

  In FIG. 11, the signal LOCK / UNLOCK indicating the synchronization state or the synchronization loss from the synchronization detection circuit 16 is input to the amplitude limiting circuit 18 described above, and the low-pass filter 3 side (3) and the analog selector 12 side (12) 1 shows a configuration of a main part provided with an integrated circuit selector 19 for selecting whether or not to connect an upper limit limiting unit and a lower limit limiting unit, and an operational amplifier U1A is connected to a terminal X1 of the selector 19 Is connected to the terminal Y1, so that the LOCK / UNLOCK signal from the synchronization detection circuit 16 is input to the terminal A.

  When a signal indicating the synchronization state from the synchronization detection circuit 16 is input to the terminal A, the terminals X and X1 and the terminals Y and Y1 are connected, and the amplitude limiting circuit 18 sets the upper and lower limits of the output signal of the low-pass filter 3. Restrict. When a signal indicating loss of synchronization is input to the terminal A, the terminals X and X0 and the terminals Y and Y0 are connected, and the low-pass filter 3 and the amplitude limiting circuit 18 are disconnected from each other. There is no restriction on the control voltage, and a quick synchronization pull-in can be performed. By limiting the amplitude value of the output signal of the low-pass filter 3 by the amplitude limiting circuit 18 described above, fluctuations in the output signal frequency fo of the voltage controlled oscillator 5 when the input is cut off from the synchronized state can be suppressed. .

It is explanatory drawing of Example 1 of this invention. It is operation | movement explanatory drawing of Example 1 of this invention. It is explanatory drawing of Example 2 of this invention. It is operation | movement explanatory drawing of Example 2 of this invention. It is explanatory drawing of the synchronous detection process of Example 2 of this invention. It is explanatory drawing of a switch part. It is principal part explanatory drawing of Example 3 of this invention. It is operation | movement explanatory drawing of Example 3 of this invention. It is explanatory drawing of an amplitude limiting circuit. It is principal part explanatory drawing of Example 4 of this invention. It is explanatory drawing of the amplitude limiting circuit containing a selector. It is explanatory drawing of the phase locked loop of a prior art example. It is explanatory drawing of the free-running circuit of a prior art example. It is explanatory drawing of an analog selector. It is operation | movement explanatory drawing of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Charge pump 3 Low pass filter 4 Self-running circuit 5 Voltage controlled oscillator (VCO)
6 Frequency Divider 11 Input Break Detection Circuit 12 Analog Selector 13 Constant Voltage Generation Circuit 14 Capacitor 15 Switching Unit 16 Synchronization Detection Circuit 18 Amplitude Limiting Circuit

Claims (4)

A phase comparator for comparing phases of an input signal and a comparison signal, a charge pump for inputting an output signal of the phase comparator, a low pass filter for inputting an output signal of the charge pump, and an output signal of the low pass filter An input free-running circuit, a voltage-controlled oscillator that inputs an output signal of the free-running circuit as a control voltage, and a frequency divider for making the frequency of the output signal of the voltage-controlled oscillator coincide with the frequency of the input signal In the phase synchronization circuit including:
The free-running circuit includes an input disconnection detection circuit that detects disconnection of the input signal, a constant voltage generation circuit, an output signal of the low-pass filter, and an output signal of the constant voltage generation circuit from the input disconnection detection circuit. A phase-locked loop comprising: an analog selector that switches according to a detection signal and inputs it as a control voltage to the voltage-controlled oscillator; and a capacitor that holds an output signal of the low-pass filter.   The free-running circuit includes an input disconnection detection circuit that detects disconnection of the input signal, a constant voltage generation circuit, an output signal of the low-pass filter, and an output signal of the constant voltage generation circuit from the input disconnection detection circuit. Synchronous detection that detects whether or not a synchronization state is established based on a phase difference between the input signal and the comparison signal that are input to the phase comparator and an analog selector that is switched by a detection signal and is input to the voltage controlled oscillator as a control voltage A circuit, a switching unit that is turned on by a detection signal of the synchronization state from the synchronization detection circuit, and a capacitor that receives and holds the output signal of the low-pass filter via the switching unit that is turned on 2. The phase locked loop circuit according to claim 1, wherein A phase comparator for comparing phases of an input signal and a comparison signal, a charge pump for inputting an output signal of the phase comparator, a low pass filter for inputting an output signal of the charge pump, and an output signal of the low pass filter An input free-running circuit, a voltage-controlled oscillator that inputs an output signal of the free-running circuit as a control voltage, and a frequency divider for making the frequency of the output signal of the voltage-controlled oscillator coincide with the frequency of the input signal In the phase synchronization circuit including:
The free-running circuit includes an input disconnection detection circuit that detects disconnection of the input signal, a constant voltage generation circuit, an amplitude limiting circuit that limits an amplitude value of an output signal of the low-pass filter, and an output signal of the amplitude limiting circuit And an analog selector that switches the output signal of the constant voltage generation circuit according to a detection signal from the input disconnection detection circuit and inputs it as a control voltage to the voltage controlled oscillator. A phase comparator for comparing phases of an input signal and a comparison signal, a charge pump for inputting an output signal of the phase comparator, a low pass filter for inputting an output signal of the charge pump, and an output signal of the low pass filter An input free-running circuit, a voltage-controlled oscillator that inputs an output signal of the free-running circuit as a control voltage, and a frequency divider for making the frequency of the output signal of the voltage-controlled oscillator coincide with the frequency of the input signal In the phase synchronization circuit including:
The free-running circuit inputs an input disconnection detection circuit that detects the disconnection of the input signal, a constant voltage generation circuit, an amplitude limiting circuit that limits an amplitude value of an output signal of the low-pass filter, and inputs to the phase comparator A synchronization detection circuit that detects whether or not a synchronization state is detected based on a phase difference between the input signal and the comparison signal; and an output signal of the constant voltage generation circuit based on a detection signal of the synchronization state by the synchronization detection circuit. A phase synchronization circuit comprising an analog selector for switching to an output signal.

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