JP2585221B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a digital phase locked loop (hereinafter referred to as DPLL) circuit for obtaining a signal synchronized in phase with a certain reference signal.
The abbreviated circuit is applicable to a wide range of applications such as frequency synthesis, conversion and signal synchronization establishment and demodulation in communication.

2. Description of the Related Art Conventionally, various types of DPLL circuits have been proposed, but basically have a configuration as shown in FIG.
In FIG. 2, 11 is a phase comparator, 12 is a loop filter, 13 is a voltage controlled oscillator (VCO), 14 is a reference signal input terminal to which a reference signal RS is supplied, and 15 is a synchronization signal to which a synchronization signal SS is supplied. An input terminal, PS is a phase difference signal, and VS is a control voltage signal.

In the configuration as described above, the phase difference between the reference signal RS and the synchronization signal SS is detected by the phase comparator 11, and this phase difference is supplied to the next-stage loop filter 12 as the phase difference signal PS. The signal that has passed through the loop filter 12 is supplied to the voltage control oscillator 13 as a control voltage signal VS. As a result, a synchronization signal is supplied from the voltage controlled oscillator 13 to the phase comparator 11, and a desired synchronization signal is obtained by repeating the above operation.

By the way, in the DPLL circuit, the above voltage controlled oscillator
Numeral 13 denotes a programmable counter, which changes the frequency division ratio in accordance with the result of comparison by the phase comparator 11. Then, the base clock is frequency-divided according to the frequency division ratio to generate a synchronization signal.

As a practical circuit, in order to increase the maximum operating frequency, a prescaler is provided as an auxiliary circuit at the input terminal of the reference signal RS of the phase comparator 11 so that the frequency of the reference signal RS can be divided by the program counter. Some measures such as lowering the area are taken.

As described above, in the conventional DPLL circuit, since the synchronization signal is obtained by dividing the reference clock, the time resolution related to synchronization is given by one cycle of the reference clock to be used. Therefore, a high frequency clock signal is required to obtain a high time resolution. For this reason, a high-frequency clock signal generating circuit, a high-speed counter, and the like are required, which makes the design difficult and requires a high level of manufacturing process technology.

(Problems to be Solved by the Invention) As described above, in the conventional phase locked loop circuit, it was difficult to obtain a high time resolution using a low frequency reference clock.

Accordingly, the present invention has been made to eliminate the above-mentioned disadvantages, and can provide a high time resolution even when a reference clock having a relatively low frequency is used, and can greatly reduce the pull-in time required for establishing synchronization. It is an object of the present invention to provide a phase locked loop circuit.

[Configuration of the Invention] (Means for Solving the Problems) That is, a phase synchronization circuit of the present invention includes a phase difference detection circuit for detecting a phase difference between a reference signal and a synchronization signal, and a phase difference detection circuit. Based on the phase difference signal output from the circuit, one clock signal is selected and output from m-phase clock signals shifted in phase by 2π / m, and the division ratio of the selected clock signal is specified. And a clock signal output from the selection circuit and a signal designating a frequency division ratio are supplied. The selected clock signal is frequency-divided at the frequency division ratio to detect the phase difference amount. And a programmable counter for supplying a synchronization signal to the circuit, wherein the division ratio of the programmable counter is N, and the length of one cycle of the synchronization signal is 2πN and the length of one cycle of the reference signal is actually To equal, when the Δθ the phase difference between the reference signal and the synchronization signal, (Where i represents the difference between the clock signal to be selected next and the currently used clock signal, and n represents the increase or decrease of the frequency division ratio when dividing the clock signal). When Δθ is small, phase synchronization is performed by selecting a clock signal. For a large phase difference Δθ, the division ratio of the programmable counter is specified by the selection circuit based on the phase difference amount signal, and the programmable counter is selected. The synchronization signal is obtained by selecting a clock signal whose phase is closest to the reference signal from the m-phase clock signals and dividing the frequency.

(Operation) In the phase locked loop circuit according to the present invention, the selecting circuit selects the clock signal whose phase is closest to the reference signal from the m-phase clock signals shifted in phase by 2π / m, and specifies the frequency division ratio. Then, the synchronization signal is obtained by dividing the frequency of the selected clock signal by the above division ratio using a programmable counter. When the phase difference between the reference signal and the synchronization signal is small, phase synchronization is performed by selecting a clock signal, and a large phase difference is dealt with by changing the frequency division ratio. .

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 16 denotes a phase difference detection circuit. The phase difference detection circuit 16 detects the phase difference between the reference signal RS and the synchronization signal SS supplied from the reference signal input terminal 14 and the synchronization signal input terminal 15, respectively. Detect quantitatively. The phase difference amount signal PMS output from the phase difference amount detection circuit 16 is
Supplied to 7. This selection circuit 17 is supplied with m-phase clock signals f _{0 to} fm ₋₁ shifted in phase by 2π / m,
The selected clock signal fi and its division ratio N are supplied to the programmable counter 18. Now, m-phase clock signals f ₀ to
When one cycle of fm _-1 is considered as a unit of phase (2π radian), when the division ratio of the programmable counter is N, the length of one cycle of the synchronization signal SS is 2πN, which is almost equal to that of the reference signal RS. Equal to the length of one cycle, the phase difference Δθ between the reference signal RS and the synchronization signal SS, (I, n: any integer). Therefore, the above equation is discretized to calculate the phase difference. , I represents the difference between the clock signal to be selected next and the currently used clock signal, and n represents the increase or decrease of the frequency division ratio when dividing this clock signal. That is, m
A synchronization signal SS obtained by dividing a certain clock signal fp in the phase clock signals f _{0 to} fm _{-1 by} a dividing ratio 1 / N, and a reference signal R
If the phase difference from S is 2πi / m + 2πn, the next clock signal to be selected is fp ₊ i, and the frequency division ratio is 1 / (N + n). That is, when the phase difference Δθ is small, the phase synchronization is performed by selecting the clock signal, and the large phase difference Δθ is handled by changing the frequency division ratio. The selection circuit
The outputs n and fi of 17 correspond to the above (N + n) and fp ₊ i, respectively. Such selection is performed by the selection circuit 17 described above.
Done by In response to the designation of the frequency division ratio and the clock signal to be used, the clock signal is frequency-divided by the programmable counter 18, and the synchronization signal is supplied to the phase difference detection circuit 16.

If the frequency to be synchronized is known in advance, the programmable counter 18 is unnecessary, and may be a fixed counter capable of generating a signal having a target frequency based on a clock signal. In this case, the selection circuit 17
Is the phase difference Therefore, it is necessary to search for and select the next clock signal to be selected beyond one cycle of the clock signal. Therefore, the clock signal is switched and the counter is reset before the counter that divides the frequency by the fixed frequency division ratio can not always divide the clock signal. As a result, a signal synchronized with the reference signal RS is obtained.

According to such a configuration, a high time resolution can be obtained without increasing the frequency of the clock signal. For example, in the circuit of FIG. 2, the time resolution is determined by the frequency of the clock signal used in the voltage controlled oscillator 13, and if this is F (Hz), the time resolution is 1 / F (sec). On the other hand, since the circuit of FIG. 1 uses an m-phase clock signal, the time resolution is 1 / mF (sec). As described above, in the circuit of FIG. 2, there is a technical barrier because the upper limit of the frequency of the clock signal that can be used is limited by the element to be used, but the circuit of FIG. If the number is increased, the time resolution can be improved accordingly. That is, it is possible to improve the time resolution without increasing the frequency of the clock signal.

The DPLL circuit of FIG. 2 establishes synchronization only by changing the frequency division ratio, whereas the circuit of FIG.
Since the synchronization signal is generated by selecting the clock signal whose phase is closest to the reference signal from the clock signals of the phases, the time required for establishing the synchronization decreases as the number m of clock signals used increases.

Note that the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, a prescaler may be provided at the input terminal of the phase difference amount detection circuit 16. Also, when using a counter that performs frequency division with a fixed frequency division ratio, it has been described that the frequency of the signal to be synchronized is known, but even if it is unknown, the frequency of the m-phase clock signal is changed according to the frequency of the reference signal. This can be handled by adding a circuit for adjusting.

[Effects of the Invention] As described above, according to the present invention, a high time resolution can be obtained even when a reference clock having a relatively low frequency is used, and the pull-in time required for establishing synchronization is greatly reduced. A phase locked loop circuit is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a phase locked loop circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional phase locked loop circuit. RS ...... reference signal, SS ...... synchronizing signal, 16 ...... phase difference detection circuit, f ₀ ~fm _-1 ...... m phase of the clock signal, 17 ...... selection circuit, 18 ...... programmable counter.

Claims (1)

(57) [Claims] 1. A phase difference detection circuit for detecting a phase difference between a reference signal and a synchronization signal, and a phase shift of 2π / m based on the phase difference signal output from the phase difference detection circuit. a selection circuit that selects and outputs one clock signal from m-phase clock signals, and outputs a signal that specifies a frequency division ratio of the selected clock signal; A programmable counter supplied with a signal designating a frequency division ratio, dividing the selected clock signal by the frequency division ratio, and supplying the signal as a synchronization signal to the phase difference amount detection circuit; Assuming that the ratio is N, the length of one cycle of the synchronization signal is 2πN and substantially equal to the length of one cycle of the reference signal, and when the phase difference between the reference signal and the synchronization signal is Δθ, (Where i represents the difference between the clock signal to be selected next and the currently used clock signal, and n represents the increase or decrease of the frequency division ratio when dividing the clock signal). When Δθ is small, phase synchronization is performed by selecting a clock signal. For a large phase difference Δθ, the division ratio of the programmable counter is specified by the selection circuit based on the phase difference amount signal, and the programmable counter is selected. Wherein a clock signal having the phase closest to the reference signal is selected from the m-phase clock signals and frequency-divided to obtain a synchronization signal.