JPH05167440A - Out of synchronism detection circuit - Google Patents

Abstract

PURPOSE:To provide the out of synchronism detection circuit detecting a phase shift and out of synchronism in a phase locked loop oscillator circuit. CONSTITUTION:A phase locked oscillator circuit 1 is provided with a phase shift means 20 shifting a phase of any of an input clock signal (f) and a phase comparison clock signal f0 being an output of a frequency divider 5, a flip-flop 30 storing a clock signal phase-shifted at a change point of the clock signal not shifted in the two inputted clock signals and a change detection means 40 detecting a change in a phase state of the clock signal by the flip-flop 30 in addition, and any of the input clock signal (f) and the phase comparison clock signal f0 is shifted and the result is inputted to the flip-flop 30 to store the clock signal phase-shifted at a change point of the clock signal not phase- shifted and when a change takes place in the output due to a phase shift or the like between the two clock signals, the change detection means 40 raises an alarm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting out-of-sync and frequency shift in a phase locked oscillator circuit.

In recent years, digital communication lines have come into wide use, but the synchronization of the clock signal sent from the transmission side, which is the basis of data transmission / reception, and the clock signal generated at the reception side. It is essential that the synchronization be exactly the same. Therefore, there is a strong demand for early detection and early stabilization of the phase shift between the transmitting clock signal and the receiving clock signal.

[0003]

2. Description of the Related Art Abnormalities in a conventional phase-locked oscillator circuit are detected by a drift detection method which monitors a frequency shift between an input clock signal and a clock signal generated and output at a receiving side, or this drift detection is performed by low frequency filtering. A drift alarm is issued by comparing the error voltage output from the device LPF with a predetermined voltage Es in a comparison circuit. However, because of the voltage comparison, the disadvantage that even a subtle drift cannot be detected is improved. It is detected by the drift detection method of the voltage controlled oscillator VCO as shown.

In FIG. 6, 1 is a phase-locked oscillator circuit,
2 is a phase comparator PC, 3 is a low frequency filter LPF, 4 is a voltage controlled oscillator VCO, 5 is a frequency divider DIV, 51 and 52 are pulse generation circuits PG1, PG2, 53 and 54 are D-type flip-flops D-. FF1, D-FF2, 55 are OR circuits OR.

The phase comparison clock signal f ₀ , which is the output of the frequency divider 5, and the input clock signal f are supplied to the first and second sections, respectively.
Pulse generator circuits 51 and 52. The first and second pulse generating circuits 51 and 52 are composed of a monostable multivibrator or the like, and the monostable multivibrator is formed by the rising portions of the input clock signal f and the frequency divider output phase comparison clock signal f _0. A pulse having a predetermined width determined by the time constants of the resistor R and the capacitor C is formed.

The output of the first pulse generating circuit 51 is given to the D input terminal of the first D-type flip-flop 53, and the output of the second pulse generating circuit 52 is also the D-type of the second D-type flip-flop 54. The input clock signal f is applied to the C input terminal of the first D-type flip-flop 53, and the phase comparison clock signal f ₀ is applied to the C input terminal of the second D-type flip-flop 54. Be done. The outputs of the first and second D-type flip-flops 53 and 54 are input to the OR circuit 55, and the outputs are sent to the alarm circuit.

When the phase comparison clock signal f ₀ output from the frequency divider 5 fluctuates due to an abnormality of the voltage controlled oscillator 4 or the like, the second D flip-flop 54 receives the input clock signal f, and When the input clock signal fluctuates, the phase comparison clock signal output from the frequency divider 5 is used for reading, and the fluctuations of the voltage-controlled oscillator 4 or the input side are also detected in order to read each other's input / output clock signals. Is possible. That is, when the phase of the reference signal f is delayed by a specific time compared with the output phase comparison clock signal f _{0 of the} voltage controlled oscillator 4, the output of the second D-type flip-flop 54 becomes “1”, and the input clock signal As compared with the phase of f, the output of the first D-type flip-flop 33 becomes "1" when it advances by a specific time. Therefore, the OR circuit 5
The output of 5 becomes "1" when the drift is detected.

[0008]

However, in the voltage controlled oscillator drift abnormality detection circuit having such a configuration, since the monostable multivibrator or the like is used as the first and second pulse generation circuits 51 and 52,
Since an accurate pulse width cannot be created, it is difficult to perform accurate measurement, and there is a drawback that adjustment is time-consuming because the resistor R and the capacitor C are adjusted to determine the pulse width.

The drift detection basically monitors deterioration of the output frequency due to aging or aging of the voltage controlled oscillator, and therefore does not monitor the out-of-synchronization frequency.

An object of the present invention is to solve such a problem, and an object thereof is to provide an out-of-sync detecting circuit for detecting a phase shift or out-of-sync in a phase-locked oscillator circuit.

[0011]

FIG. 1 is an example of a principle configuration diagram of an out-of-synchronization detection circuit according to the present invention, showing a case where a phase comparison clock signal of two clock signals is phase-shifted.

In the figure, the same reference numerals as those in FIG.
20 is a phase shift means, 30 is a flip-flop, 40 is change
It is a detection means. The present invention uses a reference input on one of the input terminals.
The clock signal f is input and the other input terminal of the frequency divider 5
Output phase comparison clock signal f₀Enter the phase
And a phase comparator 2 for comparison and connected to the phase comparator 2.
Low frequency filter 3 and the input through the low frequency filter 3.
The oscillation frequency is controlled according to the output of the phase comparator.
The voltage-controlled oscillator 4 and the output signal of the voltage-controlled oscillator 4 are separated.
It is composed of a frequency divider 5 which divides the frequency and sends it to the phase comparator 2.
The phase comparison clock signal f₀And the input clock signal
Obtain the phase difference from f so that the phase difference is less than a predetermined value.
Control the oscillation frequency of the voltage controlled oscillator 4 to
The output of the voltage controlled oscillator 4 synchronized with the clock signal f
In the phase-locked oscillator circuit 1 to be taken out, the phase comparison clock
Lock signal f ₀And the phase difference of the input clock signal f
The phase of one of the clock signals so that it becomes a constant value
And a clock signal that is not phase-shifted.
Phase state of clock signal phase-shifted at signal change point
Flip floppy to store and always update
And the clock stored in the flip-flop 30.
When a change in the phase state of the
By providing the change detection means 40 for sending
Can be achieved.

Further, instead of the change detecting means 40, a counting means 41 is provided on the output side of the flip-flop 30, which counts the output changed in a constant cycle and outputs an alarm when the set number of counts is exceeded. It may be added.

[0014]

The phase shift oscillator circuit 1 is provided with the phase shift means 20, the flip-flop 30, and the change detection means 40, and the frequency divider 5 is added.
Of the phase comparison clock signal f ₀ or the input clock signal f, which is the output of the above, is shifted by a predetermined value, and these two signals are input to the flip-flop 30 to obtain the phase. If there is a change in the phase difference between these two signals at the change point of the clock signal that does not shift, it can be detected. Therefore, in the phase-locked oscillator circuit 1, the input clock signal f and the phase comparison clock signal f ₀ If an abnormality such as a phase shift occurs during the period, the change detection means 40 can detect the abnormality and issue an alarm.

Further, instead of the change detecting means 40, the output of the flip-flop 30 counts the output signal corresponding to the phase difference between the input clock signal f output from the flip-flop 30 and the phase comparison clock signal f _0. By adding the counting means 41, an alarm is generated when the pulse corresponding to the frequency difference counts a preset value for a certain time, so that the frequency oscillated by the voltage controlled oscillator 4 with arbitrary accuracy. Can be monitored.

[0016]

EXAMPLES Next, examples will be described with reference to FIGS. 2, 3, 4, and 5. 2 is a diagram showing a first embodiment of the present invention, in which the same reference numerals as those in FIG. 1 indicate the same components, 21 is a 1 / 2π delay circuit, 30 is a D-type flip-flop, and 41 is
Is a change detector. FIG. 3 is a waveform explanatory diagram of the out-of-synchronization detection circuit of FIG. 2. In FIG.
Show the same place as.

FIG. 4 is a diagram showing a second embodiment of the present invention, in which the same reference numerals as those in FIG. 1 indicate the same components, 43 is a timer, 42 is a protection counter, and 44 is an alarm signal generator. FIG. 5 is a waveform explanatory diagram of the out-of-synchronization detection circuit of FIG. 4, in which ˜ indicates the same place as ˜ on the circuit of FIG.

In FIG. 2, when the phase-locked oscillator circuit 1 is in the synchronous state, the input clock signal f and the phase comparison clock signal f ₀ output from the frequency divider 5 have a certain phase. A signal obtained by delaying the phase comparison clock signal by a 1 / 2π delay circuit 21 by a 1 / 2π phase is input to the D terminal of the D-type flip-flop 30, and the input clock signal f is input to the C terminal of the D-type flip-flop 30. To do. In this synchronous state, the signal "0" is output to the output of the D-type flip-flop 30. Each of the waveforms is shown in FIG.

However, when an abnormality such as loss of synchronization occurs in the phase-locked oscillator circuit 1, the phase-locked oscillator circuit 1 goes out of synchronization, and FIG.
As a result of the change in the pulse width of the waveform of, the phase relationship between the waveforms changes, and the signal "1" is output to the output of the D-type flip-flop 30. This change is detected by the change detector 41 in the subsequent stage, and an alarm is issued.

Further, FIG. 4 shows a protection counter circuit 42 which uses the output signal of the D-type flip-flop 30 as a count, as the counting means 40 of FIG. 1 at the output of the D-type flip-flop 30, and the protection counter circuit 42. A clear signal is transmitted at regular time intervals, and the protection counter circuit 42
There is provided a timer 43 for clearing the count number of 1 and an alarm signal generator 44 for transmitting a clear signal for clearing the count number of the protection counter circuit 42 when the protection counter circuit 42 counts up. Here, the input clock signal of the timer 43 may be another clock signal generated in its own device instead of the clock signal of the transmission side.

Here, out-of-synchronization occurs in the phase-locked oscillator circuit 1, and, for example, as shown in (1) of FIG. 5, the frequency of the output phase comparison clock signal f ₀ of the frequency divider 5 becomes high. In the case, or as shown in (2) of FIG. 5, when the frequency of the output phase comparison clock signal f ₀ of the frequency divider 5 becomes low, the output of the D-type flip-flop 30 has "
0 "and" 1 "are alternately output periodically.

Protecting counter circuit 42 from timer 43
Then, a clear signal is periodically transmitted at regular intervals to clear the count number of the output signal from the D-type flip-flop 30 stored in the protection counter circuit 42.

If the count-up is completed before the clear signal from the timer 43 is input to the protection counter circuit 42, an alarm is output. in this case,
The count number of the protection counter circuit 42 becomes the amount of phase change of the two signals, and represents how much the phase has moved during the clear signal transmission cycle of the timer 43.
Since the frequency difference can be represented by the phase / time, by changing the clear signal transmission time period of the timer 43, an alarm can be issued when an arbitrary frequency difference occurs.

[0024]

As described above, according to the present invention,
Out-of-sync of the phase-locked oscillator circuit can be easily detected,
When the frequency difference between the input signal and the output signal is a certain value,
Moreover, since the frequency difference can be set arbitrarily, a great effect can be expected on the performance improvement of the phase locked oscillator circuit.

[Brief description of drawings]

FIG. 1 is an example of a principle block diagram of an out-of-sync detection circuit according to the present invention.

FIG. 2 is a first embodiment of the present invention.

FIG. 3 is a diagram illustrating a waveform of the out-of-sync detection circuit of FIG.

FIG. 4 is a second embodiment of the present invention.

5 is a diagram illustrating waveforms of the out-of-synchronization detection circuit of FIG.

FIG. 6 is a diagram showing an example of a conventional phase-locked oscillator circuit.

[Explanation of symbols]

 1 Phase-locked oscillator circuit (PLL) 2 Phase comparator (PC) 3 Low frequency filter (LPF) 4 Voltage controlled oscillator (VCO) 5 Frequency divider (DIV) 20 Phase shift means 21 1 / 2π delay circuit 30, 53 , 54 flip-flop (D-FF) 40 counting means 41 change detector 42 protection counter 43 timer 44 alarm signal generator 51, 52 pulse generation circuit (PG) 55 logical sum circuit (OR)

Claims (2)

[Claims] 1. A phase comparison is performed by inputting a reference input clock signal f to one input terminal and a phase comparison clock signal f ₀ output from a frequency divider (5) to the other input terminal. Of the phase comparator (2), the low frequency filter (3) connected to the phase comparator (2), and the phase comparator (2) input via the low frequency filter (3). A voltage controlled oscillator (4) whose oscillation frequency is controlled according to the output and an output signal of the voltage controlled oscillator (4) are frequency-divided and sent to the phase comparator (2) as a phase comparison clock signal f _0. And a frequency divider (5) for obtaining a phase difference between the phase comparison clock signal f ₀ and the input clock signal f, and the phase difference of the voltage controlled oscillator (4) is controlled so that the phase difference becomes a specified value or less. Output of the voltage controlled oscillator (4) which controls the oscillation frequency and is synchronized with the input clock signal f In the phase-locked oscillator circuit (1) for extracting the phase comparison clock signal f ₀ and the input clock signal f
Phase shift means (20) for shifting the phase of any one of the clock signals so that the phase difference of the clock signal becomes a predetermined value, and the clock signal that has been phase-shifted at a change point of the clock signal that is not phase-shifted. A flip-flop (30) that stores the phase state and always updates it to the latest state, and sends an alarm when it is detected that the phase state of the clock signal stored in the flip-flop (30) has changed An out-of-synchronization detection circuit having a change detection means (40). 2. The change detecting means is provided on the output side of the flip-flop (30), which counts the output changed at every constant period and outputs an alarm when the set count is exceeded. The out-of-sync detection circuit according to claim 1, which is added instead of (40).