JPH05243992A - Pll circuit - Google Patents

Abstract

PURPOSE:To provide a PLL circuit which shorten a lock-up time to improve response and extracts a synchronizing clock signal from among signals having a synchronizing clock signal pattern which can correctly provide VCO control voltage. CONSTITUTION:From a synchronizing separator circuit 1, the synchronizing signal pattern of a digital audio signal is extracted and provided for the phase comparator circuit 3 and the input signal presence/absence detection circuit 19 of the PLL circuit 2. When the input presence/absence detection circuit 19 judges an input signal to be absent, it generates a switching signal to switch a switch 21 to the side of a fixed control voltage selector 20 to directly provide control voltage selected-set by the fixed control voltage selector 20 for VCO 5 to make VCO 5 to oscillate with an oscillation frequency based on the control voltage. At the time of judging the input signal to be present, control voltage from a loop filter 4 is provided to VCO 5 and ordinary PLL operation is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a P which extracts a synchronous clock signal from signals having a synchronous clock signal pattern.
The present invention relates to an LL circuit, and more particularly to a PLL circuit that extracts a suitable synchronous clock signal for a signal transmitted intermittently.

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 3 is known as a receiving and demodulating circuit for an AES / EBU format digital audio signal which is a kind of digital audio signal having an intermittent signal. The conventional example shown in FIG. 3 will be described below. The AES / EBU format signal has a sync signal pattern. When a digital audio signal having this sync signal pattern is input, the sync separation circuit 1 first extracts the sync signal pattern. The synchronization signal pattern is supplied as a reference signal to the phase comparison circuit 3 of the PLL circuit 2 for phase synchronization. Here, the synchronization signal pattern is 2 in the sampling period.
The frequency of the reference signal is 2f.
_S (f _S is the sampling frequency).

The PLL circuit 2 includes the phase comparison circuit 3
In addition to the loop filter (low pass filter LPF) 4,
Voltage controlled oscillator (hereinafter referred to as VCO) 5, frequency divider 6
It consists of The phase comparison circuit 3 receives the reference signal REF supplied from the sync separation circuit 1 and VAR which is a frequency divider output signal, and supplies a phase difference detection signal to the loop filter 4.

The loop filter 4 comprises a phase comparison circuit 3
The high frequency component of the phase difference detection signal supplied from is removed, and this is supplied to the VCO 5 as the frequency control voltage of the VCO 5. The VCO 5 oscillates at a frequency controlled by the frequency control voltage supplied from the loop filter 4, supplies this to the frequency divider 6 and supplies it to the circuit in the subsequent stage. To reference signal and the phase comparison frequency 2f _S, the frequency divider 6, a carrier 128f _S of the digital audio signal of the AES / EBU format 6
The frequency is divided by 4 and input to the phase comparison circuit 3 to control the oscillation frequency of the VCO 5 to 128 f _S. And
The latter circuit demodulates the received data using the 128 f _S clock signal of VCO5.

In the PLL circuit 2, AES / EB
When the U format digital audio signal is not input, the reference signal is not generated, so the loop lock is released, the PLL circuit 2 operates to synchronize with the frequency of 0 Hz, and the VCO 5 oscillates at the lowest frequency (free run). Frequency) and the VCO 5 is in a free-run state. When the AES / EBU digital audio signal is input to the PLL circuit 2 in this state and the reference signal starts to be generated, the VCO 5 raises its oscillation frequency in order to lock it, but the VCO 5 pulls in from the free-run frequency. Therefore, there is a problem that the lockup time becomes long.

Therefore, in order to shorten the lockup time, a PLL circuit described below has been proposed. Figure 4
FIG. 1 shows an example of a PLL circuit proposed for shortening the lockup time in a PLL circuit for extracting a synchronous clock signal from a reproduction signal recorded on a recording medium (Japanese Utility Model Publication No. 2-8234). .. In FIG. 4, 7
Is a data detection circuit that is supplied with a reproduction signal and detects the presence or absence of the reproduction signal. Reference numeral 8 is a switch that operates by the output of the data detection circuit 7. Reference numeral 9 is a reference voltage generation circuit and a comparator. Is fed back to the input side of the LPF 4 to switch and set the LPF transfer function, 10 is a comparator constituting the LPF transfer function switching circuit, and 11 is a reference voltage generating circuit.

A reproduction signal from the magnetic recording / reproducing apparatus is supplied to the PLL.
It is added to the input terminal 12 of the circuit 2. The PLL circuit 2 extracts a clock signal from the reproduced signal, oscillates a synchronous clock signal synchronized with this clock signal, and outputs it from the output terminal 13. The intermittent reproduction signal supplied to the input terminal 12 is supplied to the phase comparison circuit 3 and the data detection circuit 7 of the PLL circuit 2. The data detection circuit 7 detects the reproduction signal and determines whether or not the reproduction signal level has reached a preset reference value. When the data detection circuit determines that there is input data, the output signal of the data detection circuit controls the switch 8 to turn off. On the other hand, when it is determined that the input reproduction signal level is equal to or lower than the reference value (no input data), the output signal of the data detection circuit operates to turn on the switch 8.

When the switch 8 is off, the LPF transfer function switching circuit 9 becomes an open loop, and the PLL circuit 2
Operates normally. There is recorded data of the playback signal,
When the reproduction signal is supplied to the phase comparison circuit 3 of the PLL circuit 2, the clock signal in the reproduction signal and the output signal of the VCO 5 are phase-compared, and the output signal of the VCO 5 is phase-locked with the clock signal of the reproduction signal to be accurate. It oscillates a synchronous clock signal in synchronization with and outputs it to the output terminal 13.

When the switch 8 is on, the control voltage of the VCO 5 passes through the switch 8 and the LPF transfer function switching circuit 9
Is supplied to the comparator 10. On the other hand, comparator 1
A reference voltage generation circuit 9 is connected to the input of 0, the reference voltage and the control voltage of the VCO 5 are compared, and the output signal of the comparison result is fed back to the input side of the LPF 4 of the PLL circuit 2. Comparator 1 fed back to the input side of LPF4
The output voltage of 0 becomes the bias voltage of LPF4 and becomes L
It is guided to the output of PF4 and operates as the control voltage of VCO5.

When the input terminal 12 has no signal, the control voltage of the VCO 5 becomes a voltage peculiar to the PLL circuit 2, and the VCO 5 oscillates at the free-run frequency controlled by this peculiar voltage. Is turned on, the LPF transfer function switching circuit 9 operates to apply a bias voltage to the LPF 4. The output voltage of the comparator 10 of the LPF transfer function switching circuit 9 becomes the reference voltage of the reference voltage generating circuit 11 and is supplied to the input side of the LPF 4. That is, the control voltage of the VCO 5 operates so as to be equal to the reference voltage of the LPF transfer function switching circuit 9, and the PLL circuit 2
The free-run frequency becomes the oscillation frequency whose voltage is controlled by this reference voltage.

As described above, the PLL circuit 2 can be arbitrarily set by the reference voltage of the LPF transfer function switching circuit 9 when there is no signal input. When there is no signal input, V set by the reference voltage
When the free-run frequency of CO5 is set close to the synchronous clock frequency oscillated by the synchronous clock signal by phase-locking to the clock signal of the input reproduction signal, the PLL circuit 2
The phase lock operation is smoothly switched depending on the presence / absence of an input signal, and the lockup time for frequency control of the VCO 5 is shortened to perform stable PLL operation.

However, although the lock-up time can be shortened in the above conventional example, there are the following problems. That is, since there is an operation of changing the transfer function of the loop filter, the constant of the loop filter has a large effect on the series of operations of the PLL circuit 2, and VC
It affects the lockup time of O5, and the response becomes slower. Further, the reference voltage of the reference voltage generating circuit 11 passes through the comparator 10 and the LPF 4, and
Since it is supplied to No. 5, it is almost the reference voltage and not the reference voltage itself, so that there is a problem that an accurate VCO control voltage is not always supplied when there is no signal.

[0013]

SUMMARY OF THE INVENTION The present invention provides a PLL circuit that can shorten the lock-up time of the PLL circuit to improve the response and can supply the VCO control voltage accurately.

[0014]

In order to solve the above-mentioned problems, a PLL circuit of the present invention comprises a phase comparison circuit, a loop filter and a voltage controlled oscillator, and selects a synchronous clock from input signals having a synchronous clock signal pattern. In a PLL circuit for extracting a signal, an input signal presence / absence detection circuit connected to the output side of a sync separation circuit, a switch controlled by the output of this input / output signal presence / absence detection circuit, and a fixed control voltage selector connected to this switch Is provided, and when there is no input signal, the switch is switched from the loop filter side to the fixed control voltage selector side to supply the control voltage of the voltage controlled oscillator to the voltage controlled oscillator.

[0015]

FIG. 2 shows a block diagram of a digital mixer in which a PLL circuit of the present invention is adopted. In this digital mixer, the PLL circuit of the present invention is used for the reception demodulation PLL of the demodulator 14. The demodulator 14 is AES / EB
The U-format digital audio signal is demodulated and converted into a format suitable for device internal signal processing, and is supplied to the equalizer / mixing block 15. Modulator 1
6 modulates the processing result of the equalizer / mixing block 15 into an AES / EBU digital audio signal,
Send it out of the device.

The timing generator 17 generates an operation clock signal inside the device and supplies it to the equalizer / mixing block 15, modulator 16 and demodulator 14. At present, 32 KHz, 44.1 KHz, and 48 KHz are selected as the sampling frequency of the digital audio signal, and the sampling frequency selection switch 18 selects which of the sampling frequencies is used for the signal processing cycle inside the device. The selected sampling frequency is sent to the timing generator 17, and the timing generator 17 generates a clock signal according to this. Also, the AES / EBU having the same sampling frequency as the sampling frequency selected by the switch 18 is used.
Since the digital audio signal is input to the demodulator 14, it is smoothly processed as a digital mixer without excess or deficiency of audio information.

The PLL circuit shown in FIG. 1 shows a preferred embodiment which solves the above problems and is adopted in the digital mixer. The PLL circuit of the present invention comprises an input signal presence / absence detection circuit 1
9, the fixed control voltage selector switch 21 and the fixed control voltage selector 20 are provided. In FIG. 1, first, the sync separation circuit 1 extracts the sync signal pattern of the AES / EBU digital audio signal and supplies it as a reference signal (2f _S ) to the phase comparison circuit 3 of the PLL circuit 2 and the input signal presence / absence detection circuit 19. To do. The input signal presence / absence detection circuit 19 has a counter inside and detects the presence / absence of input data by measuring the interval between the reference signals supplied from the sync separation circuit 1. When a certain interval or more is counted, it is determined that there is no input signal, and the input signal detection signal that is the result of this determination becomes the switching signal for the switch 21.

The phase comparison circuit 3 receives the reference signal supplied from the sync separation circuit 1 and the signal supplied from the frequency divider 6, and outputs the phase difference detection signal to a loop filter (LP).
F) Supply to 4. The loop filter 4 removes the high frequency component of the phase difference detection signal supplied from the phase comparison circuit 3, and supplies it to the VCO 5 through the switch 21 as the oscillation frequency control voltage of the VCO 5. Further, the VCO 5 is controlled by the frequency control voltage supplied from the loop filter 4 through the switch 21 to oscillate, and supplies its output signal to the frequency divider 6 and also to the circuit in the subsequent stage. VCO
The signal obtained by dividing the oscillation frequency of 5 by the frequency divider 6 is supplied to the phase comparison circuit 3 to form a loop. Further, the switch 21 is located between the loop filter 4 and the VCO 5, and switches the control voltage of the VCO 5 between the signal from the loop filter 4 and the signal from the fixed control voltage selector 20.

If the input signal presence / absence detection circuit 19 determines that there is an input signal, the control voltage from the loop filter 4 is selected and supplied to the VCO 5, and the conventional PL is used.
Operates the same as the L circuit. On the other hand, when the input signal presence / absence detection circuit 19 determines that there is no input signal, the control voltage from the fixed control voltage selector 20 is selected, and the VCO 5 oscillates at the frequency set by the fixed control voltage selector 20. The fixed control voltage selector 20 outputs the VES signal corresponding to the expected AES / EBU digital audio signal.
It is configured as a selector capable of changing the oscillation frequency of CO, and is set in the fixed control voltage selector 20 corresponding to the sampling frequency changeover switch of the digital audio mixer.

The PLL circuit of the present invention and the proposed FIG.
In comparison with the conventional PLL circuit shown in FIG. 3, when the input signal presence / absence detection circuit 17 determines that there is no input signal, the PLL circuit of the present invention has the switch 21 independent of the fixed control voltage selector 20 side. Since the control voltage is supplied to the VCO 5 and the oscillation frequency is set, the fixed control voltage selector 20 changes the loop consisting of the VCO 5, the frequency divider 6, the phase comparison circuit 3, the loop filter 4, and the switch 21. Separated, the oscillation frequency of the VCO 5 can be set independently and an accurate VCO control voltage can be supplied. Furthermore, as in the conventional example, the comparator 1
Since 0 is not required, there is no cost.

The present invention also provides a fixed control voltage selector 20.
While the switching control voltage is directly supplied from the VCO 5 to the VCO 5, the proposed conventional PLL circuit uses the transfer function of the loop filter 4 at the output of the comparator 10 when it detects that there is no input signal. Is controlled and the control voltage is supplied to the VCO 5 through the loop filter 4, the response of the operation switching of the VCO 5 to the determination of the presence or absence of the input signal is delayed by that much, while the PLL circuit of the present invention is a PLL circuit excellent in immediate response. Can be configured.

[0022]

The PLL circuit of the present invention has a VC at the desired frequency when the expected reference signal is input.
Since O oscillates, the lock-up time becomes extremely short. Further, when the PLL circuit of the present invention is adopted in a digital mixer, (1) a digital switcher is arranged in the front stage of the digital mixer for the purpose of expanding or switching the number of input channels of the digital mixer. If there is no input to the demodulator 14, the demodulator 1 may be suddenly input, or at the moment when the input connector is connected to the digital mixer alone.
In the state where there is no input of 4, the state is such that a sudden input is made. Even in such a state, the PLL of the demodulator 14 is immediately locked up, so that the sound is immediately input, that is, the response is improved.

(2) In order to improve the operability of the digital mixer and digital switcher, the snap automation function is adopted in these devices. This is equalizer, level adjustment, switcher connection information, etc.
It is a function that instantly stores or reproduces device setting information. A sharp response is required for this reproduction operation, but this function causes a case where the demodulator 14 is suddenly input in the absence of input, and conventionally a long lockup time has been a problem. However, even in such a case, the PLL of the demodulator 14 is immediately locked up, so that the sound is immediately input, that is, the response is improved.

(3) It is required to shorten the lock-up time of the PLL circuit of the reception demodulator even when the function of the AES / EBU digital audio interface section is checked by a digital mixer or digital switcher having multi-channel input / output. It That is, A for test
By distinguishing whether the ES / EBU digital audio signal is supplied to each input channel or not, the operating condition is checked to check the function. In this function check, there are many cases in which the demodulator 14 is suddenly input in the absence of input. Therefore, when this function check is performed by the CPU program, after setting the presence or absence of the test signal supply to the input channel under test, wait for the lockup of the PLL circuit for reception demodulation, and then check the operation status to check the function. It becomes the form to do.
In digital audio mixers and switchers with multi-channel input / output, the waiting time assuming the lockup time at the time of this function check becomes longer in proportion to the number of input / output channels. Since the 14 PLL circuits are locked up, the waiting time assuming the lock-up time, which has been required in the past, becomes unnecessary, and the function check time is greatly shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit of the present invention.

FIG. 2 is a partial block configuration diagram of a digital mixer using the PLL circuit of the present invention.

FIG. 3 is a block diagram of a conventional PLL circuit.

FIG. 4 is a block diagram of another conventional PLL circuit.

[Explanation of symbols]

1. ・ Synchronous separation circuit 2 ・ ・ PLL circuit 3 ・ ・ Phase comparison circuit 4 ・ ・ LPF 5 ・ ・ VCO 6 ・ ・ Frequency divider 19 ・ ・ Input signal presence / absence detection circuit 20 ・ ・ Fixed control voltage selector 21 ・ ・ Switch

Claims (1)

[Claims] 1. A PLL circuit for extracting a synchronous clock signal from an input signal having a synchronous clock signal pattern, comprising a phase comparison circuit, a loop filter, and a voltage controlled oscillator, and an input signal connected to an output side of a synchronous separation circuit. A presence / absence detection circuit, a switch controlled by the output of this input / output signal presence / absence detection circuit, and a fixed control voltage selector connected to this switch are provided, and the switch is fixed from the loop filter side when the input signal is absent. A PLL characterized by switching to the control voltage selector side to supply the control voltage of the voltage controlled oscillator to the voltage controlled oscillator.
circuit.