JP2679621B2 - Clock extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extraction circuit using a digital PLL circuit.

[0002]

2. Description of the Related Art This type of clock extraction circuit has a digital PLL circuit 1 for receiving an input digital signal and generating an extraction clock signal, as shown in FIG. What is provided to the waveform shaping circuit 2 is known.

Generally, in this type of clock extraction circuit,
The sync pull-in time and the sync hold capacity are determined by the Q value of the digital PLL circuit 1. When the Q value is low, the sync pull time is short, and when the Q value is high, the sync hold capacity is improved. Therefore, the sync pull-in time is short,
In order to realize a clock extraction circuit using the digital PLL circuit 1 having a high synchronization holding ability, it is necessary to control the Q value of the digital PLL circuit 1.

Conventionally, as a clock extraction circuit based on such an operation principle, as described in, for example, Japanese Patent Laid-Open No. 62-47233, the quality of the signal-to-noise ratio of the received input digital signal is judged, When the signal-to-noise ratio is good, the Q value of the digital PLL circuit is increased to improve the synchronization holding ability, and when the signal-to-noise ratio is bad, the digital PL circuit is
It is known that the Q value of the L circuit is lowered to shorten the synchronization pull-in time.

[0005]

SUMMARY OF THE INVENTION Conventional digital PLL
In the clock extraction circuit that does not control the Q value of the circuit, if the Q value is high, the time required for the synchronization pull-in becomes long, and if the Q value is low, the out-of-synchronization is likely to occur, and quick and stable clock extraction can be obtained. There is a problem that there is no.

Further, when the clock extraction circuit disclosed in Japanese Patent Laid-Open No. 62-47233 is applied to a system for intermittently transmitting information such as the TDMA system, the synchronization pull-in time is set immediately after the reception of information is started. Is expected to be long. Immediately after starting to receive information,
The signal-to-noise ratio is generally in a good state, and the clock extraction circuit has a problem that the Q value of the digital PLL circuit becomes high and the synchronization pull-in time becomes long.

An object of the present invention is to provide a clock extraction circuit capable of extracting a clock signal quickly and stably even in a system in which information is transmitted intermittently.

[0008]

According to the present invention, in order to solve the above problems, a clock extraction circuit having a digital PLL circuit receives an input digital signal, detects a specific synchronization pattern, and outputs a pattern detection signal. And a digital pattern which is connected to the synchronous pattern detection circuit and receives the pattern detection signal.
And a Q value control circuit for switching the Q value of the L circuit from a low value to a high value.

Further, according to the present invention, in a clock extraction circuit having a digital PLL circuit, a sync pattern detection circuit which receives an input digital signal, detects a specific sync pattern, and outputs a pattern detection signal, and this sync pattern detection circuit And a digital PLL circuit for controlling the Q value of the digital PLL circuit, and a timer connected to the synchronous pattern detection circuit for turning on the output signal for a fixed time after receiving the pattern detection signal. A circuit, a transmission information judging circuit which receives the input digital signal and judges the presence or absence of transmission information, and outputs a transmission information present signal when there is transmission information, the transmission information judging circuit, a timer circuit and a Q value control circuit And the transmission information present signal is received while the output signal of the timer circuit is ON and the transmission information present signal is received. A first reset signal is generated when the signal disappears and is given to the Q value control circuit, and a second reset signal is generated when the transmission information present signal is not received while the output signal of the timer circuit is ON. And a reset signal generation circuit for giving the Q value control circuit to the Q value control circuit, wherein the Q value control circuit switches the Q value of the digital PLL circuit from a low value to a high value when receiving the pattern detection signal, and The Q value of the digital PLL circuit is switched from a high value to a low value when receiving the first reset signal or the second reset signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The clock extraction circuit of the present invention is a digital P
In a clock extraction circuit having an LL circuit 1, a sync pattern detection circuit 3 for receiving an input digital signal, a Q value control circuit 4 connected to the sync pattern detection circuit 3 and the digital PLL circuit 1, and the sync pattern detection circuit. Three
A timer circuit 5 connected to the transmission information determination circuit 6, a transmission information determination circuit 6 for receiving the input digital signal, and a transmission information determination circuit 6
And a reset signal generating circuit 7 connected to the timer circuit 5 and the Q value control circuit 4.

The sync pattern detection circuit 3 receives the input digital signal, detects a specific sync pattern, and outputs a pattern detection signal. The Q value control circuit 4 controls the Q value of the digital PLL circuit 1. The timer circuit 5 is connected to the synchronization pattern detection circuit 3 and the output signal is turned on for a fixed time after receiving the pattern detection signal. The transmission information determination circuit 6 receives the input digital signal, determines the presence or absence of transmission information, and outputs a transmission information present signal when there is transmission information.

The reset signal generating circuit 7 is connected to the transmission information judging circuit 6, the timer circuit 5 and the Q value control circuit 4, and is transmitted from the transmission information judging circuit 6 while the output signal of the timer circuit 5 is ON. When the transmission information present signal disappears after receiving the transmission information present signal, a first reset signal is generated and given to the Q value control circuit 4, and while the output signal of the timer circuit 5 is ON. Transmission information determination circuit 6
The second reset signal is generated when the signal having the transmission information is not received from and is given to the Q value control circuit 4.

The Q value control circuit 4 switches the Q value of the digital PLL circuit 4 from a low value to a high value when it receives a pattern detection signal from the synchronous pattern detection circuit 3, and
When the first reset signal or the second reset signal is received from the reset signal generation circuit 7, the Q value of the digital PLL circuit 1 is switched from a high value to a low value.

Therefore, the digital PLL circuit 1 is
Until the synchronization pattern is detected, the Q value is set low and the synchronization pull-in time is shortened. Therefore, in this state, the digital input digital signal is quickly pulled in and the clock is extracted quickly. Further, in the digital PLL circuit 1, since the Q value is set to be high after the synchronization pattern is detected, the synchronization holding ability is enhanced with respect to the extracted clock extraction, and the synchronization state is stably held. Become. Further, when noise or the like is erroneously detected as a synchronization pattern, the Q value control circuit 4 receives a signal from the timer circuit 5 after a certain period of time, and the Q value control circuit 4 receives the digital PLL signal.
The Q value of the circuit 1 is set low.

Next, the operation of the clock extraction circuit of the present invention will be described with reference to the timing charts of FIGS.

FIG. 2 is a timing chart of one embodiment of the present invention, which shows the operation timing of each part of the circuit when the transmission information is received.

When the input digital signal is as shown in FIG. 2, the sync pattern detection circuit 3 receives the input digital signal, detects a specific sync pattern, and outputs a pattern detection signal. The Q value of the digital PLL circuit 1 that receives this pattern detection signal is switched from the low value to the high value by the Q value control circuit 4. Reset signal generation circuit 7
Is a Q-value control circuit for generating a first reset signal when the transmission information present signal disappears after receiving the transmission information present signal from the transmission information determination circuit 6 while the output signal of the timer circuit 5 is ON. 4, the Q value control circuit 4 switches the Q value of the digital PLL circuit 1 from a high value to a low value.

FIG. 3 is a timing chart of one embodiment of the present invention, which shows the operation timing of each part of the circuit when the transmission information is not received.

When the input digital signal is as shown in FIG. 3, the sync pattern detection circuit 3 receives the input digital signal, detects a specific sync pattern, and outputs a pattern detection signal. The Q value of the digital PLL circuit 1 that receives this pattern detection signal is switched from the low value to the high value by the Q value control circuit 4. Reset signal generation circuit 7
Generates a second reset signal when the transmission information presence signal is not received from the transmission information determination circuit 6 (that is, when noise is received) while the output signal of the timer circuit 5 is ON, and the Q value control is performed. Since it is given to the circuit 4, the Q value control circuit 4 switches the Q value of the digital PLL circuit 1 from a high value to a low value.

[0022]

The clock extraction circuit of the present invention shortens the sync pull-in time by lowering the Q value of the digital PLL circuit until the sync pattern is detected, and raises the Q value when the sync pattern is detected. To improve the synchronization holding ability, and when there is no transmission information after a lapse of a fixed time after detecting the synchronization pattern, the Q value of the digital PLL circuit is switched from a high value to a low value, so that a quick and stable clock is obtained. Extraction can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a timing chart shown for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional clock extraction circuit.

[Explanation of symbols]

 1 Digital PLL circuit 2 Waveform shaping circuit 3 Synchronization pattern detection circuit 4 Q value control circuit 5 Timer circuit 6 Transmission information judgment circuit 7 Reset signal generation circuit

Claims (1)

(57) [Claims] 1. A clock extraction circuit having a digital PLL circuit, which receives an input digital signal, detects a specific synchronization pattern, and outputs a pattern detection signal, and this synchronization pattern detection circuit and digital PLL circuit. Q of the digital PLL circuit connected to
A Q value control circuit for controlling a value, a timer circuit which is connected to the synchronous pattern detection circuit and turns on an output signal for a fixed time after receiving the pattern detection signal, and the presence or absence of transmission information by receiving the input digital signal And a transmission information determination circuit that outputs a transmission information presence signal when there is transmission information, and the output signal of the timer circuit connected to the transmission information determination circuit, the timer circuit, and the Q value control circuit is ON. While receiving the transmission information present signal in the meantime, when the transmission information present signal disappears, a first reset signal is generated and given to the Q value control circuit, and while the output signal of the timer circuit is ON. And a reset signal generating circuit for generating a second reset signal when not receiving the transmission information present signal and supplying the second reset signal to the Q value control circuit. The digital P when receiving a signal
The Q value of the LL circuit is switched from a low value to a high value, and the Q value of the digital PLL circuit is switched from a high value to a low value when receiving the first reset signal or the second reset signal. Clock extraction circuit.