JP3039497B2 - Clock extraction circuit, communication system, and transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extraction circuit, and more particularly to a clock extraction circuit having a digital PLL circuit configuration for extracting a clock signal synchronized with an input digital signal from an input digital signal, and a communication system using the clock extraction circuit. About.

[0002]

2. Description of the Related Art In a communication system for transmitting a digital signal from a transmitting side to a receiving side, a clock is extracted from a transmitted signal on the receiving side, and digital data processing and the like are performed based on the extracted clock. Digital PLL as a clock extraction circuit for extracting a clock
Devices using (phase locked loop) circuits are widely known.

Japanese Patent Application Laid-Open No. 8-84137 discloses a clock extraction circuit suitable for such transmission data when burst data composed of a synchronization pattern portion and an information bit portion is transmission data. ing. As shown in FIG. 4, the clock extracting circuit includes a digital PLL circuit 81 which receives input data and a reference clock of a receiving device and outputs a reproduced clock, decodes input data based on the reproduced clock, and outputs output data. Output decoder 82
And a data detection circuit 8 for detecting the head of burst data
3 and the output of the data detection circuit 83, the setting value of the programmable divider of the digital PLL circuit 81 is reduced during the input of the bit synchronization pattern section, and the digital bit is input in the information bit section input following the bit synchronization pattern section.
A programmable divider control circuit 84 for increasing the set value of the programmable divider of the LL circuit 81 is provided. With such a configuration, a clock extraction circuit is realized in which synchronization is quickly pulled in at the head of the burst data and synchronization is hardly lost in the subsequent information bit portion.

Further, Japanese Patent Application Laid-Open No. 7-3077 by the present inventors
Japanese Patent Publication No. 29 discloses a clock extraction circuit that can reduce the synchronization pull-in time and improve the synchronization holding capability, assuming that a specific synchronization pattern is included in an input digital signal. FIG. 5 shows the configuration of this clock extraction circuit. This clock extraction circuit includes a digital PLL circuit 91 which receives an input digital signal and outputs an extracted clock signal, and a waveform shaping circuit 92 which shapes the waveform of the input digital signal based on the extracted clock signal and outputs it as an output digital signal. Pattern detection circuit 93 which receives an input digital signal, detects a specific synchronization pattern, and outputs a pattern detection signal (synchronization information).
And a digital PLL circuit 91 according to the pattern detection signal.
And a Q-value control circuit 94 for changing the Q-value of the input digital signal, receiving the input digital signal, determining the presence or absence of the transmission information in the input digital signal, and outputting the transmission information-present signal when the transmission information exists. The control circuit includes a determination circuit 95, a timer circuit 96 that operates according to the pattern detection signal, and a reset signal generation circuit 97 that generates a reset signal for resetting the Q value control circuit 94. When a specific synchronization pattern is detected in the input digital signal and a pattern detection signal is output, the Q-value control circuit 94
The Q value of the L circuit 91 is switched from a low value to a high value. The reset signal generation circuit 97 receives the transmission information presence signal from the transmission information determination circuit 95 while the output signal of the timer circuit 96 is on (ON), and outputs the first reset signal when the transmission information presence signal disappears. Is generated and given to the Q value control circuit 94, so that when such a condition is satisfied, the Q value control circuit 94 switches the Q value of the digital PLL circuit 91 from a high value to a low value. In this manner, the Q value of the digital PLL circuit 91 is reduced to reduce the synchronization pull-in time until the synchronization pattern is detected, and the Q value is increased when the synchronization pattern is detected to increase the synchronization holding capability. Have improved.

[0005]

All of the above-mentioned conventional clock extraction circuits control the digital PLL circuit to reduce the synchronization pull-in time and improve the synchronization holding capability. A fixed-length synchronization pattern is given to a signal to be performed, and control is performed based on the fixed-length synchronization pattern. When the signal-to-noise ratio (S / N) of the communication line is low, the digital signal input to the clock extraction circuit contains much jitter, so that a long synchronization pattern is required. Conversely, when the signal-to-noise ratio of the communication line is high, the jitter of the input digital signal is small, so that the clock can be extracted with a relatively short synchronization pattern. In a conventional clock circuit, it is necessary to consider the case where there is a lot of jitter to ensure synchronization pull-in, so use a long-length synchronization pattern because a fixed-length synchronization pattern is used. It was common to do. For this reason, the ratio of the synchronization pattern in the signal transmitted from the transmission side to the reception side increases, which causes a problem that the amount of transmittable information decreases. In a communication system in which information is intermittently transmitted, that is, a communication system in which burst data is transmitted,
This problem becomes more prominent because the synchronization pattern is used frequently.

SUMMARY OF THE INVENTION It is an object of the present invention to increase transmittable information by using a minimum necessary synchronization pattern even when used in a communication system in which information is transmitted intermittently. It is another object of the present invention to provide a clock extracting circuit capable of extracting a clock signal quickly and stably, and to provide a communication system using the clock extracting circuit and a transmitting device used in the communication system.

[0007]

A clock extracting circuit according to the present invention includes a receiving circuit for receiving a transmission signal transmitted from a transmitting side, converting the signal, and outputting the converted signal as a digital signal, and a clock synchronized with the digital signal from the digital signal. In a clock extraction circuit having a digital PLL circuit for extracting a signal, a reception circuit outputs a reception level signal corresponding to a reception level of a transmission signal, and Q value control means for controlling a Q value of the digital PLL circuit; The signal-to-noise ratio of the transmission signal is calculated based on the signal, and Q
A signal-to-noise ratio measurement unit that controls the value control unit and sends a signal based on the calculation result to the transmission side.

[0008] A communication system according to the present invention includes a transmitting device that receives transmission information, converts the transmission information into a transmission signal, and sends the transmission signal, and a receiving device that receives the transmission signal and extracts the transmission information as output data. A transmitting circuit for converting a transmission information into a transmission signal by adding a synchronization pattern, which is a pattern for establishing synchronization at a bit level, to the transmission information prior to the transmission information, and transmitting the transmission information. And a synchronization pattern setting circuit for setting a synchronization pattern, wherein the receiving device receives and converts the transmission signal and outputs it as a digital signal, and outputs a reception level signal according to the reception level of the transmission signal. A receiving circuit, a digital PLL circuit for extracting a clock signal synchronized with the digital signal from the digital signal, and a digital PLL
Q value control means for controlling the Q value of the circuit, a signal-to-noise ratio in the transmission signal is calculated based on the reception level signal, and the Q value control means is controlled based on the calculation result. Signal-to-noise ratio measuring means for transmitting to the synchronization pattern setting circuit.

In the communication system of the present invention, the synchronization pattern setting circuit sets the synchronization pattern relatively short when the signal-to-noise ratio is relatively large, and sets the synchronization pattern relatively small when the signal-to-noise ratio is relatively small. It is preferable that the synchronization pattern is set relatively long.

A transmitting apparatus according to the present invention converts a transmission information into a transmission signal by inputting the transmission information and transmits the transmission signal to a receiving side. The transmitting apparatus uses a synchronization pattern which is a pattern for establishing synchronization at a bit level. A transmission circuit that converts the transmission information into a transmission signal by adding it to the transmission information prior to the transmission information and sends the transmission signal; and a synchronization pattern setting circuit that sets a synchronization pattern. The information on the ratio is received from the receiving side, and when the signal-to-noise ratio is relatively large, the synchronization pattern setting circuit sets the synchronization pattern relatively short, and when the signal-to-noise ratio is relatively small, A synchronization pattern setting circuit sets the synchronization pattern relatively long.

In the present invention, a transmission signal is typically a high-frequency signal modulated based on transmission information.
Further, it is preferable that the reception level signal is input to the digital PLL circuit so that the operation of the clock extraction processing in the digital PLL circuit is stopped when the reception level is equal to or lower than a predetermined threshold value.

<< Operation >> In the clock extraction circuit according to the present invention, the operation of the digital PLL circuit and the pattern length for synchronization are controlled by using the signal-to-noise ratio in a wireless or other receiving circuit. That is, in the initial state (state in which no information is received), the noise level is measured and the digital P
The Q value of the LL circuit is set low to shorten the synchronization pull-in time after receiving the information. When a certain period of time has passed since the information was received (when the signal-to-noise ratio increased) and the synchronization of the digital PLL circuit was completed, the Q value of the digital PLL circuit was increased to improve the synchronization holding capability. When receiving condition is bad during receiving information (when signal-to-noise ratio is low)
In this method, since the received digital signal contains much jitter and the like, control is performed on the transmitting side to lengthen the synchronization pattern and ensure synchronization. When the reception state is good (when the signal-to-noise ratio is high), since the jitter of the received digital signal is small, the synchronization pattern is shortened so that the synchronization is quickly performed. As a result, the length of the synchronization pattern can be reduced, and a larger amount of information can be transmitted.

In the communication system according to the present invention, there are provided a receiving device having the above-described clock extracting circuit, and a pattern length setting circuit for changing the pattern length of the synchronization pattern in accordance with the signal-to-noise ratio on the receiving side. Transmission device having a synchronization pattern of a length adapted to the signal-to-noise ratio on the receiving side is transmitted from the transmitting side to the receiving side, such as when transmitting burst data,
More information can be transmitted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a communication system according to an embodiment of the present invention.

This communication system has a configuration in which a transmitting device 1 and a receiving device 2 are connected by a line 3, and information is transmitted by a high frequency signal on the line 3. Here, it is assumed that information is transmitted by burst data,
It is assumed that a synchronization pattern is added to the head of each burst data. The line 3 is typically a wireless line. The transmission device 1 receives a transmission information signal, performs modulation processing and frequency conversion processing on the transmission information signal, converts the transmission information signal into a high-frequency signal, and transmits the high-frequency signal to the line 3. A synchronization pattern setting circuit 12 for setting a pattern length. When a wireless line is used as the line 3, the transmission circuit 11 also has a function as a wireless transmitter. In the transmission circuit 11, the synchronization pattern having the pattern length set by the synchronization pattern setting circuit 12 is added to the transmission information signal so as to precede the data entity of the transmission information signal.

On the other hand, the receiving device 2 receives a high-frequency signal transmitted via the line 3 and performs a frequency conversion process and a demodulation process to output a digital signal, and at the same time, a reception level signal proportional to the strength of the high-frequency signal. A digital PLL circuit 22 that extracts a clock from a digital signal output by the receiving circuit 21 and outputs it as an extracted clock signal and outputs a synchronization signal indicating whether synchronization has been established; A waveform shaping circuit 23 for shaping the waveform of a digital signal based on the signal and outputting the digital signal as an output digital signal; a signal-to-noise ratio measuring circuit 24 for calculating a signal-to-noise ratio in a high-frequency signal with a reception level signal as an input; A Q value control circuit 25 for controlling the Q value of the PLL circuit 21 is provided. If the line 3 is a wireless line, the receiving circuit 21 also has a function as a wireless receiver. As will be described later, the signal-to-noise ratio calculated by the signal-to-noise ratio measurement circuit 24 is supplied to a Q-value control circuit 25, and the synchronization pattern setting circuit 1
2 is used to control the pattern length of the synchronization pattern. The Q value control circuit 25 is a Q value control unit,
Signal-to-noise ratio measurement circuit 24 serving as signal-to-noise ratio measurement means
Digital PLL circuit 2 in the initial state by the control from
2 is set low, and after the synchronization signal is output from the digital PLL circuit 22, the Q value is set high.

Next, the operation of the communication system will be described.

In the receiving apparatus 2, the digital signal output from the receiving circuit 21 is input to a digital PLL circuit 22 to extract a clock component, and the digital signal is shaped by a waveform shaping circuit 23 based on the extracted clock signal. It is shaped and output as an output digital signal. Further, in this communication system, the following operation is executed in order to efficiently control the Q value of the digital PLL circuit 22 and perform the synchronization pull-in process of the digital PLL circuit 22 in response to the transmission of the burst data.

That is, before receiving the high-frequency signal from the transmitting device 1, the signal-to-noise ratio determination circuit 24 measures the noise level based on the reception level signal from the reception circuit 21, And the Q value of the digital PLL circuit 22 is set low. This makes it possible to shorten the synchronization pull-in time when the reception of information is started. In addition, the reception level signal is also supplied to the digital PLL circuit 22, so that when the reception level is low and no high-frequency signal is received, the operation of the digital PLL circuit 22 is stopped,
Malfunction due to spatial noise is prevented. Specifically, when the reception level is equal to or lower than a predetermined threshold, the digital PL
The operation of the L circuit, at least the operation of the clock extraction processing, is stopped.

When the reception level signal from the reception circuit 21 rises, it is determined that information has been received, and the digital PLL circuit 22 starts clock extraction processing. At this time,
Since the Q value control signal output from the Q value control circuit 25 remains at a low value and the Q value of the digital PLL circuit 21 remains set at a low value, synchronization can be quickly performed. After a certain time, the digital PLL
When the synchronization of the circuit 22 is completed, the digital PL
The synchronization signal is output from the L circuit 22 to the Q value control circuit 25. The Q value control circuit 25 to which the synchronization signal has been input increases the Q value of the digital PLL circuit 22 by setting the Q value control signal to a high value, and improves the synchronization holding ability.

Further, in this communication system, the receiving device 2
In the case where the signal-to-noise ratio measured by the signal-to-noise ratio measurement circuit 24 during reception of the information is low, the reception state is poor and the digital signal contains a lot of jitter. Then, synchronization can be reliably performed. At this time, the signal-to-noise ratio measurement circuit 24
From the transmission device 1 to control the synchronization pattern setting circuit 12 to increase the pattern length of the synchronization pattern in the high-frequency signal transmitted from the transmission device 1 onward.

On the other hand, when the signal-to-noise ratio measured by the signal-to-noise ratio measuring circuit 24 during the reception of information is high, the reception state is good and the jitter contained in the digital signal is small, and Since the synchronization can be established, it is possible to shorten the synchronization pattern and quickly perform the synchronization pull-in. At this time, the signal-to-noise ratio measurement circuit 24 controls the synchronization pattern setting circuit 12 of the transmission device 1 to shorten the synchronization pattern of the high-frequency signal transmitted from the transmission device 1 onward.

With the above processing, it is possible to minimize the synchronization pattern length when transmitting burst data, and it is possible to perform efficient information transmission.

FIG. 2 is a timing chart for explaining the operation of the communication system shown in FIG. 1, showing states before and after the receiving device 2 starts to receive a high frequency signal of burst data. (a) shows a high-frequency signal received by the receiving device 2.

At first, a high-frequency signal is not transmitted from the transmitting device 1 side, and the signal received by the receiving device 2 is only spatial noise. Receiving the transmission pattern following the synchronization pattern. For such a high-frequency signal, the reception level signal output from the reception circuit 21 is as shown in FIG. That is, before a high-frequency signal from the transmission side is input to the receiving device 2, spatial noise is output to the digital signal output from the receiving circuit 21, and the reception level signal is held at a low value. Thereafter, when the high-frequency signal is received, the synchronization pattern and the transmission information are sequentially output to the digital signal. Also, the reception level signal has a high value, which causes the digital P
The clock extraction process in the LL circuit 22 is started. At this point, the Q value of the digital PLL circuit 22 has been set to a low value, and quick clock extraction (lock-in) is performed. Digital PLL circuit 2 during input of synchronization pattern
2, after a certain period of time, as shown in (c), the synchronization of the digital PLL circuit 22 is completed, and the digital PLL circuit 22 sends (d) A synchronization signal is output as shown in FIG. Upon receiving the synchronization signal, the Q value control circuit 5 sets the Q value of the digital PLL circuit 22 high as shown in (e). As a result, stable synchronization is maintained. With the above processing, it is possible to perform stable clock extraction that is not easily affected by the jitter of the input digital signal and the bias of the pattern.

Here, the digital PLL circuit 22 will be described. For the Q value control of the digital PLL circuit,
For example, a known technique can be used as disclosed in Japanese Patent Application Laid-Open No. 3-97318. FIG. 3 shows a digital PLL circuit that can be used as the digital PLL circuit 22 and that can control the Q value. FIG. 3 is a block diagram showing an example of the configuration of FIG. This digital PLL circuit generally has one
A circuit commercially available as a general-purpose IC (integrated circuit) for a chip can be used. For example, "CD74EC297
"B" (manufactured by Harris: HARRIS), the Q value of which can be set from outside the IC. Although a mechanism for controlling the operation of the digital PLL circuit according to the reception level signal is not shown in FIG. 3, for example, when the reception level represented by the reception level signal is equal to or less than a predetermined threshold value, , A circuit for stopping the supply of power to the entire PLL circuit or the frequency dividing circuit may be provided.

This digital PLL circuit has a reference clock oscillation circuit 31 for generating a clock used therein.
A phase comparison circuit 32 that compares the phase of an input digital signal (a digital signal output by the receiving circuit 21 in FIG. 1) with the phase of the extracted clock to determine the difference and outputs the difference as a phase error signal; An up / down (U / D) counter 33 that outputs a control signal each time the count value exceeds or falls below a predetermined range, using a clock from the up / down counter, and is controlled by a control signal from the up / down counter 33. And a frequency dividing circuit 34 for dividing the frequency of the clock from the reference clock oscillation circuit 31. The output of the frequency dividing circuit 34 is an extracted clock. The extracted clock is supplied to the outside of the digital PLL circuit and is input to the phase comparing circuit 32 as described above.

The switching between the up-counting and the down-counting in the up-down counter 33 is performed according to a phase error signal ("up-down control" in the figure) from the phase comparison circuit 32. The up / down counter 33 has:
A Q value control signal is input from the Q value control circuit 25 (FIG. 1),
The above-described predetermined range changes depending on whether the Q-value control signal is low or high.

The frequency divider 34 divides the clock from the reference clock generator 24 to generate an extracted clock having the same frequency as the input digital signal. During this frequency division operation, the phase of the extracted clock to be output is changed by the control signal input from the up / down counter 33, and more specifically, the number of pulses of the extracted clock is ± 1 according to the control signal. Has become.

By adopting the above configuration,
When the Q value control signal input to the digital PLL circuit has a low value, a predetermined range in the up / down counter 33 is reduced, and a control signal to the frequency dividing circuit 34 is frequently generated.
The phase change of the extracted clock is likely to occur. This facilitates synchronization of the digital PLL circuit 1. When the Q-value control signal is high, the predetermined range in the up / down counter 33 is increased, and the generation of the control signal is suppressed. As a result, the phase change of the extracted clock is less likely to occur. The ability to maintain synchronization is improved.

Further, in this digital PLL circuit, an extracted clock is input to a D input terminal and an input digital signal is input to a clock (C) terminal in order to generate a synchronization signal by performing synchronization detection (judgment of synchronization pull-in). And a pulse generating circuit 36 that generates a pulse by using the Q output of the D-type flip-flop 35 as an input, and the output of the pulse generating circuit 36 is output to the outside of the digital PLL circuit as a synchronization signal. Is done.

At the point in time when the pull-in of the digital PLL circuit is completed, the input digital signal and the extracted clock are signals having the same frequency and shifted in phase. Therefore, the Q terminal which is the output of the D-type flip-flop 35 is at L (low).
Level or H (high) level. The pulse generation circuit 36 is a circuit that detects an edge of the input signal (output of the D-type flip-flop 35) and outputs a pulse for a predetermined time. The pulse generation circuit 28
If the input is fixed at the L level or the H level, no pulse is output (L level fixed), so this state is set to a synchronous state.

On the other hand, at the point in time when the pull-in of the digital PLL circuit is not completed, the phase of the input digital signal and the phase of the extracted clock are changed.
Changes between L level and H level. Therefore, the output of the pulse generation circuit 36 becomes H level,
This state is referred to as an asynchronous state. As described above, the synchronization of the digital PLL circuit is detected by the D-type flip-flop 35 and the pulse generation circuit 36 and output as a synchronization signal.

[0034]

As described above, according to the present invention, the minimum necessary synchronization pattern length can be set in the transmitting apparatus based on the receiving condition (signal-to-noise ratio) in the receiving apparatus, thereby achieving the synchronization. There is an effect that the pattern can be minimized, the capacity for transmission information can be increased, and the clock signal can be quickly and stably extracted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication system according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of the operation of the communication system of FIG.

FIG. 3 is a block diagram illustrating an example of a configuration of a digital PLL circuit.

FIG. 4 is a block diagram illustrating an example of a conventional clock extraction circuit.

FIG. 5 is a block diagram showing another example of a conventional clock extraction circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission device 2 reception device 3 line 11 transmission circuit 12 synchronization pattern setting circuit 21 reception circuit 22 digital PLL circuit 23 waveform shaping circuit 24 signal-to-noise ratio measurement circuit 25 Q value control circuit 31 reference clock oscillation circuit 32 phase comparison circuit 33 Up / down (U / D) counter 34 Frequency divider 35 D-type flip-flop 36 Pulse generator

Claims (8)

(57) [Claims] 1. A receiving circuit for receiving and converting a transmission signal transmitted from a transmission side and outputting the converted signal as a digital signal;
A digital PLL circuit for extracting a clock signal synchronized with the digital signal from the digital signal, wherein the receiving circuit outputs a reception level signal corresponding to a reception level of the transmission signal; Q-value control means for controlling the Q-value of: calculating a signal-to-noise ratio in the transmission signal based on the reception level signal; controlling the Q-value control means based on the calculation result; And a signal-to-noise ratio measuring means for transmitting a signal to the transmitting side. 2. The clock extraction circuit according to claim 1, wherein the transmission signal is a high-frequency signal modulated based on transmission information to be transmitted. 3. The method according to claim 2, wherein the reception level signal is the digital PL.
3. The clock extraction circuit according to claim 1, wherein the clock extraction processing is stopped in the digital PLL circuit when the signal is input to an L circuit and the reception level is equal to or lower than a predetermined threshold. 4. A communication system comprising: a transmission device that receives transmission information as input and converts the transmission information into a transmission signal and transmits the transmission signal; and a reception device that receives the transmission signal and extracts the transmission information as output data. The transmitting apparatus adds a synchronization pattern, which is a pattern for establishing synchronization at a bit level, to the transmission information so as to precede the transmission information, converts the transmission information into the transmission signal, and transmits the transmission signal. A transmission circuit, and a synchronization pattern setting circuit for setting the synchronization pattern, wherein the reception device receives and converts the transmission signal and outputs it as a digital signal, and according to a reception level of the transmission signal. A reception circuit that outputs a reception level signal; a digital PLL circuit that extracts a clock signal synchronized with the digital signal from the digital signal; Q-value control means for controlling the Q-value of the digital PLL circuit; calculating a signal-to-noise ratio in the transmission signal based on the reception level signal; controlling the Q-value control means based on the calculation result; A signal-to-noise ratio measuring unit for transmitting a signal based on the calculation result to the synchronization pattern setting circuit. 5. The synchronization pattern setting circuit sets the synchronization pattern relatively short when the signal-to-noise ratio is relatively large, and sets the synchronization pattern relatively small when the signal-to-noise ratio is relatively small. The communication system according to claim 4, wherein the communication pattern sets the synchronization pattern relatively long. 6. The communication system according to claim 4, wherein the transmission signal is a high-frequency signal. 7. The method according to claim 7, wherein the reception level signal is the digital PL.
The communication system according to any one of claims 4 to 6, wherein the digital PLL circuit stops an operation of a clock extraction process when the signal is input to an L circuit and the reception level is equal to or lower than a predetermined threshold value. 8. A transmitting apparatus which receives transmission information as input, converts the transmission information into a transmission signal, and sends the transmission signal to a receiving side, wherein a synchronizing pattern for establishing synchronization at a bit level is included in the transmission information. A transmission circuit that adds the transmission information to the transmission information as described above, converts the transmission information into the transmission signal, and transmits the transmission signal; and a synchronization pattern setting circuit that sets the synchronization pattern. Information on the noise ratio is received from the receiving side, and when the signal-to-noise ratio is relatively large, the synchronization pattern setting circuit sets the synchronization pattern relatively short, and the signal-to-noise ratio is relatively small. The transmission apparatus, wherein the synchronization pattern setting circuit sets the synchronization pattern relatively long when the synchronization pattern is relatively small.