JP3252566B2 - Automatic frequency control circuit and its receiving device in spread spectrum communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit and its receiving apparatus in spread spectrum communication, and more particularly, to a chip clock on a transmission side (in this specification, it is always described as "chip clock". In the figure, “TxCLK” may be described.) And a sample clock on the receiving side (in this specification, “sample ×
Although it is described as "clock", it may be described as "RxCLK" in the figure. ) And an automatic frequency control circuit in spread spectrum communication that can pull in a reproduced carrier to an intermediate frequency carrier that forms an intermediate frequency signal in a short time even when the intermediate frequency signal is asynchronous, and an automatic frequency control circuit in the spread spectrum communication. The present invention relates to a receiver for spread spectrum communication to which a demodulation circuit is added.

Data 1 to be transmitted on the transmitting side
A bit is multiplied by a chip pattern which is a pseudo-random pattern on a bit-by-bit basis, and the transmission frequency band is expanded by several hundred to several thousand times the band of one bit of data to be transmitted (this is called spreading). A spread-spectrum communication system that transmits as a band signal and performs demodulation by correlating the chip pattern set identically to the chip pattern on the transmitting side with the baseband signal reproduced from the intermediate frequency band signal on the receiving side. Has been widely put to practical use.

The spread spectrum communication system spreads the spectrum by multiplying a base band signal and a chip pattern, which is a pseudo random pattern, bit by bit, so that interference with other communication paths can be reduced. And communication is possible even when the power per band is weak.

[0004] The spread spectrum communication system has the above features, but has a carrier-to-noise ratio (so-called "C / N").
Is extremely low, and it is difficult for an automatic frequency control circuit applied in a general wireless communication system or a wired communication system to reproduce a carrier. In order to solve this problem, an automatic frequency control circuit utilizing a frequency characteristic of a correlation value output by a correlator for correlating a baseband signal with a chip pattern on a receiving side has been put to practical use and applied. . In such an automatic frequency control circuit, it is important that a reproduced carrier wave exactly matching the intermediate frequency carrier wave forming the intermediate frequency signal can be obtained in a short time.

[0005]

2. Description of the Related Art A digital matched filter is a correlator used in a direct spread system of a spread spectrum communication system.

FIG. 7 shows an example of the configuration of a digital matched filter.

[0007] In FIG. 7, S1 denotes a base to be inputted.
This is a shift register that reads a band signal (indicated as “input signal” in the figure but is the same) with a sample clock. Here, it is a chip pattern (described as “PN pattern” in the figure). Shift register S1 is assumed to be 10 bits, so that the shift register S1 has 10 flip-flops F1.
To F10 in cascade connection.

C11 is a comparison circuit for comparing the chip pattern with the base band signal. The chip pattern (described as "PN pattern" in the figure but identical) is 10 bits. Therefore, the comparison circuit C11 is composed of ten comparators C1 to C10.

A1 is a chip output from the comparison circuit C11.
This is an adder for adding a comparison result between the pattern and the base band signal to obtain a correlation value. Then, the adder A1 outputs the correlation value in a parallel signal format of a plurality of bits. Although not shown in FIG. 7, a circuit for comparing the correlation value with a predetermined threshold value and actually outputting a detection pulse when detecting that the correlation value exceeds the threshold value is also provided. .

[0010] Each of the comparators C1 to C10 constituting the comparison circuit C11 outputs, for example, + when the logic level of the base band signal matches the chip pattern.
1 is output when the baseband signal does not match the chip pattern.

Accordingly, when the chip clock on the transmitting side and the sample clock on the receiving side are synchronized, when all the logic levels of the baseband signal match the chip pattern, the correlation value becomes 10, and the base value becomes 10. The correlation value is -10 when the logic level of the band signal is negative and all the patterns match the chip pattern, and if they do not match, the correlation value becomes a small value determined by the autocorrelation coefficient of the chip pattern.

FIG. 8 is a diagram showing a conventional example of an automatic frequency control circuit to which a digital matched filter is applied.

[0013] In FIG. 8, 11 at the input (FIG intermediate frequency signal is described as "IF Input". Later
Are similarly indicated in the figure. ), An intermediate frequency mixer that reproduces a base band signal using a reproduced carrier, 12 is an analog-to-digital converter that quantizes the base band signal output from the intermediate frequency mixer and converts it into a digital signal, and 13 is an analog-to-digital converter A digital matched filter that compares the output of the chip 12 with the chip pattern and outputs the correlation value and the detection pulse; 22 generates a sample clock to be supplied to the digital matched filter 13 based on the detection pulse A phase lock loop circuit 15 for outputting a frequency discrimination signal for reducing a frequency difference between an intermediate frequency carrier forming an intermediate frequency signal and a reproduction carrier using the correlation value and the detection pulse; A digital-to-analog converter for converting the frequency discrimination signal output from the frequency discriminator 15 into an analog signal; Is abbreviated as "VCO" is the voltage controlled oscillator (Figure by the analog output of the digital-to-analog converter 16. Later
The frequency control circuit 18 controls the oscillation frequency. Note that the output of the voltage controlled oscillator 18 is
The force is supplied to the intermediate frequency mixer 11 as a carrier.

FIG. 8 shows a configuration of a chip on the transmitting side.
Even if the clock and the sample clock generated on the receiving side are asynchronous, finally, the frequency of the intermediate frequency carrier and the frequency of the reproduced carrier are made to match, and the digital matched filter 13 outputs the same frequency as the chip clock on the transmitting side. Operates so as to be supplied with the sample clock.

[0015]

However, if the chip clock on the transmitting side and the sample clock generated on the receiving side are asynchronous at the time of starting the frequency pull-in in the automatic frequency control circuit, however, the frequency relationship between the two is determined. There is a problem in that the correlation value output from the digital matched filter 12 fluctuates, and the time required for pulling in the reproduced carrier with respect to the frequency of the intermediate frequency carrier becomes long. Hereinafter, this point will be described.

FIG. 5 is a diagram for explaining a correlation value when the chip clock is synchronized with the sample clock. For the sake of simplicity, in a spread spectrum communication having a chip pattern length of 10 bits and a chip frequency of 10 MHz, a sample clock is one clock per chip,
That is, a hard decision digital matched filter whose sample clock is 10 MHz will be described as an example.

In FIG. 5, RxDATA is a reproduced base band signal, one rectangle represents 1-bit data, and the repetition frequency of continuous data is equal to the frequency of the chip clock on the transmission side.

RxCLK is a sample clock for writing a base band signal to a shift register constituting a digital matched filter. For now, it is assumed that the chip clock and the sample clock are synchronized.
The period is equal to one bit time of the baseband signal.
Although not shown, the rising edge of the chip clock coincides with the data switching point of the base band signal.

Further, S / R is data obtained by reading a base band signal into a shift register by a sample clock. If it is assumed that the previous data is read when the switching point of two consecutive data in the base band signal is read by the sample clock, the shift register stores the data obtained by shifting the base band signal by one bit. Will be read. Then, since the sample clock is synchronized with the base band signal, the correlation value is obtained every chip pattern period, that is, every 10 bits.

Therefore, if all bits match the chip pattern, the correlation value becomes the maximum value of 10. In this case, the correlation value is always 10 regardless of the phase relationship between the sample clock and the baseband signal. That is, when the chip clock is synchronized with the sample clock, and the above assumption holds, the correlation value is always 10.

FIG. 9 is a diagram for explaining a correlation value when the frequency ratio between the chip clock and the sample clock is 9:10.

In FIG. 9A, the rising of the chip clock (not shown) and the rising of the sample clock coincide at the switching point of data A and data B on the left side of the baseband signal. Since the correlation value is obtained from the time when both rising edges coincide with each other to the last bit of the chip pattern, the correlation value in this case is 10 under the same assumption as in FIG.

On the other hand, in FIG. 9B, the frequency relationship between the chip clock and the sample clock is shown in FIG.
FIG. 9 shows a case where the phases of the chip clock and the sample clock are different from those in FIG.
In this case, the rising of the chip clock (not shown) and the rising of the sample clock coincide at the switching point of data E and data F on the left side of the baseband signal. Since the correlation value is obtained from the time when both rising edges coincide with each other to the last bit of the chip pattern, the correlation value in this case is 6 under the same assumption as in FIG.

Actually, FIG. 9 (2) shows the case where the correlation value is minimum, and when the phase relationship between the chip clock and the sample clock is intermediate between FIGS. 9 (1) and 9 (2), Is 9 to 7.

When the frequency difference between the chip clock and the sample clock is 1 Hz or less per chip cycle,
When the chip pattern length is even, the correlation value fluctuates between the maximum value and the maximum value / 2 + 1. Similarly, when the frequency difference between the chip clock and the sample clock is equal to or less than one chip clock cycle per one chip period and the chip pattern length is an odd number, the correlation value is equal to the maximum value (maximum value +
1) / 2.

That is, in the configuration of FIG. 8, when the chip clock and the sample clock are not synchronized, the correlation value output of the digital matched filter fluctuates in the initial phase acquisition stage of the automatic frequency control circuit. Even when the correlation value indicates the maximum value, the frequency of the intermediate frequency carrier and the frequency of the reproduced carrier do not always match. Therefore,
Until the phase locked loop circuit generates a sample clock synchronized with the chip clock, a correct correlation value cannot be obtained, and there is a problem that it takes time to pull in the frequency.

In view of the above problem, the present invention relates to an automatic frequency control circuit in spread spectrum communication and a receiving apparatus therefor, and an intermediate frequency signal is output even when a chip clock on a transmitting side and a sample clock on a receiving side are asynchronous. An automatic frequency control circuit in spread spectrum communication capable of pulling in a reproduced carrier in a short time with respect to an intermediate frequency carrier to be formed, and a receiving apparatus in spread spectrum communication in which a demodulation circuit is added to the automatic frequency control circuit in spread spectrum communication. The purpose is to provide.

[0028]

Means for Solving the Problems A first aspect of the present invention provides a base station having a repetition frequency equal to a chip clock on a transmitting side reproduced by a reproduction carrier from an intermediate frequency band signal.
A first signal for correlating the band signal with a chip pattern set to be identical to the chip pattern on the transmission side and outputting a correlation value and a detection pulse that detects that the correlation value exceeds a predetermined threshold value. A digital matched filter; a frequency discriminator for outputting a frequency discrimination signal for reducing a frequency difference between an intermediate frequency carrier forming the intermediate frequency band signal and the reproduction carrier based on the correlation value and the detection pulse; and the frequency discrimination A frequency control circuit for controlling an oscillation frequency of a first voltage-controlled oscillator that generates the reproduced carrier by a signal, wherein the baseband signal is converted to the first digital matched signal. The frequency of the sample clock to be read into the filter is compared with the frequency of the transmitting chip clock by a spread spectrum code. 2 chip clock per cycle -
An automatic frequency control circuit in spread spectrum communication characterized by differentiating only by a cycle.

According to the first invention, the frequency of the sample clock for reading the baseband signal into the first digital matched filter is determined by the transmitting chip.
Since the frequency of the clock is different by two chip clock cycles per one cycle of the spread spectrum code, the rising of the chip clock and the sample clock are independent of the phase relationship between the chip clock and the sample clock. After the clock rise coincides, the time until the rise of the chip clock coincides with the rise of the sample clock again becomes constant.
In the first digital matched filter, the correlation between the chip clock and the baseband signal is obtained within the above time, so that the correlation value is always constant, and the frequency discrimination signal is generated using the constant correlation value. Control the frequency of the reproduced carrier by reducing the time required to pull in the frequency of the reproduced carrier to the intermediate frequency carrier, and when the frequency pull-in is completed, match the frequency of the reproduced carrier with the frequency at which the correlation value has the maximum value. Can be done.

According to a second aspect of the present invention, there is provided the automatic frequency control circuit in the spread spectrum communication according to the first aspect, wherein the frequency of the reproduced carrier output from the first voltage controlled oscillator is equal to the frequency of the intermediate frequency carrier. The above base
The band signal is read, and a correlation is made with a chip pattern set identically to the chip pattern on the transmission side, and a correlation value and a detection pulse which detects that the correlation value exceeds a predetermined threshold are output and demodulated. A second digital matched filter to be supplied to the processing unit, and a phase for generating a sample clock in the second digital matched filter based on the detection pulse output from the second digital matched filter A receiving device for spread spectrum communication characterized by adding a demodulation circuit having a lock loop circuit.

According to the second aspect of the present invention, the time for pulling in the frequency of the reproduced carrier with respect to the intermediate frequency carrier can be shortened, and when the frequency pull-in is completed, the frequency of the reproduced carrier is set to the frequency at which the correlation value becomes the maximum value. Since the demodulation circuit is added to the automatic frequency control circuit that can match, the correlation value in the second digital matched filter in the demodulation circuit becomes the maximum value when synchronized with the sample clock and the chip clock, Correct data can be obtained by demodulation.

[0032] The third invention is, in the receiver in a spread spectrum communication of the second invention, the second
And supplies the correlation value and the detection pulse output by the first digital matched filter to the demodulation processing unit, and reproduces the reproduced carrier wave output by the first voltage-controlled oscillator. Before the frequency of the intermediate frequency carrier becomes equal to the frequency of the intermediate frequency carrier, the sample clock supplied to the first digital matched filter is set to two chips per one cycle of the spread spectrum code with respect to the frequency of the transmitting chip clock. clock cycle only supplied from different oscillator, said in the state in which the frequency of the regenerated carrier is equal to the frequency of said intermediate frequency carrier first voltage controlled oscillator output, supplied to the digital matched filter of the first To supply a sample clock to be generated from a phase locked loop circuit that generates the sample clock based on the detected pulse A receiving apparatus in a spread spectrum communication, characterized in that it comprises.

According to the third invention, the correlation value and the detection pulse output from the first digital matched filter are supplied to the demodulation processing unit, and the reproduction output from the first voltage controlled oscillator is supplied. Before the frequency of the carrier equals the frequency of the intermediate frequency carrier, the first digital
A sample clock to be supplied to the matched filter is supplied from an oscillator that differs from the frequency of the chip clock on the transmitting side by two chip clock cycles per cycle of the spread spectrum code, and is output from the first voltage controlled oscillator. In a state where the frequency of the reproduction carrier is equal to the frequency of the intermediate frequency carrier, the sample clock supplied to the first digital matched filter is supplied to the first digital matched filter based on the detection pulse. Since the configuration is such that a sample clock is generated from a phase-locked loop circuit, one digital matched filter can be deleted, and the configuration of the receiving apparatus in spread spectrum communication can be simplified. , Cost reduction becomes possible.

According to a fourth aspect, in the receiving apparatus for spread spectrum communication according to the third aspect, the oscillation device may
Vessel was removed, the above prior first voltage controlled oscillator the frequency of the recovered carrier outputs equal to the frequency of the intermediate frequency carrier, the oscillation frequency to a second voltage controlled oscillator that constitutes the phase-locked loop circuit the frequency of the recovered carrier but which supplies an offset voltage which is only different frequency 2 chip clock cycles per cycle of the spread spectrum code for frequencies the transmitter chip clock, said first voltage controlled oscillator output the state is equal to the frequency of said intermediate frequency carrier, a voltage obtained by the phase comparison between the output of said detection pulse and said second voltage controlled oscillator in which the first digital matched filter outputs fed to said second voltage controlled oscillator, a sample clock output of said second voltage controlled oscillator to said first digital matched filter Providing the structure for supplying Te is a receiving apparatus in a spread spectrum communication according to claim.

According to the fourth aspect, before the frequency of the reproduced carrier outputted from the first voltage controlled oscillator becomes equal to the frequency of the intermediate frequency carrier, the second phase-locked loop circuit is constituted. An offset voltage is supplied to the voltage-controlled oscillator such that the oscillation frequency of the second voltage-controlled oscillator is different from the frequency of the transmitting-side chip clock by two chip clock cycles per one cycle of the spread spectrum code. When the frequency of the reproduced carrier output by the first voltage controlled oscillator is equal to the frequency of the intermediate frequency carrier, the detection pulse output by the first digital matched filter and the second voltage control A voltage obtained by comparing the phase with the output of the oscillator is supplied to the second voltage-controlled oscillator, and the output of the second voltage-controlled oscillator is output from the first data-controlled oscillator. Since the signal is supplied as a sample clock to the total matched filter, one digital matched filter can be deleted, the configuration of the receiving apparatus in spread spectrum communication can be simplified, and the cost can be reduced. .

[0036]

Hereinafter, the technology of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes an intermediate frequency mixer that reproduces a base band signal from an input of the intermediate frequency signal using a reproduced carrier wave, and 12 quantizes the base band signal output from the intermediate frequency mixer and converts the quantized base band signal into a digital signal. An analog-to-digital converter 13 compares the output of the analog-to-digital converter 12 with the chip pattern and outputs a correlation value and a detection pulse.
The filter 14 has a fixed oscillation frequency (hereinafter, abbreviated as “OSC” in the figure) that generates a sample clock for reading the output of the analog-to-digital converter 13 into the digital matched filter 13. , 15 is a frequency discriminator that outputs a frequency discrimination signal for reducing a frequency difference between an intermediate frequency carrier forming an intermediate frequency signal and a reproduced carrier using the correlation value and the detection pulse, and 16 is a frequency discriminator. A digital / analog converter 17 converts the frequency discrimination signal output from the discriminator 15 into an analog signal. Reference numeral 17 denotes a voltage controlled oscillator (abbreviated as “VCO” in the figure) by an analog output of the digital / analog converter 16.
18 is a frequency control circuit for controlling the oscillation frequency.
The output of the voltage controlled oscillator 18 is supplied to the intermediate frequency mixer 11.
Provided as a carrier.

A feature of the configuration shown in FIG. 1 is that the oscillation frequency of the oscillator 14 differs from the frequency of the chip clock on the transmission side by two chip clock cycles per one cycle of the spread spectrum code. .

FIG. 6 is a diagram for explaining the correlation value when the frequency ratio between the chip clock and the sample clock is 8:10.

FIG. 6A shows a case where the rising of the chip clock (not shown) and the rising of the sample clock coincide at the switching point of data A and data B on the left side of the baseband signal. in this case,
Next, the rising edge of the chip clock coincides with the rising edge of the sample clock at the switching point between the data E and the data F of the baseband signal. Since the correlation value is obtained between the times when both rising edges coincide with each other, the correlation value in this case is 5 under the same assumption as in FIG.

On the other hand, FIG. 6 (2) shows that the frequency relationship between the chip clock and the sample clock is the same as that of FIG. 6 (1), but the phases of the chip clock and the sample clock are different from those of FIG. 6 (1). Shows different cases. In this case, it is assumed that the rising of the chip clock (not shown) and the rising of the sample clock coincide at the switching point between the data B and data C of the baseband signal. In this case, the rising edge of the chip clock coincides with the rising edge of the sample clock at the switching point between the data E and the data F of the baseband signal. Since the correlation value is obtained between the times when both rises coincide, if the same assumption is made as in FIG. 5, the correlation value will be 5 in this case as well.

The correlation value is 5 regardless of the phase relationship between the chip clock and the sample clock.

In the configuration of FIG. 1, while controlling the first voltage-controlled oscillator so as to sweep the frequency in a preset range, the frequency discrimination obtained from the correlation value output from the digital matched filter 13 and the detection pulse is performed. Hold the signal,
When the sweep is completed, control is performed such that the oscillation frequency of the first voltage controlled oscillator 18 becomes equal to the frequency of the intermediate frequency carrier.

Since the correlation value does not fluctuate due to the phase relationship between the chip clock and the sample clock during the above control, the oscillation frequency of the first voltage-controlled oscillator 18 does not drop to the wrong frequency. FIG.
In the above configuration, the above-described control is performed while the chip clock and the sample clock are in an asynchronous state, so that it is possible to reduce the time for drawing the frequency of the sample clock to the frequency of the chip clock.

FIG. 2 shows a receiving apparatus in spread spectrum communication according to a second embodiment of the present invention in which a demodulation circuit is added to the automatic frequency control circuit having the configuration shown in FIG.

In FIG. 2, reference numeral 11 denotes an intermediate frequency mixer that reproduces a base band signal from the input of the intermediate frequency signal using a reproduced carrier, and 12 quantizes the base band signal output by the intermediate frequency mixer and converts the quantized base band signal into a digital signal. An analog-to-digital converter 13 compares the output of the analog-to-digital converter 12 with the chip pattern and outputs a correlation value and a detection pulse.
Filter, 14 an oscillation frequency fixed oscillator for generating a sample clock to the digital matched filter 13 reads the output of the analog-digital converter 12, 15
Is a frequency discriminator that outputs a frequency discrimination signal that reduces a frequency difference between an intermediate frequency carrier and a reproduced carrier that forms an intermediate frequency signal using the correlation value and the detection pulse, and 16 is a frequency that the frequency discriminator 15 outputs. A digital-to-analog converter 17 converts the discrimination signal into an analog signal.
The frequency control circuit controls the oscillation frequency of the automatic frequency control circuit 8. The automatic frequency control circuit 10 is configured by the above components.
The output of the voltage controlled oscillator 18 is supplied to the intermediate frequency mixer 11.
Provided as a carrier.

The reference numeral 21 fetches the base band signal output from the analog-to-digital converter 12 and correlates the same with the same chip pattern used on the transmitting side. The correlation value is larger than a predetermined threshold value. A second digital matched filter that outputs a detection pulse that detects that
22 is a phase locked loop circuit for synchronizing the sample clock with the chip clock based on the detection pulse.
A demodulation processing unit 3 generates demodulated data using the correlation value and the detection pulse.
0 is configured.

In the configuration of FIG. 2, the automatic frequency control circuit 10
Generates a reproduced carrier having a frequency equal to the frequency of the intermediate frequency carrier, and converts the baseband signal reproduced from the intermediate frequency signal by the reproduced carrier into an analog-to-digital converter 1
The signal is supplied to the second digital matched filter 21 constituting the demodulation circuit 20 via 2.

In the demodulation circuit 20, the phase lock loop circuit 22 generates a sample clock based on the detection pulse output from the second digital matched filter 21 and supplies the sample clock to the second digital matched filter 21. Therefore, the second digital matched filter 21 can output a stable correlation value and a detected pulse. Therefore, the demodulation circuit 20 can generate correct demodulated data.

FIG. 3 shows a third embodiment of the present invention, which is a receiving apparatus in spread spectrum communication having the same function as the configuration of FIG. 2, and uses two digital matched filters in the configuration of FIG. 3 shows a configuration of a receiving apparatus that can reduce one.

In FIG. 3, reference numeral 11 denotes an intermediate frequency mixer that reproduces a baseband signal from the input of the intermediate frequency signal using a reproduced carrier, and 12 quantizes the baseband signal output by the intermediate frequency mixer and converts the quantized baseband signal into a digital signal. An analog-to-digital converter 13 is a first digital matched filter that compares the output of the analog-to-digital converter 12 with the chip pattern and outputs a correlation value and a detection pulse, and 14 is a first digital matched filter. An oscillator having a fixed oscillation frequency for generating a sample clock for reading the output of the analog-to-digital converter 12 into the filter 13; a reference numeral 22 synchronizes the sample clock with the chip clock on the basis of the detected pulse to generate a sample clock after completion of the frequency sweep; A phase locked loop circuit for supplying one digital matched filter 13; Reference numeral 5 denotes a frequency discriminator for outputting a frequency discrimination signal for reducing a frequency difference between an intermediate frequency carrier and a reproduced carrier, which forms an intermediate frequency signal, using the correlation value and the detection pulse. A digital-to-analog converter for converting the frequency discrimination signal into an analog signal, 17 is a frequency control circuit for controlling the oscillation frequency of the voltage controlled oscillator 18 by an analog output of the digital-to-analog converter 16, and 23 uses the correlation value and the detection pulse. demodulation processing unit to generate the demodulated data, 24 sweep Kan
Selects the output of oscillator 14 before completion, and phase
To select the output of the first digital
A switch for supplying to the matched filter 13;
The output of the voltage controlled oscillator 18 is supplied to the intermediate frequency mixer 11.
Provided as a carrier.

The configuration of FIG. 3 is characterized in that the first digital matched filter 13 is a digital matched filter for performing automatic frequency control and the correlation value is demodulated by the demodulation processing unit 2.
3 in that it is shared as a digital matched filter for supplying the signal to C.3. For this purpose, in the configuration of FIG. 3, the output of the oscillator 14 and the output of the phase locked loop circuit 22 are switched by the sweep completion signal output from the frequency control circuit 17, and the sample clock is supplied to the first digital matched filter 13. The switch 24 is provided as a switch.

That is, before the sweep is completed, the intermediate frequency mixer 11, the analog / digital converter 12, the first digital matched filter 13, the oscillator 14, the frequency discriminator 15, the digital / analog converter 16, the frequency control In the automatic frequency control circuit comprising the circuit 17 and the voltage controlled oscillator 18, the reproduced carrier is pulled into the frequency of the intermediate frequency carrier, and after the sweep is completed, the intermediate frequency mixer 11, the analog-to-digital converter 12, the first digital matched filter 13, an automatic frequency control circuit including a phase lock loop circuit 22, a frequency discriminator 15, a digital / analog converter 16, a frequency control circuit 17, and a voltage controlled oscillator 18 locks the reproduced carrier to the frequency of the intermediate frequency carrier, First digital matched filter 13, phase lock Loop circuit 22, a demodulation processing unit 23
Demodulated data is generated by a demodulation circuit comprising

Therefore, the configuration of FIG. 3 is obtained by removing the second digital matched filter 22 from the configuration of FIG. 2, and can simplify the configuration of the receiving device in spread spectrum communication.

FIG. 4 shows a fourth embodiment of the present invention, which is a receiving apparatus in spread spectrum communication having the same function as the configuration of FIG. 2. In the configuration of FIG. 2, a digital matched filter using two is used. 3 shows a configuration of a receiving apparatus that can reduce one.

In FIG. 4, reference numeral 11 denotes an intermediate frequency mixer that reproduces a baseband signal from the input of the intermediate frequency signal using a reproduced carrier wave, and 12 quantizes the baseband signal output from the intermediate frequency mixer and converts the quantized baseband signal into a digital signal. The analog-to-digital converter 13 is a first digital matched filter that compares the output of the analog-to-digital converter 12 with the chip pattern and outputs a correlation value and a detection pulse, and 28 is a filter before completion of the frequency sweep. First
A fixed frequency clock is supplied as a sample clock for reading the output of the analog-to-digital converter 12 to the digital matched filter 13 and a clock synchronized with the chip clock is supplied as a sample clock after the frequency sweep is completed. The second voltage controlled oscillator, 26
Phase of the detection pulse and the output of the second voltage controlled oscillator 28
And 27 is a direct current of the output of the phase comparator.
Low-pass filter to extract the minute (abbreviated as "LPF" in the figure)
I have. ), 29 are the output frequencies of the second voltage controlled oscillator 28
Number to spectrum of transmitting chip clock
2 chip clock size per cycle of ram spreading code
Generate an offset voltage that makes the frequency different
The offset voltage generation circuit 24 has an offset voltage before the sweep is completed.
Select the output of the voltage generator, and after the sweep is completed,
And selects the output of the output device 27 and supplies it to the second voltage controlled oscillator.
That switch, 15 a frequency discriminator for outputting a frequency discriminating signal for reduction the frequency difference of the intermediate frequency carrier and the recovered carrier to form an intermediate frequency signal by using the correlation value and the detection pulse, 16 a frequency discriminator 15 Is a digital-to-analog converter that converts the frequency discrimination signal output from the digital-to-analog converter into an analog signal; 17 is a frequency control circuit that controls the oscillation frequency of the voltage-controlled oscillator 18 using the analog output of the digital-to-analog converter 16; This is a demodulation processing unit that generates demodulated data using pulses. In addition, voltage controlled oscillation
Output of the mixer 18 is supplied to the intermediate frequency mixer 11 as a carrier wave.
Is done.

A feature of the configuration of FIG. 4 is that the first digital matched filter 13 is a digital matched filter for performing automatic frequency control and the correlation value is demodulated by the demodulation processing unit 2.
3 in that it is shared as a digital matched filter for supplying the signal to C.3. To this end, the configuration of FIG. 4 includes an offset voltage generation circuit 29 that supplies an offset voltage for causing the second voltage controlled oscillator 28 to oscillate at a fixed frequency.
A phase detector 26 for comparing the output of the second voltage-controlled oscillator 28 with the phase of the detection pulse; and a low-pass filter ("LP" in the figure) for extracting the DC component of the output of the phase detector 26.
F ". ) And the offset voltage generation circuit 2
4 and a switch 24 for selecting one of the output of the low-pass filter 27 and the output of the low-pass filter 27 based on the sweep completion signal output from the frequency control circuit 17.

That is, before the sweep is completed, the intermediate frequency mixer 11, the analog-to-digital converter 12, the first digital matched filter 13, and the offset voltage generating circuit 2
9. In the automatic frequency control circuit including the second voltage-controlled oscillator 28, the frequency discriminator 15, the digital / analog converter 16, the frequency control circuit 17, and the voltage-controlled oscillator 18, the reproduced carrier is pulled into the frequency of the intermediate frequency carrier.
After the completion of the sweep, the intermediate frequency mixer 11, the analog-to-digital converter 12, the first digital matched filter 1
3, frequency discriminator 15, digital / analog converter 1
6. An automatic frequency control circuit comprising a frequency control circuit 17 and a voltage controlled oscillator 18 locks the reproduced carrier to the frequency of the intermediate frequency carrier and
Matched filter 13, second voltage controlled oscillator 28,
Phase detector 26, low-pass filter 27, and demodulation processing unit 2
3. Demodulated data is generated by the demodulation circuit composed of 3.

Therefore, the configuration of FIG. 4 is obtained by removing the second digital matched filter 22 from the configuration of FIG. 2, and can simplify the configuration of the receiving apparatus in spread spectrum communication. The circuit including the oscillator 14, the phase locked loop circuit 22, and the switch 24 in the configuration of FIG.
8, a circuit comprising an offset voltage generating circuit 29, a phase detector 26, a low-pass filter 27 and a switch 24.

Examining the circuit in more detail, the oscillator 14 in FIG. 3 and the voltage-controlled oscillator arranged in the phase-locked loop circuit 22 are shared, and the switch 24 is included in the configuration of the phase-locked loop circuit. It can be seen that they are arranged. Therefore, it can be said that the configuration of FIG. 4 is a further simplification of the configuration of FIG.

[0062]

As described above in detail, according to the present invention, an automatic frequency control circuit and its receiving apparatus in spread spectrum communication are reproduced even when the transmitting-side chip clock and the receiving-side sample clock are asynchronous. An automatic frequency control circuit in spread spectrum communication that can pull the carrier frequency to the intermediate frequency carrier frequency in a short time, and a receiving device in spread spectrum communication that adds a demodulation circuit to the automatic frequency control circuit in spread spectrum communication. can do.

That is, according to the first invention, the frequency of the sample clock for reading the baseband signal into the first digital matched filter is set to be different from the frequency of the chip clock on the transmitting side by the spread spectrum code. Of 1
Because the chip clock and the sample clock rise coincide, regardless of the phase relationship between the chip clock and the sample clock, they differ by two chip clock cycles per cycle. Is constant until the rising edge of the sample clock coincides with the rising edge of the sample clock. In the first digital matched filter, the correlation value between the chip clock and the baseband signal is obtained within the above time, so that the correlation value is always constant, and a frequency discrimination signal is generated using the constant correlation value. Control the frequency of the reproduced carrier by reducing the time required to pull in the frequency of the reproduced carrier to the intermediate frequency carrier, and when the frequency pull-in is completed, match the frequency of the reproduced carrier with the frequency at which the correlation value has the maximum value. Can be done.

According to the second aspect of the present invention, the time for pulling in the frequency of the reproduced carrier with respect to the intermediate frequency carrier can be shortened, and when the frequency pull-in is completed, the frequency of the reproduced carrier is set to the frequency at which the correlation value becomes the maximum value. Since the demodulation circuit is added to the automatic frequency control circuit that can match, the correlation value in the second digital matched filter in the demodulation circuit becomes the maximum value when the sample clock and the chip clock are synchronized. Correct data can be obtained by demodulation.

According to the third aspect of the invention, the correlation value and the detection pulse output from the first digital matched filter are supplied to the demodulation processing section, and the frequency of the reproduced carrier output from the voltage controlled oscillator is adjusted to the intermediate frequency carrier. Before the frequency becomes equal to the frequency of the sampled clock supplied to the first digital matched filter, the sample clock supplied from the oscillator which differs from the frequency of the transmitting chip clock by 2 chip clock cycles per cycle of the spread spectrum code. In the state where the frequency of the reproduced carrier outputted from the voltage controlled oscillator is equal to the frequency of the intermediate frequency carrier, the sample clock supplied to the first digital matched filter is supplied to the first digital matched filter based on the detection pulse. From a phase-locked loop circuit that generates a sample clock to a single digital matched filter Since it is configured to feed, it is possible to remove a digital matched filter, can simplify the configuration of a receiving apparatus in a spread spectrum communication allows cost reduction.

According to the fourth invention, before the frequency of the reproduced carrier outputted from the voltage controlled oscillator becomes equal to the frequency of the intermediate frequency carrier, the second voltage controlled oscillator constituting the phase locked loop circuit is supplied to the second voltage controlled oscillator. Supplying an offset voltage at which the oscillation frequency of the voltage-controlled oscillator is different from the frequency of the transmitting-side chip clock by two chip clock cycles per one cycle of the spread spectrum code;
When the frequency of the reproduced carrier output by the voltage controlled oscillator becomes equal to the frequency of the intermediate frequency carrier, the phase of the detection pulse output by the first digital matched filter and the output of the second voltage controlled oscillator are changed. The voltage obtained by the comparison is supplied to the second voltage controlled oscillator, and the output of the second voltage controlled oscillator is supplied to the first digital matched filter as a sample clock. This makes it possible to delete one, and the configuration of the receiving apparatus in spread spectrum communication can be simplified, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 shows a first embodiment.

FIG. 2 shows a second embodiment.

FIG. 3 shows a third embodiment.

FIG. 4 shows a fourth embodiment.

FIG. 5 is a view for explaining a correlation value when a chip clock and a sample clock are synchronized.

FIG. 6 is a view for explaining a correlation value when a frequency ratio between a chip clock and a sample clock is 8:10.

FIG. 7 is a configuration example of a digital matched filter.

FIG. 8 shows a conventional example.

FIG. 9 is a view for explaining a correlation value when the frequency ratio between the chip clock and the sample clock in the conventional example is 9:10.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 automatic frequency control circuit 11 intermediate frequency mixer 12 analog-to-digital converter 13 first digital matched filter 14 oscillator 15 frequency discriminator 16 digital-to-analog converter 17 frequency control circuit 18 first voltage-controlled oscillator 20 demodulation circuit Reference Signs List 21 second digital matched filter 22 phase locked loop circuit 23 demodulation processing unit 24 switch 26 phase detector 27 low-pass filter 28 second voltage controlled oscillator 29 offset voltage generation circuit

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04B 1/69-1/713 H04J 13/00-13/06

Claims (4)

(57) [Claims] 1. A base band signal having a repetition frequency equal to a chip clock on a transmitting side reproduced by a reproduced carrier from an intermediate frequency band signal and a chip pattern set identically to the chip pattern on the transmitting side. A first digital matched filter that outputs a detection pulse that detects that the correlation value has exceeded a predetermined threshold value by taking a correlation; and the intermediate frequency band signal is generated by the correlation value and the detection pulse. A frequency discriminator for outputting a frequency discrimination signal for reducing a frequency difference between the intermediate frequency carrier to be formed and the reproduction carrier, and a frequency for controlling a transmission frequency of a first voltage-controlled oscillator for generating the reproduction carrier by the frequency discrimination signal An automatic frequency control circuit for spread spectrum communication, comprising: a baseband signal; De
Automatic frequency control in spread spectrum communication characterized in that the frequency of a sample clock to be read into a filter is made different from the frequency of a chip clock on the transmission side by two chip clock cycles per one cycle of a spread spectrum code. circuit. 2. The automatic frequency control circuit in spread spectrum communication according to claim 1, wherein said base station is in a state where a frequency of a reproduced carrier outputted from said first voltage controlled oscillator is equal to a frequency of said intermediate frequency carrier. Read the band signal and send the chip
A second digital circuit for correlating the pattern with a chip pattern set identically and outputting a correlation value and a detection pulse for detecting that the correlation value exceeds a predetermined threshold value and supplying the detected pulse to a demodulation processing unit; and matched filter, a demodulation circuit and a phase locked loop circuit for supplying a sample clock to said second digital matched filter in the detection based on the pulse digital matched filter of the second outputs A receiving device in spread spectrum communication, characterized by being additionally provided. 3. The receiving apparatus according to claim 2, wherein the second digital matched filter is removed, and the correlation value and the detection pulse output by the first digital matched filter. Is supplied to the demodulation processing unit, and before the frequency of the reproduced carrier output from the first voltage-controlled oscillator becomes equal to the frequency of the intermediate frequency carrier, the sample supplied to the first digital matched filter is clocks supplied from the 2-chip clock cycles only different oscillators per period of the spread spectrum code for frequencies the transmitter chip clock, said first voltage controlled oscillator the frequency of the recovered carrier outputs the intermediate frequency With the frequency equal to the carrier frequency,
In a spread spectrum communication, characterized in that it comprises a structure for supplying a phase lock loop circuit for generating the sub emission <br/> pull clock reference detection pulses supplied to the digital matched filter of the first Receiver. 4. The receiving apparatus for spread spectrum communication according to claim 3, wherein the oscillator is removed, and the frequency of the reproduced carrier outputted from the first voltage controlled oscillator becomes equal to the frequency of the intermediate frequency carrier. The oscillation frequency of the second voltage-controlled oscillator constituting the phase locked loop circuit is two chips per one cycle of the spread spectrum code with respect to the frequency of the chip clock on the transmitting side.
Supplying an offset voltage which is only different frequency clock cycle, the state in which the frequency of the regenerated carrier is equal to the frequency of said intermediate frequency carrier to which the first voltage controlled oscillator output,
Supplying a voltage obtained by the phase comparison between the output of said detection pulse and said second voltage controlled oscillator in which the first digital matched filter outputs to said second voltage controlled oscillator, said second receiving apparatus in a spread spectrum communication output of the voltage controlled oscillator, characterized in that it comprises a structure for supplying a sample clock to the first digital matched filter.