JP2000261421A - Clock and data regenerating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock and data reproducing circuit that can stably be in operation even when a multi-rate signal is received without remarkable revision of a conventional configuration. SOLUTION: A packet selection circuit 5a is provided in a pre-stage of a clock regenerative circuit 22 and a data reproducing circuit 21 to select a packet with a desired transmission rate and excludes a packet with a transmission rate that may possibly disturb clock regeneration. Furthermore, the packet selection circuit 5a is provided only to the pre-stage of the cock regenerative circuit 22 to select a packet at a desired transmission rate and to exclude a packet with a transmission rate that may possibly disturb the clock regeneration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock and data recovery circuit, and more particularly to a clock and data recovery circuit used in a receiving device in a slave device in a data transmission system.

[0002]

2. Description of the Related Art Generally, a data transmission system for transmitting information by transmitting each information packet having a predetermined transmission rate from a transmission device in a main device and receiving and reproducing the information packet in a reception device in a subordinate device. In the above, a clock and data recovery circuit is provided in a reception device in a slave device, and a clock and desired data required for data transmission are reproduced from a received signal.

FIG. 10 is an explanatory view showing an example of the configuration of a conventional clock and data recovery circuit.
(B) is a timing chart showing the operation. The optical signal of a single transmission rate transmitted from the transmission device in the main device is converted into an electric signal in the subordinate device and amplified to a sufficient level by the amplifier, and then the input signal Di is input.
clock and data recovery circuit 2 from input terminal 1 as n
Is input to

When an electric signal is transmitted from a transmitting device in the main device, the electric signal is amplified to a sufficient level by an amplifier in a slave device, and then input as an input signal Din from an input terminal 1 to a clock and data reproducing circuit 2. Is done.
In the clock and data recovery circuit 2, the input signal Di
n is branched at a branch point 23 and input to both the data recovery circuit 21 and the clock recovery circuit 22.

[0005] In the clock recovery circuit 22, the input signal Di
The phase timing is determined using the rising (or falling) point of n, the timing and the clock frequency are adjusted based on the determination result, and the clock Cout is reproduced and output. Further, the data recovery circuit 21 determines whether or not the data amplitude exceeds a threshold value based on the clock Cout recovered by the clock recovery circuit 22, and reproduces and outputs the received data Dout.

[0006]

However, the conventional clock and data recovery circuit used for transmission at a single transmission speed between the master device and the slave device has different transmission speeds (pit rates). When a multi-rate signal including a packet is input, there is a problem as shown in FIG. FIG. 11 is a timing chart showing an operation example of a conventional clock and data recovery circuit.

First, the receivable transmission speed of the slave device is represented by f
o (bps), and the reception timing is signal a. At this time, the clock CLK reproduced by the clock reproduction circuit 22 is fo (Hz). Here, when a signal b having a transmission speed fo / n (n is a natural number) is input to the clock and data recovery circuit (for example, n = 2), the rising (falling) of the signal b is equal to the signal a. There is no problem because it occurs in the same place.

On the other hand, when a signal c (multi-rate signal) of another transmission rate is input, the rise (fall) of the signal c may be different from the signal a. At this time, the clock recovery circuit 22 operates to cancel the deviation of the phase timing with the CLK based on the rising (falling) timing of the input signal c.

However, since the correction requires a finite amount of time, once a large deviation occurs, it takes a considerable amount of time to stabilize again, and a packet having a transmission rate capable of reproducing data is input. At times, there is a problem that data cannot be reproduced correctly. The present invention has been made to solve such a problem, and has as its object to provide a clock and data recovery circuit that operates stably even when a multi-rate signal is input, without largely changing a conventional configuration. I have.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, a clock and data recovery circuit according to the present invention has a possibility of disturbing a clock recovery operation required to recover a packet among packets included in an input signal. A packet selection circuit for eliminating a packet having a packet, a clock required for packet reproduction is reproduced based on a signal output from the packet selection circuit, and a signal output from the packet selection circuit is reproduced based on the reproduced clock. In this configuration, packets of a desired transmission rate are reproduced and output as received data.

In addition, a packet selection circuit is provided for eliminating a packet included in the input signal which may disturb the clock recovery operation required for packet recovery, and based on a signal output from the packet selection circuit, A clock required for packet reproduction is reproduced, and a packet having a desired transmission rate included in an input signal is reproduced based on the reproduced clock and output as received data.

Further, in the packet selection circuit, a sine-wave signal is output in synchronization with a specific pattern included in each packet in the input signal, and a gate signal is generated in accordance with an integrated output obtained by integrating the sine-wave signal. In this case, the output of the input signal is controlled based on the gate signal.

In the gate signal generation circuit, an output start signal is output when the integrated output from the integration circuit reaches a predetermined threshold, and a period in which the end of the packet is included according to the output start signal The output stop signal is output only by counting the time, the output of the gate signal is started according to the output start signal, and the output of the gate signal is stopped according to the output stop signal.

In addition, a packet selection circuit is provided for eliminating packets which may disturb the clock recovery operation required for packet recovery among the packets included in the input signal, and based on the signal output from the packet selection circuit, The clock required for the reproduction of the
A packet having a desired transmission rate included in the signal output from the packet selection circuit is reproduced and output based on the reproduced clock, and specific information detected from the packet based on the reproduced clock and data. On the basis of the packet selection circuit.

[0015] A packet selection circuit is provided for eliminating packets that may disturb the clock recovery operation required for packet recovery among the packets included in the input signal, and based on the signal output from the packet selection circuit, The clock required for the reproduction of the
A packet having a desired transmission rate included in the input signal is reproduced based on the reproduced clock and output as received data, and a packet is generated based on specific information detected from the packet based on the reproduced clock and data. This is to control the selection circuit.

In the packet selection circuit, a sine-wave signal is output in synchronization with a specific pattern included in each packet in the input signal, and an integrated output obtained by integrating the sine-wave signal is controlled by a logical termination circuit. A gate signal is generated according to a signal, and output control of an input signal is performed based on the gate signal.

In the gate signal generation circuit, an output start signal is output when the integrated output from the integration circuit reaches a predetermined threshold, and the output of the gate signal is started according to the output start signal. The output of the gate signal is stopped in response to a control signal from the logical termination circuit.

Further, in the logical termination circuit, information indicating the packet length is detected from the packet as specific information, and time is counted up to a predetermined period including the end of the packet in accordance with the packet length. A control signal is output in response. In the logical termination circuit, information indicating the end of a packet is detected as specific information, and a control signal is output in response to the detection of the information.

Further, in the packet selection circuit, only packets having a desired transmission rate are selected and output based on a specific pattern arranged at the head of the packet.

[0020]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a clock and data recovery circuit according to a first embodiment of the present invention.
The same or equivalent parts as those described above (see FIG. 10) are denoted by the same reference numerals. In the present embodiment, a packet selection circuit is provided before the clock recovery circuit and the data recovery circuit as in the related art to select a packet having a desired transmission rate, and a packet having a transmission rate that may disturb the clock recovery operation. Is to be eliminated.

In the clock and data recovery circuit 2a of FIG. 2, reference numeral 21 denotes a data recovery circuit, and reference numeral 22 denotes a clock recovery circuit, which have the same functions as those described above (see FIG. 10). Reference numeral 5a denotes a packet selection circuit, which is provided between the input terminal 1 to which the input signal Din generated from the signal from the transmission device in the main device is input and the branch point 23.

Here, of the packets included in the input signal Din input from the input terminal 1, only those packets that may disrupt the clock recovery operation of the clock recovery circuit 22 are selected and eliminated. Then, the remaining packets are sent to the clock recovery circuit 22 and the data recovery circuit 21 at the subsequent stage.
Supplied to

Next, a configuration example of the packet selection circuit 5a will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration example of the packet selection circuit. In FIG.
Reference numeral 1 designates a signal 55 (that is, an input signal Din) input to the packet selection circuit, which is located at the beginning of a packet having a desired transmission rate to be received among a plurality of transmission rate signals used in the data transmission system. This is a tuning circuit that outputs a sinusoidal signal 56 in response to a PR (preamble) signal included therein.

An integration circuit 52 integrates and outputs a sine wave signal 56 from the tuning circuit 51, and 53a denotes an integration circuit 5
This is a gate signal generation circuit for generating a gate signal 58 based on the integrated output 57 from the second circuit. Reference numeral 54 denotes a SW (switch) circuit that controls whether or not the signal 55, that is, the input signal Din, can be output based on the gate signal 58 from the gate signal generation circuit 53a.

Further, the gate signal generation circuit 53a is
The configuration is as shown in FIG. FIG. 3 is a block diagram showing a configuration example of the gate signal generation circuit. 531 compares the integration output 57 from the integration circuit 52 with a predetermined threshold,
A level determination circuit 533 that outputs an output start signal 534 based on the determination result is a timer circuit that starts timing according to the output start signal 534 from the level determination circuit 531 and outputs an output stop signal 535 after a predetermined period has elapsed. is there.

A gate signal 532 starts outputting the gate signal 58 based on an output start signal 534 from the level determination circuit 531 and stops outputting the gate signal 58 based on an output stop signal 535 from the timer circuit 533. 58 is an ON / OFF circuit for controlling ON / OFF of 58.

Next, the operation of the clock and data recovery circuit according to the first embodiment will be described with reference to FIG. FIG. 4 is a timing chart showing the lumbar part of the operation of the clock and data recovery circuit according to the first embodiment. Generally, a PR (preamble) signal for synchronizing with the packet is arranged at the head of the packet.

This PR signal is usually composed of a 1/0 repetition signal, and by referring to this,
The transmission speed (bit rate) of the packet is detected. In the packet selection circuit 5a, the PR signal included in the input signal Din is detected by the tuning circuit 51. That is, at time T1, when a PR signal having a desired transmission rate used in the data transmission system is input to the tuning circuit 51, the tuning circuit 51 reacts strongly to this to generate an internal sinusoidal signal.

Then, of the internal sinusoidal signals,
A signal exceeding a predetermined threshold th1 is a sinusoidal signal 5.
6 is output. The sinusoidal signal 56 is integrated by the integration circuit 52, and the integration output 57 is input to the gate signal generation circuit 53a. This integrated output 57 is output to the level determination circuit 531 of the gate signal generation circuit 53a.
It is compared with a predetermined threshold value th2.

Here, when the integrated output 57 exceeds the threshold value th2 (time T2), an output start signal 534 is output from the level determination circuit 531. ON / O accordingly
The FF circuit 532 is turned ON, and the ON / OFF circuit 5
32, a gate signal 58 for instructing to open the SW circuit 54 is output, and the input signal Din
The output of (signal 55) is started.

Thus, after time T2, the gate signal 5
Until 8 is stopped, the input signal Din is branched and output to the clock recovery circuit 22 and the data recovery circuit 21 via the branch point 23. Then, the clock Cout reproduced by the clock reproduction circuit 22 is output from the output terminal 4, data is reproduced in the data reproduction circuit 21 based on the clock Cout, and the received data Dout is output from the output terminal 3.

The timer circuit 533 is activated in response to the output start signal 534, and starts counting the period length from the time T2 to the end of the packet. And
After a lapse of a predetermined period from time T2, that is, after the end of the packet has been received (time T3), the timer circuit 533 times out and the output stop signal 535 is output, and the output is stopped.
The / OFF circuit 532 is turned off.

As a result, the output of the gate signal 58 is stopped, the SW circuit 54 is turned off, and the output of the input signal Din is stopped, so that the clock recovery operation in the clock recovery circuit 22 is stopped.

On the other hand, at time T1, when a PR signal not having the desired transmission rate used in the data transmission system is input to the tuning circuit 51, the response of the tuning circuit 51 is small, and the sinusoidal signal 56 does not grow large. . Therefore, the effective integration output 57 is not output from the integration circuit 52, and the gate signal 58 remains stopped.

As a result, the input signal Din is no longer output to the clock recovery circuit 22, and as a result, it is determined that the packet has a transmission rate that may disturb the clock recovery operation, and the packet is eliminated, and the clock recovery is performed. No action is taken.

As described above, in the present embodiment, the packet selection circuit 5a is provided before the clock recovery circuit 22 and the data recovery circuit 21 as in the prior art, to select a packet having a desired transmission speed, and to perform the clock recovery operation. This eliminates packets with a transmission rate that may disturb the transmission. As a result, in the clock recovery circuit 22, a clock recovery operation is performed based on the signal after the disturbance packet has been selectively eliminated from the input signal Din, and the input signal Din is a multi-rate signal having a speed different from the normal single transmission speed. , A stable clock recovery operation is guaranteed.

Further, since the packet selection circuit 5a is provided at a stage preceding the clock recovery circuit 22 and the data recovery circuit 21, the configuration after the branch point 23 is the same as that of the conventional configuration, that is, the clock and data recovery circuit 2 (see FIG. 10). It is equivalent, and the conventional configuration can be used as it is without changing the circuit configuration.

In the packet selecting circuit 5a, an integrating circuit 52 is provided between the tuning circuit 51 and the gate signal generating circuit 53a.
6, the gate signal 58 is not output unless the sinusoidal signal from the tuning circuit 51 is continuously output for a period determined by the time constant. Even when a pattern similar to a PR signal having a desired transmission rate is present in a packet having an undesired transmission rate present in an input signal Din, a packet having a length of several bytes is generally smaller than a PR signal having a length of several bytes. , Its length is short enough in probability. Therefore, a PR signal having a desired transmission rate can be detected stably.

In the gate signal generation circuit 53a, a timer circuit 533 is provided which is started in response to the judgment output from the level judgment circuit 531. The timer circuit 533 measures the period length including the end of the packet. The output stop signal 535 is output according to the condition (1), so that a valid packet can be reliably output to the end of the packet with a relatively simple circuit configuration.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a clock and data recovery circuit according to a second embodiment of the present invention, and the same or equivalent parts as those described above (see FIG. 1) are denoted by the same reference numerals. In the first embodiment, the case has been described in which the packet selection circuit 5a is provided before the clock recovery circuit 22 and the data recovery circuit 21, but as shown in this embodiment, the clock recovery circuit 2
The packet selection circuit 5a may be provided only in the stage preceding the packet selection circuit 2.

That is, in FIG. 5, the packet selection circuit 5a is provided between the clock recovery circuit 22 and the branch point 23 in the clock and data recovery circuit 2b. In this case, the input signal Din is branched at the branch point 23 and supplied to the packet selection circuit 5a and the data reproduction circuit 21. As a result, the signal after the disturbance packet has been sorted out by the packet selection circuit 5a is supplied only to the clock recovery circuit 22.

Thus, according to the second embodiment,
Since the input signal Din is input to the data reproducing circuit 21 as it is without being processed, the data reproducing circuit 21 guarantees the same data reproducing operation as the conventional one. The configurations of the packet selection circuit 5a and the gate signal generation circuit 53a are the same as those of the first embodiment, and the configurations of FIGS. 2 and 3 described above are used.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration example of a clock and data recovery circuit according to the third embodiment of the present invention. The same reference numerals are given to the same or equivalent parts as described above (see FIGS. 1 and 5). I have. In the first and second embodiments, a timer circuit 533 is provided in the gate signal generation circuit 53a of the packet selection circuit 5a.
Gate signal 58 indicating a period including the end of the packet
Has been described.

However, as shown in this embodiment, a logical terminating circuit 6 is provided instead of the timer circuit 533, and specific information indicating the last position included in the packet is detected from the received data Dout, and the specific information is detected. Of the gate signal 58, that is, the period including the end of the packet may be determined on the basis of the information of the above.

In the figure, a packet selection circuit 5b having no timer circuit 533 is provided instead of the above-described packet selection circuit 5a. In addition, the logical termination circuit 6
Are disposed after the clock recovery circuit 22 and the data recovery circuit 21.

The logical terminating circuit 6 uses the clock Cout reproduced by the clock reproducing circuit 22 and the received data Dout reproduced by the data reproducing circuit 21 to specify specific information contained in a packet having a desired transmission speed. Is detected. Then, the reception timing of the tail of the packet is logically generated based on the information, and the control signal 61 indicating the tail position of the packet is generated by the packet selection circuit 5b.
Is output to

FIG. 7 is a block diagram showing another configuration example of the packet selection circuit, and shows the packet selection circuit 5b used in the present embodiment. Here, a gate signal generation circuit 53b is provided instead of the above-described gate signal generation circuit 53a, and a control signal 61 from the logical termination circuit 6 is input to the gate signal generation circuit 53b.

FIG. 8 is a block diagram showing another configuration example of the gate signal generation circuit, and shows the gate signal generation circuit 53b used in the present embodiment. here,
The timer circuit 533 described above is removed, and the control signal 6 from the logical termination circuit 6 is used instead of the output stop signal 535.
1 is input to the ON / OFF circuit 532.

Next, the operation of the clock and data recovery circuit according to the third embodiment will be described. The operation timing is almost the same as that of the first embodiment, and the operation will be described below with reference to the timing chart of FIG.

In the same manner as described above, if it is determined at time T2 that the packet has a desired transmission rate based on the PR signal of the packet input from time T1, the subsequent input signal Din is used for packet selection. Circuit 5b
From the clock recovery circuit 22 and the data recovery circuit 21. Thus, the clock recovery circuit 22 outputs the clock Cout and the data recovery circuit 21 outputs the received data Dout.

In the logical termination circuit 6, this clock Cou
Based on the received data Dout, specific information for determining the end timing of the packet is detected.
For example, when information indicating a packet length is used as the specific information, a predetermined period length including the end of the packet is measured by a timer or the like based on the information, and the control signal 61 is output according to the time-up. I just need. When information indicating the end of a packet is used as the specific information, for example, the control signal 61 may be output in response to the detection of the information.

Thus, at time T3, the control signal 61 is output from the logical termination circuit 6 to the packet selection circuit 5b. Gate signal generation circuit 53b of packet selection circuit 5b
Then, the ON / OFF circuit 532 is
Is turned off, and the output of the gate signal 58 is stopped.

As a result, the output of the gate signal 58 is stopped, the SW circuit 54 is turned off, and the output of the input signal Din is stopped, so that the clock recovery operation in the clock recovery circuit 22 is stopped.

On the other hand, at time T1, when a PR signal not having the desired transmission speed used in the data transmission system is input to the tuning circuit 51, the sine wave signal 56 from the tuning circuit 51 The amplitude is small enough,
Do not exceed the threshold. Therefore, the effective integration output 57 is not output from the integration circuit 52, and the gate signal 58 remains stopped.

As a result, the input signal Din is no longer output to the clock recovery circuit 22, and as a result, it is determined that the packet has a transmission speed that may disturb the clock recovery operation, and the packet is eliminated, and the clock recovery is performed. No action is taken.

As described above, in the present embodiment, the logical terminating circuit 6 is provided instead of the timer circuit 533, the specific information indicating the end of the packet included in the received data Dout is detected, and the specific information is detected. Since the stop timing of the gate signal 58, that is, the period including the end of the packet is determined based on the information, the SW circuit 54
, The timing for stopping the output of the input signal Din can be determined more accurately.

Further, similarly to the first embodiment, since the packet selection circuit 5b is provided in the preceding stage of the clock recovery circuit 22 and the data recovery circuit 21, the configuration after the branch point 23 is the conventional configuration, that is, the clock and data. Reproduction circuit 2
(See FIG. 10), and the conventional configuration can be used as it is without changing the circuit configuration.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing a clock and data recovery circuit according to a fourth embodiment of the present invention, and the same or equivalent parts as those described above (see FIG. 6) are denoted by the same reference numerals. In the third embodiment, the case has been described where the packet selection circuit 5b is provided before the clock recovery circuit 22 and the data recovery circuit 21, but as shown in this embodiment, the clock recovery circuit 2
The packet selection circuit 5b may be provided only in the stage preceding the second.

That is, in FIG. 9, the packet selection circuit 5b is provided between the branch point 23 in the clock and data recovery circuit 2d and the clock recovery circuit 22. In this case, the input signal Din is branched at the branch point 23 and is supplied to the packet selection circuit 5b and the data reproduction circuit 21. As a result, the signal after the disturbance packet has been sorted out by the packet selection circuit 5b is supplied only to the clock recovery circuit 22.

Therefore, according to the present embodiment, since the input signal Din is input to the data reproduction circuit 21 as it is without being processed, the data reproduction circuit 21
In this case, a data reproduction operation equivalent to the conventional one is guaranteed.
Note that the packet selection circuit 5b and the gate signal generation circuit 5
The configuration of 3b is the same as that of the third embodiment, and the configurations of FIG. 7 and FIG. 8 described above are used.

[0061]

As described above, according to the present invention, there is a possibility that a packet selection circuit is provided before a clock recovery circuit and a data recovery circuit to select a packet having a desired transmission rate and disturb the clock recovery operation. A packet having a certain transmission rate is eliminated, and a clock and data are reproduced based on a signal after these packets are eliminated. Also, a packet selection circuit is provided only in the preceding stage of the clock recovery circuit to select a packet having a desired transmission rate, to eliminate a packet having a transmission rate that may disturb the clock recovery operation, and to eliminate these packets. The reproduction of the clock is performed based on the signal of. Therefore, a packet of a specific transmission rate can be extracted from a multi-rate signal and accurate clock and data reproduction can be performed by adding a packet selection circuit without a major design change from the conventional clock and data recovery circuit. And a clock and data recovery circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock and data recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a packet selection circuit.

FIG. 3 is a block diagram illustrating a configuration example of a gate signal generation circuit.

FIG. 4 is a timing chart showing the operation of the clock and data recovery circuit according to the first embodiment;

FIG. 5 is a block diagram showing a clock and data recovery circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration example of a clock and data recovery circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating another configuration example of the packet selection circuit.

FIG. 8 is a block diagram showing another configuration example of the gate signal generation circuit.

FIG. 9 is a block diagram illustrating a clock and data recovery circuit according to a fourth embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a configuration example of a conventional clock and data recovery circuit.

FIG. 11 is a timing chart showing an operation example of a conventional clock and data recovery circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2a, 2b ... Clock and data recovery circuit, 21 ... Data recovery circuit, 22 ... Clock recovery circuit,
3: Data output terminal, 4: Clock output terminal, 5a, 5
b: packet selection circuit, 51 tuning circuit, 52: integration circuit, 53a, 53b: gate signal generation circuit, 531: level determination circuit, 532: ON / OFF circuit, 533: timer circuit, 54: SW (switch) circuit, Din: input signal, Dout: received data, Cout: clock,
6 ... Logic termination circuit, 61 ... Control circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomoyuki Kurihara 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Takuya Nakamura 3-192, Nishishinjuku, Shinjuku-ku, Tokyo No. Nippon Telegraph and Telephone Corporation (72) Inventor Koichi Fujisaki 20-1 Sakuragaokacho, Shibuya-ku, Tokyo Inside NTT Electronics Corporation (72) Inventor Yuichi Sato 20th Sakuragaoka-cho, Shibuya-ku, Tokyo No. 1 NTT Electronics Corporation (72) Inventor Hiroaki Mitsuyasu 20-1 Sakuragaoka-cho, Shibuya-ku, Tokyo F-term in NTT Electronics Corporation 5K030 GA05 HB15 KA21 MA04 MB11 5K047 AA01 AA15 BB15 GG11 HH53 LL09 MM32 MM35 9A001 BB04 CC05 CC07 GG05 GG12 KK37

Claims (11)

[Claims] 1. A clock required for reproducing a packet having a desired transmission rate is reproduced from a multi-rate input signal including packets having different transmission rates, and a packet having a desired transmission rate is reproduced from the input signal based on the clock. A clock and data recovery circuit that outputs a packet that excludes a packet that may disturb the clock recovery operation required to recover the packet, out of the packets included in the input signal, and a packet output from the packet selection circuit. A clock recovery circuit for recovering a clock required for packet recovery based on the recovered signal; and a clock output circuit provided in parallel with the clock recovery circuit, which outputs a signal output from the packet selection circuit based on the clock recovered by the clock recovery circuit. Reproduces the included packet of the desired transmission rate and outputs it as received data A clock and data recovery circuit, comprising: 2. A clock required for reproducing a packet having a desired transmission rate is reproduced from a multi-rate input signal including packets having different transmission rates, and a packet having a desired transmission rate is reproduced from the input signal based on the clock. A clock and data recovery circuit that outputs a packet that excludes a packet that may disturb the clock recovery operation required to recover the packet, out of the packets included in the input signal, and a packet output from the packet selection circuit. A clock recovery circuit for recovering a clock required for packet recovery based on the received signal; and a clock recovery circuit provided in parallel with the packet selection circuit for the input signal, based on the clock recovered by the clock recovery circuit.
A clock recovery circuit that reproduces a packet having a desired transmission rate included in an input signal and outputs the data as reception data. 3. The clock and data recovery circuit according to claim 1, wherein the packet selection circuit outputs a sine wave signal in synchronization with a specific pattern included in each packet in the input signal; An integrating circuit that integrates a sine-wave signal from the tuning circuit; a gate signal generating circuit that generates a gate signal in accordance with an integrated output from the integrating circuit; and an input based on the gate signal from the gate signal generating circuit. A clock and data recovery circuit, comprising: a switch for controlling signal output. 4. A clock and data recovery circuit according to claim 3, wherein the gate signal generation circuit outputs a start signal when the integrated output from the integration circuit reaches a predetermined threshold value. According to the output start signal from the level determination circuit, a timer circuit that measures time during a period including the end of the packet and outputs an output stop signal according to the end of the time measurement, and an output start signal from the level determination circuit. And an ON / OFF circuit for starting the output of the gate signal in response to the signal and stopping the output of the gate signal in response to the output stop signal from the timer circuit. 5. A clock required for reproducing a packet having a desired transmission rate is reproduced from a multi-rate input signal including packets having different transmission rates, and a packet having a desired transmission rate is reproduced from the input signal based on the clock. A clock and data recovery circuit that outputs a packet that excludes a packet that may disturb the clock recovery operation required to recover the packet, out of the packets included in the input signal, and a packet output from the packet selection circuit. A clock recovery circuit for recovering a clock required for packet recovery based on the recovered signal; and a clock output circuit provided in parallel with the clock recovery circuit, which outputs a signal output from the packet selection circuit based on the clock recovered by the clock recovery circuit. Data reproduction to reproduce and output the packets of the desired transmission rate included A logic termination circuit that detects specific information from the packet based on the clock recovered by the clock recovery circuit and the data recovered by the data recovery circuit, and controls the packet selection circuit based on the specific information. And a clock and data recovery circuit. 6. A clock required for reproducing a packet having a desired transmission rate is reproduced from a multi-rate input signal including packets having different transmission rates, and a packet having a desired transmission rate is reproduced from the input signal based on the clock. A clock and data recovery circuit that outputs a packet that excludes a packet that may disturb the clock recovery operation required to recover the packet, out of the packets included in the input signal, and a packet output from the packet selection circuit. A clock recovery circuit for recovering a clock required for packet recovery based on the received signal; and a clock recovery circuit provided in parallel with the packet selection circuit for the input signal, based on the clock recovered by the clock recovery circuit.
A data recovery circuit that reproduces and outputs a packet having a desired transmission rate included in the input signal; and detects specific information from the packet based on the clock reproduced by the clock reproduction circuit and the data reproduced by the data reproduction circuit. And a logic termination circuit for controlling the packet selection circuit based on the specific information. 7. The clock and data recovery circuit according to claim 5, wherein the packet selection circuit tunes to a specific pattern included in each packet in the input signal and outputs a sine wave signal. An integration circuit for integrating a sine-wave signal from the tuning circuit; a gate signal generation circuit for generating a gate signal in accordance with an integration output from the integration circuit and a control signal from a logical termination circuit; And a switch for controlling output of an input signal based on a gate signal from the circuit. 8. The clock and data recovery circuit according to claim 7, wherein the gate signal generation circuit outputs a start signal when the integrated output from the integration circuit reaches a predetermined threshold. An ON / OFF circuit which starts output of a gate signal in response to an output start signal from a level determination circuit and stops output of the gate signal in response to a control signal from a logical termination circuit. And a data reproducing circuit. 9. The clock and data recovery circuit according to claim 9, wherein the logical terminating circuit detects information indicating the packet length from the packet as specific information, and determines the end of the packet according to the packet length. A clock and data recovery circuit which outputs a control signal in accordance with the end of the time measurement. 10. The clock and data recovery circuit according to claim 10, wherein the logical termination circuit detects information indicating the end of the packet as specific information, and outputs a control signal according to the detection of the information. A clock and data recovery circuit characterized by the above-mentioned. 11. The clock and data recovery circuit according to claim 1, wherein the packet selection circuit is configured to determine a packet based on a specific pattern arranged at the head of the packet.
A clock and data recovery circuit for selecting and outputting only packets having a desired transmission rate.