JPS61127243A - Bit phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To allow a simple circuit to select a re-timing clock without error even when the number of multi-phase clocks is increased by using a trailing edge of a clock where a change point of an input signal does not exists during the active period of the clock among multi-phase clocks to apply re-timing to the input signal. CONSTITUTION:The change point of an input signal 101 is detected by a change point detection circuit 115 comprising a delay circuit 102 and an exclusive OR circuit 104. The output of the change point detection circuit 115 is ANDed with the clock selected by a selector 107 by an AND gate 105. Since the data input of a flip-flop 109 passes through two delay circuits 102, 103, a period before and after the re-timing point WC-DB (WC is a clock pulse width and DB is a delay time of the delay circuit 102), DA+DB is confirmed, and in taking the WC-DB and the DA+DB larger than the data setup time and the data hold time of the flip-flop respectively, the input data is received without error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a bit phase synchronized circuit, and more particularly, to a bit phase synchronized circuit for receiving digital signals transmitted between a plurality of devices operated by clocks supplied from the same clock source. The present invention relates to a circuit for receiving a signal having delay and phase jitter in a transmission medium without error in a device for transmitting data.

[Background of the invention]

Bit phase synchronization is required when transmitting digital signals between multiple devices. A bit phase synchronization circuit is a circuit that receives an input signal having delay and jitter caused in a transmission path without error. 6 Normal bit phase synchronization is realized by a phase locked loop (pLL) and an elastic memory. That is.

Bit phase synchronization is achieved by regenerating clocks and clocks from an input signal using a PLL, writing input data to the elastic memory using the clocks, and reading data using the device clock.

However, in a state where a plurality of devices operate with clocks supplied from the same clock source (frequency synchronization is achieved), it is possible to simplify the bit phase synchronization circuit. Conventionally, such a simplified bit phase synchronization circuit has a means for converting the reference clock into multiple phases,
means for detecting a changing point of an input signal, recognizing whether the input changing point is within a time slot determined by the multiphase clock, and selecting a clock that can correctly retime the input signal. A circuit to be used is known (Japanese Patent Laid-Open No. 54-51339).

In general, in order to increase the amount of jitter allowed in the input, the standard clock is multiphased to generate N multiphase clocks, and an appropriate lock is selected from among these to retime the input signal. It is necessary to take a large N.

However, the conventional circuit has the drawback that when N is increased, the circuit that determines in which time slot the change point of the input signal is located and selects a clock that can retime the input signal without error becomes complicated. was.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit phase synchronization circuit that can select a retiming clock without causing an error with a simple circuit even when the number of multiphase clocks is increased.

[Summary of the invention]

The present invention realizes a bit phase synchronization circuit that can achieve the above object by retiming the input signal using the rear edge of the clock in which the change point of the input signal does not exist in the active period of the clock in the multiphase clock. It is something to do.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a block diagram of an embodiment of a bit phase synchronization circuit according to the present invention in the case where a four-phase clock is used. The four-phase clock φ shown in FIG. 2 is generated from the device clock 112 by the clock generator 113. ~φ
, is created. One of these four-phase clocks is selected by the selector 107, and the input signal is timed by its falling edge. D-type flip-flop 109 is a flip-flop that operates on the rising edge of the clock input. Input signal 101 is connected to delay circuit 102 and exclusive
) A change point is detected by a change point detection circuit 115 comprising an OR circuit 104. That is, when the input signal changes, a pulse having a pulse width equal to the delay time DA of the delay circuit 102 is output from the change point detection circuit 115.

The output of the change point detection circuit 115 is ANDed with the clock selected by the selector 107 by an AND gate 105-. Therefore, if a change point of the input signal exists within the active period of the currently selected clock (the period of 'H' in FIG. 2), a pulse is generated at the output of the AND gate 105, and the counter 106 count up. Reference numeral 106 is a 2-bit counter, and its output controls selector 107. Therefore, by counting up counter 106, another clock can be selected. As can be seen from the above description, a clock is finally selected in which there is no change point in the input signal during its active period. FIG. 3 shows the relationship between the selected clock and input data. It is guaranteed that the input data does not change during the period when the clock is l Hl . The data input of the flip-flop 109 is connected to two delay circuits 102 and 1.
03, so as shown in Figure 3, the values before and after the retiming point W, -D, (Wl, , is the clock pulse width, DS is the delay time of the delay circuit 102), and DA+D are determined. Therefore, input data can be received without error if W, -D, DA+D are set longer than the data set up time and data hold time of the flip-flop, respectively. A flip-flop 110 retimes the output of the flip-flop 109 using a fixed device clock and supplies an output 111 to the device.

[Effects of the Invention] □ As explained above, according to the present invention, a clock that can retiming input data without error can be easily selected using a lock selection circuit, and a bit phase synchronization circuit can be economically implemented. It can be realized.

[Brief explanation of drawings]

Figure @1 is a block diagram of a bit phase synchronization circuit according to the present invention, Figure @2 is a diagram showing the internal clock waveform of Figure 1, and Figure 3 is a diagram showing the relationship between the clock and input data. 101... Data input, 102, 103... Delay circuit, 104... Exclusive OR circuit, 105... AND circuit. 106...Counter, 107...Selector, 108
...Inverter, 109.110...Flip-flop, 1[2...Device clock input, 113...Multiphase tarot\r, ) Figure NZ Figure LK

Claims (1)

[Claims] 1. In a receiver that receives a digital data signal using a clock supplied from a clock source, means for generating N multiphase clocks that divide one period of the data transmission frequency by N (N≦3); means for detecting a changing point of the digital data signal; means for selecting one of the N multiphase clocks; and determining whether the changing point of the input digital data signal is within an active period of the selected clock. If the change point is within the active period of the selected clock, another clock is selected, and if the change point is not within the active period of the selected clock, the selected clock is selected. A bit phase synchronization circuit characterized in that it retimes an input signal using a trailing edge of a clock.