JPS63173434A - Bit phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To decrease the circuit scale as the entire bit phase synchronizing circuit by applying phase discrimination of a timing signal to a data signal and applying the control of the timing phase selection by one phase deciding/ control circuit. CONSTITUTION:A phase detecting/control circuit 6A consists of a J-K flip-flop 12-1. An identificating circuit 7A consists of a D flip-flop and a data signal S11 is read at the leading point of a timing signal S15 and a recovered data signal S17 is outputted at a recovered data output terminal 8. One J-K flip-flop 12-1 applies the decision of the propriety of the timing phase and the switching control of the timing phase. Thus, it is not required, different from a conventional circuit, to use two signals with different phase generated from the reference clock signal S3, thereby differentiating clock differentiation circuits 16-1, 16-2.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses a digital data signal with jitter and a reference clock signal as input to generate a timing signal that matches each bit of the data signal. This invention relates to a bit phase synchronized circuit.

[Conventional technology]

FIG. 4 is a circuit diagram showing a conventional bit phase synchronization circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 54-51709. In the figure, l is a data signal input terminal, 2 is a reference clock signal input terminal, and 3 is a A data change point detection circuit detects a change point of a data signal; 4 is a timing generation circuit that generates a timing signal with a different phase from an input reference clock signal; A selection circuit that selects and outputs one
7 is an identification circuit that retimes an input data signal according to a selected timing signal; 8 is a reproduced data signal output terminal that outputs the retimed data signal; 9 is a timing output terminal that outputs a selected timing pulse; 11-2 is an inverter gate, 14 is a selection circuit 5
15 is a phase control circuit that controls the operation of the selection circuit 5 based on the determination result of the phase determination circuit 14; 16-1;
16-2 is a clock differentiation circuit for differentiating a reference clock signal, 17-1, 17-2 is an AND gate, and 18 is a set-reset flip-flop.

Next, the operation will be explained using the timing chart shown in FIG.

It is assumed that input data S1 such as a non-return-to-zero signal (hereinafter referred to as an NRZ signal) having jitter is input from a data signal input terminal 1, and a reference clock signal S3 is input from a reference clock signal input terminal 2.

The input data S1 is sent to the data change point detection circuit 3.
Here, a change point detection pulse S2 having a constant time width ΔT is generated from the logic change point. On the other hand, the input reference clock signal S3 is transferred to the inverter gate 11-
By inverting by 2 and displacing the phase by 180°, two timing signals as clock signals with different phases of 180° are obtained, and each of the timing signals is inverted by the differentiating circuit 16-1.
-2, the falling point is detected and the two timing signals S4,
35 is generated and input to the selection circuit 5.

The selection circuit 5 outputs the timing signal S5 when the logic of the control signal S8 input from the phase control circuit 15 to the selection control terminal Y is "1", and outputs the timing pulse path scale data signal S1 when the logic is "0". The data signal 310 is retimed by the identification circuit 7 consisting of a flip-flop at the rising edge of the selected timing signal S5, and is outputted to the reproduced data signal output terminal 8 after being shaped to remove waveform distortion such as jitter.

At this time, if the timing signal S5 is selected, for example, the rising edge of the timing signal S5 is located near the logic change point of the input data signal, so an identification error will occur due to signal jitter, but the timing signal When S4 is selected, retiming is performed while the logic level of the data signal S1 is stable, so it can be said that this timing signal S4 is an appropriate timing that does not cause identification errors.

The phase determination circuit 14 determines whether the rising phase of the timing signal is
It is determined whether or not the data signal is at a logic change point by using the change point detection pulse S2 and the timing signal 34. This is to be identified by performing a logical product with S5. In the AND gate 17-1 in FIG. 4, the timing signal S4 has an appropriate phase that does not temporally overlap with the data change point detection pulse, so the output S6 of the AND gate 17-1 is at zero level. On the other hand, since the timing signal S5 has a phase that overlaps with the change point detection pulse S2, the AND gate 1
A pulse S7 is generated on the 7-2 output side. Antogame-I-
The outputs of 17-1 and 17-2 are respectively connected to the set terminal and reset terminal of the set/reset flip-flop 18 constituting the phase control circuit 15, so the Q terminal of the flip-flop 18 is connected in the initial state as described above. Output is “1”
The timing signal S5 was selected by the selection circuit 5 because the Q terminal output of the set-reset flip-flop 18 is reset to "0" at the moment a pulse is generated in the output of the AND gate 17-2. selects the proper timing signal S4 instead of the timing signal S5, so that a normal identification timing phase is established.

In the above circuit, the data change point detection circuit 3 is configured as shown in FIG. 6, for example, and the delay line 10-2, 10-
3 gives a data change point detection pulse width ΔT, which is normally set to 172 or less of the clock period T and is used with the two timing signals S4. Both S5 and change point detection pulse S2
Make sure there is no overlap. In other words, and gate 1
The outputs of 7-1 and 17-2 are prevented from becoming "1" at the same time. Further, 13-2 is an exclusive or gate.

As described above, the configuration of the conventional embodiment includes as many phase determination circuits as the number of timing signals generated by the timing generation circuit 4, that is, AND gates 17-1, 17-2, .・・・
. . . and the differentiation circuit 16-L for the reference clock signal S3.
16-2. ······is necessary.

[Problem that the invention seeks to solve]

Since the conventional bit phase synchronization circuit is configured as described above, it is possible to perform phase determination as many times as there are timing signals generated from the reference clock signal S3.
-2, .゜16-2. . . . is required, which causes problems such as a relatively large circuit scale and high cost.

The present invention has been made to solve the above-mentioned problems, and aims to provide a bit phase synchronization circuit that can reduce the circuit scale and reduce the cost.

(Means for Solving the Problems) The bit phase synchronization circuit according to the present invention generates a change point detection pulse of a constant time width at a change point of a data signal inputted by a data change point detection circuit, and on the other hand, Two timing signals with different phases are generated from the timing generation circuit based on the reference clock signal, one of these timing signals is selected by the selection circuit, and the phase determination/control circuit selects the timing signal within the above-mentioned time width of the above-mentioned change point detection pulse. Detecting an inappropriate timing signal having a timing of , generating a control signal, causing the selection circuit to select an appropriate timing signal from among the timing signals based on the control signal, and based on the selected timing signal, The data signal is configured to be retimed by an identification circuit.

[Effect]

The phase determination/control circuit in this invention has a flip-flop at J-, inputs a change point detection pulse to both terminals of the flip-flop, and sends a timing signal selected by the selection circuit to T. By inputting the signal to the Q terminal and using the Q terminal output as a control signal for the selection circuit, when the selected timing signal rises in the interval where the change point detection pulse is "1", that is, when the timing phase is incorrect, ,
At J-, the Q terminal output of the flip-flop is inverted and the other timing signal is selected, and when the selected timing signal rises in the section where the change point detection pulse is "0",
In other words, when the timing phase is appropriate, the Q terminal output logic is maintained and the timing signal acts so as not to switch.The circuit size is reduced by performing phase judgment and timing phase switching control using one flip-flop in this J-. Reduce.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 3A is a data change point detection circuit, which consists of a delay line 10-1 and an exclusive OR gate 13-1. 4A is a timing generation circuit, which has an inverter (11-1) and whose phase is 180 degrees from the reference clock signal.
° Generate two different timing signals. 6A is a phase determination/control circuit, which is composed of a flip-flop 12-1 at J-. 7A is an identification circuit consisting of a D flip-flop. Note that other circuit parts that are the same as those shown in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

The operation of the embodiment of the present invention will be explained below using the timing chart shown in FIG. As in the conventional example, a data signal with jitter is input to data signal input terminal 1,
A reference clock signal is input to the reference clock signal input terminal 2.

The data signal 311 is input to a D flip-flop serving as the identification circuit 7A.

Further, in the data change point detection circuit 3A, the data signal 31
1 is delayed by Δ by a delay line 10-1, and the delayed signal and the original data signal Sll are input to the exclusive OR gate 13-1. As a result, the exclusive OR game 1-13-1 outputs a changing point detection pulse S12 having a width of Δt from the changing point of the data signal Sll. The width of Δ needs to be determined in consideration of the magnitude of jitter, etc., and is usually set to 172 or less of the data period T.

The timing generation circuit 4A consists of an inverter gate 11-1, and generates two timing signals S13.1 with a phase difference of 180 degrees based on a reference clock signal. S14 is generated and output. The timing signal 313 is in phase with the reference clock signal, whereas the timing signal 314 is 180 degrees out of phase.

The selection circuit 5 selects one of the two timing signals 313°S14 according to the logic state of the output S16 to the phase determination/control circuit 6 inputted to the control terminal Y, and outputs it as the timing signal 315 to the output terminal. 9. That is, if the logic state of the output 316 is "0", the timing signal 313 is output, and if it is "'1", the timing signal 314 is output.

The phase detection/control circuit 6A has a flip-flop 1 connected to J-.
It consists of 2-1. The flip-flop 12-1 to J- is
By inputting the change point detection pulse S12 to both terminals of J, and inputting the timing signal S15 selected by the selection circuit 5 to the T terminal, the change point detection pulse 312 is
1", when the toggle operation is enabled and the timing signal S15 rises in that state, the logic state of the Q terminal output 316 changes, and on the other hand, the change point detection pulse is "0". If the timing signal 315 rises during a period, that is, J, when the inputs to both terminals are "0", the logic state of the Q terminal output 316 does not change. Inputting the terminal output 316 to the control signal terminal Y of the selection circuit 5,
The phase of the timing signal 315 input to the identification circuit 7A is controlled.

That is, the identification circuit 7A is composed of a D flip-flop, and detects the data signal 3 at the rising point of the timing signal 315.
11 is read and outputted to the reproduction data output terminal 8 as a reproduction data signal S17.

When the identification circuit 7A retimes the data signal (A) with jitter, it avoids the changing points of the data signal Sll and retimes the timing signal S15 in an interval where the logic level is stable.
The rising point of must be located. Therefore, during the period when the change point detection pulse is "1", that is, during the period when it is inappropriate to retiming the data signal Sll,
J-, the flip-flop 12-1 is enabled for toggle operation, and if an incorrect timing signal S13 is selected, as in the period up to point 2 in Figure 2, for example, the phase is determined to be appropriate at the 0 rising point. is determined, and the logic of the Q terminal output S16 of the flip-flop 12-1 is inverted at J-, and from the point ■ in FIG. Signal S14 is output from selection circuit 5 instead. Therefore, Fig. 2 0
After the point, J of flip-flop 12-1 is connected to J-.
, the selected timing signal S15 rises when the logic of the change point detection pulse 312 input to both terminals is "0", so the flip-flop 12-1 is connected to J-.
The logic state of the Q terminal output S16 does not change, and stable timing is maintained.

In this way, the 12 to 11 flip-flops in J- are used to determine whether or not the timing phase is appropriate and to control the switching of the timing phase.

Further, this phase determination/control circuit 6A is configured as described above.
Since the flip-flop 12-1 operates at the rising edge of the timing signal S15, the clock differentiating circuit 16-1. There is no need to differentiate using -2.

In the above embodiment, a circuit as shown in FIG. 1 is shown as the data change point detection circuit 3A, but any circuit can be used as long as it can generate a pulse with a constant time width corresponding to a data signal change point. For example, if a configuration as shown in FIG. 6 is adopted, changing point detection pulses can be obtained before and after the data signal changing point. In addition, the delay line 10-1
Instead, logic gates, mono-multiby-breaks, etc. may be used.

Furthermore, although a circuit as shown in FIG. 1 is shown as the timing generation circuit 4A, two clocks having different phases from the reference clock signal are used.
Any circuit that can generate the timing signals 313 and 314 may be used, such as a circuit format that inputs a clock having a frequency higher than the data transmission speed as a reference clock signal and outputs a timing signal of a different phase from a ring counter or the like. It is also possible to use a circuit format that uses a delay line to output timing signals with different phases.

Furthermore, although the case of the NRZ signal has been exemplified as the input data signal, the present invention can also be applied to digital data signals such as return-to-zero signals.

Furthermore, the D flip-flop used in the identification circuit 7A may be of any type as long as it performs the same operation.
As shown in Figure 3, connect a flip-flop to J, and connect one to each terminal.
By operating it as a flip-flop that supplies data inputs with a phase difference of 80°, the number of logic elements used in this bit phase synchronization circuit can be reduced.

[Effects of the Invention] As described above, according to the present invention, since the phase determination of the timing signal with respect to the data signal and the control of timing phase selection are performed by one phase determination/control circuit, bit phase synchronization is achieved. The circuit size of the entire circuit can be reduced, which has the effect of reducing the mounting area, power consumption, and cost.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a bit phase synchronization circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram of signals in each part of the circuit shown in FIG. 1, and FIG. 3 is a circuit showing an embodiment of an identification circuit. 4 is a block connection diagram showing a conventional bit phase synchronization circuit, FIG. 5 is a timing diagram of signals of various parts of the circuit in FIG. 4, and FIG. 6 is a connection diagram showing a data change point detection circuit. 3A is a data change point detection circuit, 4A is a timing generation circuit, 5 is a selection circuit, 6A is a phase determination/control circuit, 7A is an identification circuit, 311 is a data signal, 313 and S14 are timing signals, and S16 is a control signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 51311: Selector g i' 314 ji j zo ↑: Crown 1 Positive beam 9 Imin 7A Kuyu 11''''5 12-2 Figure 6

Claims (2)

[Claims] (1) A data change point detection circuit that generates a change point detection pulse with a constant time width at the change point of the input data signal, and two timings with different phases from the reference clock signal in a system different from the above data signal. A timing generation circuit that generates a signal, a selection circuit that selects one of these two timing signals, and a selection circuit that detects an inappropriate timing signal that has a timing within the time width of the change point detection pulse. a phase determination/control circuit that generates a control signal and causes the selection circuit to select an appropriate timing signal from among the timing signals based on the control signal;
and an identification circuit for retiming the data signal using the selected appropriate timing signal. (2) Claims characterized in that the phase determination/control circuit is a J-K flip-flop that captures the change point detection pulse into the J terminal and the K terminal, and captures the timing signal output by the selection circuit into the T terminal. The bit phase synchronization circuit according to item 1.