JPH02250535A - Bit phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To attain the bit synchronization in a short time by using three clock signals having the phases shifted from each other to latch the input signals and deciding based on the levels of the output signals whether a different clock signal should be selected or the present clock signal should be continuously used. CONSTITUTION:A selector 4 selects one of four clock signals having the phases shifted by 1/4 cycle from each other and this selected clock signal is delayed by a certain delay time tau and 2tau. Then the input data signals are latched by three flip-flops 1-3 by means of three clock signals having the phases shifted from each other by the delay time tau. The latch outputs of the flip-flops are fetched by a detecting circuit 10. If even one of those three latch outputs has a different level, the selector 4 is controlled to select another clock signal shifted by 1/4 cycle. When the coincidence is secured among those three output levels, the selector 4 is controlled so that the clock selected presently is continuously used. As a result, the bit synchronization is attained in a short time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bit phase synchronization circuit in a communication path device of an exchange, and particularly to a bit synchronization circuit that can achieve bit synchronization in a short time and is resistant to external noise. be.

[Conventional technology]

2. Description of the Related Art Conventionally, general communication devices, including communication path devices of exchanges, have been provided with bit phase synchronization circuits in order to align the phases of input signals. The bit phase synchronization circuit adjusts the phase of each input signal and achieves synchronization by reproducing signals input with different phases according to the same clock.

FIG. 4 is a configuration diagram of a conventional bit phase synchronization circuit.
FIG. 5 is a time chart of the clock signal and data fetching operation in FIG. 4.

In FIG. 4, 64 is a buffer row for setting delay time;
65 is a changeover switch, and 61, 62, and 63 are flip-flops.

Input signals are input from each stage of the buffer row 64 to the changeover switch 65. This changeover switch 65 switches and connects input signals using a control signal CTL. 3
The flip-flops 61, 62, and 63 have respective data input terminals connected in parallel to the output side of the changeover switch 65, and when the clock signal input to each clock terminal C rises, each data input terminal is connected in parallel to the output side of the changeover switch 65. By latching the input data, it outputs the captured values Ai, A, , A, respectively from the Q terminal. As shown in FIG. 5, the clock signals of the flip-flops 62 and 63 are shifted in phase from the preceding flip-flops 61 and 62 by a delay time τ due to delay circuits 66 and 67. Also, the value A2 taken in by the flip-flop 62 becomes an output signal at the same time.

A1 in Figure 4. The outputs of A, , A, are input to a comparison circuit (not shown) and compared there to determine whether or not bit phase synchronization is achieved. That is, when the input signal is input, the captured values A, , , in FIG.
Input A into the comparison circuit.

By comparing these Ayu and A,
, it is determined that the clock signal and the input signal are phase synchronized, and the captured value A2 is output as a reproduced output signal. In the case of A≠A, the changeover switch 65 is switched using the control signal CTL, and the input signal is sequentially delayed by a fixed value, and this is repeated until A=A3 (for example, P roe, 'I
international Z urichSem
inar on Digital Commun
cations'1986°C4,1-C4,4).

[Problem to be solved by the invention]

In the conventional example shown in FIG. 4 described above, it is necessary to change the delay value by 1 for the input signal until the input values of the flip-flops 61 and 63 become A1=A. The circuit configuration becomes complicated, and the delay time of the input signal must be set so that A, = A, each time.

As a result, there is a problem in that it takes time to stabilize the phase difference after it is detected.

The object of the present invention is to solve these conventional problems and provide a bit phase synchronization circuit that can achieve bit synchronization between a clock and an input signal in a short time, is resistant to external noise, and can be realized with a simple circuit configuration. Our goal is to provide the following.

[Means for Solving the Problems] In order to achieve the above object, the bit phase circuit of the present invention has the following features:
In a bit phase synchronization circuit that synchronizes the bits of an input signal on the receiving side of the synchronization signal transmission circuit, first, second, and second circuits delay a clock signal with an occupation rate of 50% by 1/4 period, 1/2 period, and 374 periods, respectively. inputting the clock signal and the output signals of the first, second, and third delay circuits to a third delay circuit, and selecting one of the clock signals by a selection signal input to a control terminal; A selector that outputs a selected clock signal, fourth and fifth delay circuits that delay the output signal of the selector by a certain delay time, and the output signal of the selector and each output of the fourth and fifth delay circuits. first, second, and third flip-flops each inputting a signal to a clock terminal and latching a data signal input to the input terminal at a rising or falling time of each of the signals; The respective outputs of the second and third flip-flops are input, and if even one of the high and low levels of the input three signals does not match, a selection signal is sent to the control terminal of the selector, and the preset The present invention is characterized in that it has a detection circuit that selects the next clock signal after the currently selected clock signal according to the order in which the clock signals are currently selected, and if they all match, continues to select the currently selected clock signal.

[For production]

In the present invention, one clock signal is selected by a selector from four clock signals whose phases are shifted by 1/4 period, and that clock signal is further delayed by τ and 2τ. An input data signal is latched into three flip-flops using a clock signal, and the latch output is taken into a detection circuit. The clock signals whose cycles are shifted are selected, and if all of their levels match, the currently selected clock is continued to be selected by controlling the selector. As a result, bit synchronization can be achieved in a short time, it is not affected by external noise, and a bit phase synchronization circuit can be realized with a simple circuit configuration.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a basic configuration diagram of a bit phase synchronization circuit showing one embodiment of the present invention.

In Figure 1, 1, 2.3 are flip-flops, 4 is a selector, 5, 6.7 are delay circuits, 8°9 is also a delay circuit,
10 is a detection circuit.

The clock signal is supplied with a waveform of 50% occupancy from a clock generator (not shown), and is output from D1 to D1 of the selector 4.
It is input to the D4 terminal. That is, the clock signal is transmitted to T/4. T/2,
The signal is delayed by 3T/4 and input to the input terminals D1 to D4 of the selector together with the original clock signal. In other words, four clock signals having the same period and sequentially shifted in phase by 1/4 are input to the selector 4. In the selector 4, the selection signal input to the control terminal S causes the selector 4 to
Select one of the clock signals to output terminal Q.
Output to. The clock signal output from the selector 4 is delayed by the delay circuit 8 and further delayed by the delay circuit 9. By taking out the respective outputs of these delay circuits 8, 9 and selector 4, three clock signals each having a phase shift of τ can be generated. These three clock signals are input to each input terminal of three flip-flops 1, 2, and 3, respectively. That is, the clock signal from the output terminal Q of the selector 4 is sent to the clock terminal C of the flip-flop 1, the clock signal output from the delay circuit 8 is sent to the clock terminal C of the flip-flop 2, and the clock signal output from the delay circuit 9 is sent to the clock terminal C of the flip-flop 1. The signals are respectively input to the clock terminals C of the pull-up 3.

On the other hand, input signals are simultaneously input to these three flip-flops 1, 2.3, but these input signals are latched by clock signals whose phases are shifted by τ. 3
The outputs of the flip-flops 1.degree.2.3 are all transferred to the detection circuit 10, where their respective output levels are compared. As a result of the comparison, if they match, it is determined that synchronization is achieved, and a control signal is output to the control terminal S of the selector 4 so as to continue selecting the currently selected clock signal. On the other hand, if they do not match, it is determined that synchronization is not achieved, and the clock signal next to the currently selected clock signal is selected in the order preset to the control terminal S of the selector 4. The selection signal is output as follows. In this way, by sending out the output of the flip-flop 2 when synchronization is achieved as the output signal of the bit phase synchronization circuit, data synchronized with the clock signal on the receiving side can be accurately reproduced.

Figure 2 is a specific configuration diagram of Figure 1, and the third
The figure is a time chart showing the operation.

In FIG. 2, the delay time τ is set to T/4. Further, the detection circuit 's10 is composed of an exclusive OR gate 11, a delay circuit 12, an AND gate 1-13, and a counter 14.

Data 21 to 24 shown in FIG. 3 are clock signals input to the selector 4, SL and 82 are selection signals output from the detection circuit 10 to the terminal S of the selector 4, and data 27 to 29 are input to the flip-flops, respectively. 1, 2.3, and data 33 to 35 are the outputs of the exclusive OR gate 11 in the detection circuit 10 and the delay circuit 1.
2 and the output of AND gate 13.

A clock signal (data 21) and a clock signal (data 2) obtained by delaying this clock signal by delay circuits 5, 6.
2, 23, 24) are the input terminals D of the selector 4, respectively.
1 to D4. The selector 4 selects one clock signal from the four clock signals by a combination of two selection signals input to the two control terminals SL and S2, and outputs it from the output terminal Q (data 27).

FIG. 6 is a table diagram of combinations of selection signals in FIG. 2 and clock signals selected thereby.

When a low level selection signal is input to Sl and S2, data 21 (that is, the clock signal input to Dl) is selected, and when a high level is input to Sl and a low level is input to S2, data 22 (that is, the clock signal input to D2) is selected.
is selected, and when a low level is input to SL and a high level is input to S2, data 23 (that is, the clock signal input to D3) is selected. When a high level is input to SL and S2, data 24 (that is, the clock signal input to D4) is selected. clock signal) is selected.

As shown in FIG. 3, at time ti, SL (data 25
) is L and S2 (data 26) is also L, so data 21 is selected according to Figure 6 (output is data 27)
The s data 27 is delayed by T/4 in the delay circuit 8 to become data 28, and further delayed by T/4 in the delay circuit 9 to become data 29. The input signals are data 27 and data 2 in three flip-flops 1 and 2°3, respectively.
8. The rising time of data 29 (that is, each time t
□.

ta, ja).

FIG. 7 is a diagram of a truth table of inputs and outputs of the exclusive OR gate of FIG.

Data 30, 31 and 32 (that is, flip-flop 1
and 2 and 3), the exclusive OR
The output of gate 11 becomes data 33. That is, if even one of the three inputs has a different level, the output will be at H level, and only when all the inputs are at the same level, the output will be at L level.

In the case of Figure 3, depending on the waveform timing of the input signal,
The output of flip-flop 1 becomes L, and the outputs of flip-flops 2 and 3 become H. As shown in FIG. 7, the truth value of the exclusive OR gate 11 is such that when even one of the three inputs has a different level, the output becomes H level. On the other hand, in the detection circuit 10, the delay circuit 12
9 is further delayed by T/4 to create data 34. As a result, at time t, the output (data 33) of the exclusive OR gate 11 becomes H level.

Further, the counter 14 is a binary counter, and counts each rising edge of the clock input to the input terminal, and outputs the count in binary. In FIG. 3, data 35 rises at time t4, and SL (data 25) changes to H level. Therefore, as is clear from FIG. 6, the output of the selector 4 (data 27) is changed to the following order, and the data 22
is selected (data 28), and in the same way, time t
S,j! +t, when the three flip-flops 1, 2.3 latch data, the input is at L level, so the outputs of the three flip-flops 1, 2.3 (data 30, 31, 32) are all L, and the levels are all the same, so the output of exclusive OR gate 11 (data 33)
becomes L level at time t7. When the data 33 becomes L, the output of the delay circuit 12 cannot be input to the clock terminal C of the counter 14, so from now on, Sl, S2
Stable without changing the state of By extracting the output (data 31) of the flip-flop 2 as an output signal, the input signal can be reproduced with a large margin against jitter.

In the embodiment, for convenience of explanation, the case where the input signal is an alternating pattern of 1°0 has been described, but any pattern can be detected in the same way after a certain amount of time.
It is possible to play.

In this way, in the present invention, one clock signal is selected by the selector from four clock signals whose phases are shifted by 174 cycles, and the clock signal is further delayed by τ and 2τ, and the phase shift is adjusted by τ. If the input signals are latched with three clock signals and their output levels are different, the selector is controlled to
A clock signal shifted by four periods is selected, and if all the latched results match, the selector is controlled to continue selecting the currently selected clock signal.

〔Effect of the invention〕

As explained above, according to the present invention, the phase-shifted three
latch the input signals with two clock signals and select another clock signal depending on the level of those output signals, or
Since it is determined whether to continue the current clock signal, bit synchronization can be achieved in a short time, it is robust against external noise, and it can be realized with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of a bit phase synchronization circuit showing an embodiment of the present invention, FIG. 2 is a specific configuration diagram in FIG. 1, FIG. 3 is an operation time chart in FIG. 2, and FIG. The figure is a configuration diagram of a conventional bit phase synchronization circuit, FIG. 5 is an operation time chart in FIG. 4, and FIG. 6 is a table diagram of selection signal combinations and selection clock signals in FIG. 2.
FIG. 7 is a truth value table diagram of the exclusive ○R gate in FIG. 1.2, 3, 61, 62, 63: flip-flop, 4
: Selector, 5, 6, 7, 8, 966.67: Delay circuit, 10: Detection circuit, 11: Exclusive OR gate, 13:
AND gate, 14: counter, 64: buffer, 6S
: Changeover switch, CTLH control signal, S, SL, S2
: Control terminal, D1-D4: Input terminal, Q: 8-power terminal, C
: Clock terminal. Figure (spontaneous)

Claims (1)

[Claims] (1) In a bit phase synchronization circuit that synchronizes bits of an input signal on the receiving side of a synchronization signal transmission circuit, a clock signal with an occupation rate of 50% is delayed by 1/4 period, 1/2 period, and 3/4 period, respectively. first, second, and third delay circuits;
The above clock signal and the output signals of the first, second, and third delay circuits are input, one of the above clock signals is selected by a selection signal input to a control terminal, and the selected clock signal is output. a selector, fourth and fifth delay circuits that delay the output signal of the selector by a certain delay time τ, and input the output signal of the selector and each output signal of the fourth and fifth delay circuits to a clock terminal, respectively. first, second and third flip-flops that latch the data signal input to the input terminal at the rising or falling point of each signal; Each output is input, and if even one of the high and low levels of the three input signals does not match, a selection signal is sent to the control terminal of the selector, and the currently selected clock is selected according to the preset order. 1. A bit phase synchronization circuit comprising: a detection circuit that selects the next clock signal of the signals, and if they all match, continues to select the currently selected clock signal.