JP2982138B2 - Bit phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit phase synchronizing circuit in a communication channel device of an exchange, and particularly does not require adjustment.
The present invention also relates to a bit phase synchronization circuit having a simple configuration.

[0002]

2. Description of the Related Art Conventionally, not only a communication path device of an exchange but also a general communication device is provided with a bit phase synchronization circuit for aligning the phase of a signal inputted on the receiving side of a synchronous signal transmission circuit. Have been. The bit phase synchronization circuit adjusts the phase of each input signal by synchronizing the signals input at different phases with each other by reproducing them in synchronization with the same clock. As a conventional bit phase synchronization circuit, for example, there is a bit phase synchronization circuit described in Japanese Patent Application No. 1-72174 and drawings. FIG. 4 is a configuration diagram of a conventional bit phase synchronization circuit according to the above-mentioned prior application. 4, 101, 102, and 103 are flip-flops, 104 is a selector, 105, 106,
107 is a delay circuit, 108 and 109 are also delay circuits, 110
Is a detection circuit. In addition, flip-flops 101 to 1
03, D is an input signal supply terminal, C is a clock input terminal, Q is a signal output terminal, D1 in the selector.
D is a clock signal input terminal, S is a control terminal to which a control input is supplied, and Q is a clock output terminal. A clock signal with an occupancy of 50% is generated by the clock generator.
(Not shown), and D1 to D4 of the selector 104.
The signals are input to the D4 terminal via delay circuits 105 to 107, respectively. That is, the clock signal is supplied to the delay circuit 105
107, the signals are delayed by T / 4, T / 2, and 3T / 4, respectively, and input to the D2 to D4 terminals, and a non-delayed clock signal is input to the D1 terminal. Four clock signals whose phases are shifted by ４ are input to the selector 104. The selector 104 selects one of the four clock signals input to the D1 to D4 terminals according to the selection signal input to the control terminal S, and outputs this from the output terminal Q.
The output clock signal is delayed by τ in the delay circuit 108 and further delayed by τ in the next delay circuit 109. The clock from the Q terminal of the selector 104, the clock from the delay circuit 108, and another delay circuit 109
Are three clock signals whose phases are shifted by τ, respectively, and these three clock signals are sent to the clock terminals C of the flip-flops 101, 102, and 103, respectively.

[0003] On the other hand, the exchange signal passing through the channel device is:
At the same time, the signals are input to the three flip-flops 101 to 103, and these input signals are latched by the flip-flops 101 to 103, respectively, with clock signals having phases shifted by τ. Three flip-flops 101 to 103
Are sent from the output terminal Q to the detection circuit 110. The detection circuit 110 compares the input output levels. If the output levels match, it is determined that synchronization has been established, and the control terminal S of the selector 104 outputs the currently selected clock signal to the control terminal S. A control signal is output so as to continue selection. On the other hand, if they do not match, it is determined that synchronization has not been achieved, and a clock signal next to the currently selected clock signal is selected in a preset order at the control terminal S of the selector 104. Output the selection signal to That is, the phase synchronization is adjusted by comparing the amplitude of the input signal at the time of 0 to 2τ. In this way, by outputting the output from the output terminal Q of the flip-flop 102 at the time of synchronization as the output signal of the bit phase synchronization circuit, data synchronized with the clock signal on the receiving side can be accurately reproduced. can do.

[0004]

However, in the above-described example of FIG.
Since it is necessary to generate various kinds of clock signals, it is troublesome, and the configuration is large, which is not suitable for LSI. When the frequency of the clock signal changes, it is necessary to adjust the phases of the four types of clock signals again. Further, there is a problem that the configuration is complicated due to the use of the selector. SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional problems and eliminate the need to generate a plurality of different types of clock signals. It is to provide a suitable bit phase synchronization circuit.

[0005]

In order to achieve the above object, a bit phase synchronization circuit according to the present invention is provided in a bit phase synchronization circuit for performing bit synchronization of an input signal on a receiving side of a synchronous signal transmission circuit. An inversion circuit that inverts and outputs a signal only when instructed by a control signal (FIG. 1)
5), a first clock signal which is an output signal of the inverting circuit, a second clock signal obtained by delaying the first clock signal by a predetermined delay time τ ₁ , and a second clock signal. A delayed clock generation circuit (6) for outputting a third clock signal delayed by a delay time (τ ₂ −τ ₁ ), and a clock signal for each one of the first, second and third clock signals And first, second and third flip-flops (1, 2, 3) for latching the input data signal at the rising or falling edge of each clock signal, respectively. At a point in time when the data is latched in the flip-flop with a delay, the respective outputs of the first, second and third flip-flops (1, 2, 3) are input, and the respective levels are compared. Invert if any By sending a control signal to the roadside (5), first, by inverting the second and third clock signals,
In addition, as a result of the comparison, if all match, the inversion circuit (5)
And a detection circuit (4) for continuously outputting the current first, second, and third clock signals as they are.

[0006]

According to the present invention, the input on the receiver side synchronous signal transmission circuit de - for taking bit synchronization of data signals, three of the input clock signal and tau ₁ and tau ₂ only clock signal delayed flip And the input data signal is latched in each flip-flop by these clock signals. Each level is compared by sending those latch outputs to a detection circuit. When even one of the levels is different, only the clock signal is inverted,
Each clock signal can be shifted in phase by １ ／ cycle. That is, when the levels are different, it is determined that the rising or falling changing point of the input data is near the changing point of the clock signal. By inverting the input clock signal, the input data can be accurately re-timed thereafter. As a result, a bit phase locked loop circuit having a simple structure can be created, without generating four types of clock signals having phases different from each other by 1/4 cycle as in the related art, and changing the frequency of the clock signal. It can be used as it is.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a basic configuration diagram of a bit phase synchronization circuit showing one embodiment of the present invention. In FIG. 1, 1, 2,
3 is a flip-flop, 4 is a detection circuit, 5 is an inversion circuit,
6 is a delay clock generation circuit. D of the flip-flops 1 to 3 is an input signal supply terminal, C is a clock signal input terminal, and Q is a signal output terminal. FIG.
As compared with the conventional circuit configuration shown in FIG. 5, five delay circuits are not required, and one delay clock generation circuit 6 is provided instead. Further, a selector is not required, and one inverting circuit 5 is provided instead. The clock signal input to the inversion circuit 5 is selected by the control signal from the detection circuit 4 to be output as it is or to be inverted and output. The clock signal output from the inversion circuit 5 is input to the delay clock generation circuit 6. In the delayed clock generation circuit 6, a signal having the same phase as the input clock signal,
A signal delayed by τ ₁ and a signal delayed by τ ₂ (> τ ₁ ) are generated and input to clock terminals C of flip-flops 1 to 3, respectively. On the other hand, the input signal is simultaneously input to the D terminals of the three flip-flops 1 to 3,
Each input signal is latched in each of the flip-flops 1 to 3 by three types of clock signals. Outputs from the output terminals Q of the flip-flops 1 to 3 are sent to the detection circuit 4 respectively. The detection circuit 4 compares the respective output levels. When all the comparison results match, it is determined that synchronization has been achieved, and the current output clock signal is continuously output to the inversion circuit 5. Thus, the control signal is transmitted. If even one of them does not match, it is determined that synchronization has not been achieved, and a control signal is sent to the inverting circuit 5 so as to invert the currently output clock signal and output it. In this way, the output from the Q terminal of the flip-flop 2 at the time of synchronization is transmitted as the output signal of the bit phase synchronization circuit, so that the data synchronized with the clock signal on the receiving side is accurately reproduced. be able to.

FIG. 2 is a diagram showing an example of a specific configuration in FIG. 1, and FIG. 3 is a time chart showing the operation of FIG. In FIG. 2, the delay times τ ₁ = τ, τ ₂ = 2τ are set. The inverting circuit 5 comprises a flip-flop 13 and an exclusive OR gate 12, the delay clock generating circuit 6 comprises delay circuits 7 and 8, and the detecting circuit 4 comprises an exclusive OR gate 9 and a delay circuit. 10 and an AND gate 11. The clock signal b is output from the inversion circuit 5
Is input to one of the exclusive OR gates 12, and the output of the flip-flop 13 is input to the other. As shown in FIG. 3, the clock signal (data b) rises at t ₁ and t ₄ , while the output of the flip-flop 13 (data 1)
Holds the low (L) level until t _8,
The output (data c) of the exclusive OR gate 12 is the same signal as the clock signal (data b). Output signal (data
The data c) is delayed by .tau. In the delay circuit 7 to become an output (data d) of the delay circuit 7, and further delayed by .tau. In the delay circuit 8 to become an output (data e) (data in FIG. 3). −ta c, d,
e). On the other hand, the input signal (de - data a), as shown in a of FIG. 3, the rise at the time of t _3, but entered as waveform falls at time t _5, the three flip-flops 1-3 Are latched in synchronization with the rising edges of data c, d and e, respectively. Since the latched signal level is the level of the input signal (data a) from t ₁ to t _{2 in each} of the flip-flops 1 to 3, all the outputs from the Q terminals are at the L level. The comparison process in the detection circuit 4 will be described in detail with reference to FIG.

FIG. 5 is a diagram of the truth table of the input and output of the exclusive OR gate in FIG. As shown in FIG. 5, data f, g, and h, that is, flip-flops 1,
The exclusive OR is determined by the combination of the output signals 2 and 3.
The output of the gate 9 is data i. That is, if at least one of the three inputs has a different level, the output is at a high (H) level, and the output is at an L level only when all are at the same level. As described above, during the period from t _{1 to} t ₂ , which is the latch interval of the three flip-flops 1, ₂ , 3, all the outputs of the flip-flops 1 to 3 are at the L level. Becomes L level. In this case, the detection circuit 4
Since the output (data k) of the AND gate 11 at L is at L level, the flip-flop 13 is not set, so that the data 1 does not change and the clock signal (data Data c) is still the input clock signal (data b). In FIG. 3, time t
₄ Until ~t _7, the input signal - there is a change point of (de data a), the actual flip-flop 2 clock signal - if latched on (de data d), be latched at time t ₆ to become, the input signal (de from time t ₃ to t ₅ -
The data '1' of data a) cannot be read. De In between time t ₄ of t ₉ - data f is H level, de - data g, h
Is at the L level, and the data i is at the H level.

[0010] In the detection circuit 4, and is delayed by τ 'in the delay circuit 10, the time t _8, which was to some extent taken a margin from the time t ₇
Is determined. That is, at time t _8, since the data i, the data j are both H level, the output of AND gate 11 (data k) becomes H level. Further, the inversion circuit 5
Since the data k in the clock terminal C of the flip-flop 13 is inputted, the data 1 at time t ₈ is H from L level
Change to a level. When the data 1 goes to the H level, the exclusive OR gate 12 inverts the level of the input clock signal (data b) and outputs it as data c (see k, l, c in FIG. 3). That is, at time t ₈
Thereafter, the inverting circuit 5 inverts the input clock signal (data b) and outputs it as data c. Therefore, after t ₈ , the input signal (data a) is obtained as a result of latching of the flip-flops 1 to 3, that is, between the latch synchronization times t ₉ and t ₁₀ and between t ₁₁ and t _12.
Becomes the same for all three, and the clock signal having the same phase as that of the current clock is continuously supplied to the flip-flops 1 to 3. Further, since there is no change point of the input signal (data a) in this latch section, the input signal can be reproduced stably and the data g is output as the output signal. In the embodiment, the first, second and third clocks are used.
The case where there is a time difference of τ between
As described above, the first clock signal depends on the setting conditions of the delay circuit.
Second clock signal delayed by a delay time τ ₁ from the signal
And a further delay time (τ ₂ −τ ₁ ) (where τ ₂
> Τ ₁ ) to generate a third clock signal
Can be In this case, τ ₂ and τ ₁ are arbitrary values
(Where τ ₂ > τ ₁ ).

As described above, in this embodiment, the clock signal is delayed by τ ₁ and τ ₂ , and the input signal is latched by three types of clock signals having a phase shift including the clock signal which is not delayed. ,as a result,
If the output levels are different, the clock signal is inverted and the input signals are latched, and as a result,
If the output levels match, control is performed so that the input signal is latched with the current clock signal as it is. As a result, the number of delay circuits can be reduced as compared with the conventional bit phase synchronization circuit shown in FIG. 4, and a selector is not required, thereby simplifying the configuration. Further, even if the clock frequency changes, it can be used continuously as it is.

[0012]

As described above, according to the present invention,
In addition to a flip-flop that latches an input signal and a circuit that detects a level, a bit phase synchronization circuit can be configured simply by providing an inverting circuit and a circuit that generates three clock signals that are out of phase. , An LSI can be achieved. Further, unlike the related art, there is no need to create various types of clock signals having slightly different phases, and even if the frequency of the clock signal changes, there is no need to adjust the phase again, and the clock signal is used continuously. Therefore, the operation efficiency is extremely high.

[0013]

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a bit phase synchronization circuit showing one embodiment of the present invention.

FIG. 2 is a diagram showing an example of a specific configuration in FIG.

FIG. 3 is an operation time chart in FIG. 2;

FIG. 4 is a configuration diagram of a conventional bit phase synchronization circuit.

FIG. 5 is a diagram of a truth table of an exclusive OR gate in FIG. 2;

[Explanation of symbols]

 1 to 3, 13, 101 to 103 Flip-flop 7, 8, 10, 105 to 109 Delay circuit 4 Detection circuit 5 Inversion circuit 6 Delay clock generation circuit 9, 12 Exclusive OR gate 11 AND gate 104 Selector S Control terminal Q output terminal Q inverted output terminal D, D1 to D4 input terminal C clock terminal

Claims (1)

(57) [Claims] 1. A bit phase synchronization circuit for performing bit synchronization of an input signal on a receiving side of a synchronous signal transmission circuit, wherein the inversion circuit inverts and outputs an input clock signal only when instructed by a control signal. A first clock signal which is an output signal of the inverting circuit, a second clock signal obtained by delaying the first clock signal by a predetermined delay time τ ₁ , and a further delay time ( τ ₂ −τ ₁ ) (where (τ ₂ > τ ₁ )), and a delayed clock generating circuit for outputting a third clock signal, and one of the first, second and third clock signals. First, second, and third flip-flops for inputting the input data signals as clock signals and latching the input data signals at the rising or falling of each clock signal, respectively, When the signal is latched to the flip-flop with the latest delay, the respective outputs of the first, second and third flip-flops are input and the respective levels are compared. For example, a control signal is sent to the inverting circuit, and the first, second and third control signals are transmitted.
And a detection circuit for inverting the clock signal of the second clock signal and outputting the current first, second, and third clock signals to the inverting circuit if the result of the comparison indicates that they all match. A bit phase synchronization circuit characterized by the following.