JP2769530B2 - Bit phase synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit phase synchronization circuit, and more particularly, to a bit phase synchronization circuit in a communication path device of an exchange.

[Conventional technology]

Conventionally, this type of bit phase synchronization circuit has been synchronized by adjusting the phase of each input signal in order to reproduce signals input at different phases in accordance with the same clock.

FIG. 4 is a configuration diagram showing a conventional example of a bit phase synchronization circuit,
FIG. 5 is a view for explaining the data capture with respect to the clock signal CLK ₀ in the conventional example of FIG. 4.

The input signal D _in is input to the switch SW from each stage of the buffer array BUF provided for setting the delay time. Changeover switch SW input signal D by a control signal S _C
perform _in switching connections. 3 flip-flops FF ₄ , FF
_5, FF ₆ is respective data input terminal D to the output side of the changeover switch SW is connected in parallel, the rise time of the clock signal CLK ₀ inputted to the clock terminal C, is input from the respective data input terminal D Data is latched,
The values are output from the Q terminal as captured values S ₁ , S ₂ , and S ₃ . Note that the clock signals CLK _{0 of} the flip-flops FF ₅ and FF ₆
Each phase from the preceding flip-flop FF ₄ and FF ₅ by a delay time τ by the delay circuit DL ₁ and DL ₂ are shifted. Further, uptake value S ₂ of the flip-flop FF ₅ is the output signal D _out at the same time.

Then, when the input signal D _in is input, the control circuit (not shown) compares the fetched values S ₁ and S ₃ , and when S ₁ = S ₃ , the input signal D _in and the clock signal CLK ₀ are of determining that the phase synchronization is established, it outputs an output signal D _out obtained by reproducing the uptake value S _2. For S ₁ ≠ S _3, control signal S _c switches the changeover switch SW gives a delay of each sequential constant value to the input signal D _in, so that repeating this until S ₁ = S _3.

(See Proc. International Zurich Seminar on Dig
Ital Communications, 1986, C4.1-C4.4) [Problem to be Solved by the Invention] In the above-described conventional example, the input signal D _in is obtained until the fetched values S ₁ = S ₃ of the flip-flops FF ₄ and FF ₆ are satisfied. , The configuration of the phase difference detection circuit and the configuration of the optimum delay value setting circuit become complicated, and each time, S ₁ = S ₃
Since the delay time of the input signal must be set so as to satisfy the following condition, it takes a long time from detection of the phase difference to stabilization.

An object of the present invention is to provide a bit phase synchronization circuit having a simple circuit configuration, which requires only a short time to stabilize.

[Means for solving the problem]

In the bit phase synchronization circuit according to the present invention, the first clock signal supply means having an occupancy of 50% is equal in cycle to the first clock signal, and is shifted in phase by 1/4 cycle. Means for supplying a second clock signal, a first clock signal to a data input terminal, the input signal to a clock terminal, and the first input signal when the signal level of the input signal rises or falls. A first flip-flop for latching the second clock signal, an inverter for inverting the second clock signal, and two states based on the high / low level of the latched first clock signal previously output from the first flip-flop. Each of them is set to correspond to one or the other of the two clock signals of the second clock signal and the clock signal output from the inverter, and is input to the selection control terminal. A selector for selecting one clock signal from the corresponding in has been the flip-flop the two clock signals inputted by the output level,
A second flip-flop for inputting the input signal to a data input terminal, inputting a clock signal output from the selector to a clock terminal, and latching the input signal when the clock signal rises or falls; and have.

The second embodiment is the same as the first embodiment, except that the second
Inputting the output signal of the flip-flop to a data input terminal and inputting the first clock signal to a clock terminal;
A third flip-flop for latching the input signal when the signal level of the clock signal rises or falls;

According to a third aspect of the present invention, the selection by the selector is permitted only when a setting permission signal is input from the outside in the first or second aspect, and when the setting permission signal is not input, the selection of the selector is changed. Has means to prohibit.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the data output terminal of the first flip-flop is provided on the data output terminal side, and the output data of the first flip-flop is supplied to the data input terminal. An input signal is input to a clock terminal, and during a period of n times (n is a positive integer) of the input signal input to the clock terminal, the signal input to the data input terminal does not change during the rising or falling period. Only a protection circuit for transmitting an input signal to a selection control terminal of the selector is provided.

[Action]

According to the first aspect, one clock signal is latched at the time of rising or falling of an input signal using two clock signals having an occupancy of 50% and a phase shifted by 1/4 cycle, and the other is latched according to the latch result. By selecting the clock signal or the inverted signal of the clock signal and latching the input signal with the selected clock signal, data synchronized with the clock on the receiving device side can be output.

According to a second aspect of the present invention, when the clock signal latched by the input signal is used as the clock of the receiving device, the output data is latched again by the clock signal to synchronize with the clock of the receiving device. Data can be output.

Claim 3 relates to Claim 1 or 2,
By using a setting permission signal from the outside, once a clock signal is selected, the clock signal is not allowed to be changed, thereby preventing the clock signal from being affected by noise or the like.

According to a fourth aspect of the present invention, in any one of the first to third aspects, a protection circuit is provided in front of an input terminal of a selector for a selection control signal to prevent a temporary fluctuation of an input signal when a clock signal is selected. Thus, it is possible to prevent a clock signal from being erroneously selected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Circuit diagram showing the structure of an embodiment of a bit phase synchronization circuit of Figure 1 according to the present invention, FIG. 2 (a), (b), respectively, the clock signal CLK ₁ and the input signal D _in and the data from the selector SEL FIG. 3 is a timing chart showing the operation of the present embodiment.

As shown in FIG. 3, the clock signal CLK ₂ with respect to the clock signal CLK ₁ is a clock signal of the receiver side cycle is delayed equally phase 1/4 period, both occupancy 50
%. Flip-flop FF ₁ is the clock signal CLK ₁ to the data input terminal D, also, the input signal D _in including timing information to the clock terminal C is inputted,
It latches the clock signal CLK ₁ which is input at the rising point and outputs the data 1. Protection circuit PRT is the data 1 to the data input terminal D, also the input signal D _in the clock terminal C are respectively input to latch data 1 at the fall of the input signal D _in, continuous latch result 2 The latch result is output as data 2 when the level is the same. The selector SEL has data 2 at its selection control terminal S,
Data input terminal D _0, the inverted signal and the clock signal CLK ₂ of the clock signal CLK ₂ of each of D ₁ through an inverter NOT is input, and the correspondence between the data 2 and data 3 shown previously in the following Table 1 Set and input data 2
Is output.

Wherein the input signal D _in the flip-flop FF ₂ is at its data input terminal D, also, the data 3 to the clock terminal C are input, latches the input signal D _in at the rise of the data 3 and outputs the data 4. Flip-flop FF ₃ is the data input terminal data 4 to D is inputted, it transmits the data 4 at the rise of the clock signal CLK ₁ which is input to the clock terminal C as the output signal D _out latches.

 Next, the operation of this embodiment will be described with reference to FIG.

At time t _1, the clock signal CLK ₁ of the latch result of the flip-flop FF ₁ at the rise of the input signal D _in (data 1) goes high (and H). Subsequently, the protection circuit PRT does not respond to the fall and the rise of the input signal D _in at the time t ₂ and t ₃ , and the H level at the time of the second fall of the input signal D _in at the time t ₄ Is latched and output as data 2. The data 2 is at the H level, and the selector SEL selects the clock signal ▼ on the data input terminal D ₀ according to the correspondence in Table 1 and outputs it as data 3. Therefore, the time t ₅ in the data 3
The rise of the (clock signal ▲ ▼), the input signal D _in at that time is latched, thereafter, the clock signal ▲
▼ input signal D _in each rising edge of the output is latched as data 4. Time t ₅ from the clock signal ▲
Clock signal CL at time t ₆ 1 cycle later than ▼
K ₁ is rising, the data 4 is latched by the flip-flop FF _3, thereafter, the output signal D _out in synchronization with the clock signal CLK ₁ of the receiving device side is transmitted.

If this embodiment has been described in claim 4 when dependent on claim 2, if, using the clock signal CLK ₂ as the receiving apparatus side clock signal, the flip-flop FF
Data ₃ may be used as it is as output signal D _out omitting ₃ (case 1). Furthermore, when using a setting permission signal, the protection circuit PRT or flip-flop FF a gate circuit provided before the _first clock terminal C, only the input signal D _in the protection circuit when the setting permission signal is inputted
It is clear that it suffices to input PRT or the flip-flop FF ₁ to the clock terminal C (the case of claim 3).

Thus, in either embodiment, as shown in FIG. 2 (a), the clock signal as the data 3 when the rise of the input signal D _in is in the period A of H level of the clock signal CLK ₁ ▲ ▼ select, whereas, as shown in FIG. 2 (b), the clock signal CLK as the data 3 when in period B of the low-level rise of the clock signal CLK ₁ of the input signal D _in (a L) since selecting _2, flip-flop FF ₂ can be latched on reliably select the input signal D _in the clock signal.

〔The invention's effect〕

As described above, the present invention latches one clock signal at the time of rising or falling of an input signal by using two clock signals which are shifted in phase by 1/4 cycle, and outputs the other clock signal based on the latch result. By selecting a signal or an inverted signal of the clock signal and latching the input signal with the selected clock signal, data in phase with the clock on the receiving device side can be output, until the configuration is simple and stable. This has the effect of providing a bit phase synchronization circuit that requires only a short time. Further, by providing the setting permission signal, the clock signal once set can be protected from the influence of noise or the like of the subsequent input signal, and by providing the protection circuit, the input signal temporarily when selecting the clock signal can be protected. There is an effect that a large margin is provided for the temporal fluctuation and erroneous selection of the clock signal can be prevented.

[Brief description of the drawings]

Circuit diagram showing the structure of an embodiment of a bit phase synchronization circuit of Figure 1 according to the present invention, FIG. 2 (a), (b), respectively, the clock signal CLK ₁ and the input signal D _in and the data from the selector SEL 3 is a timing chart showing the operation of the present embodiment, FIG. 4 is a configuration diagram showing a conventional example of a bit phase synchronization circuit, and FIG. 5 is a clock signal CL shown in FIG.
It is an explanatory view of data acquisition relative to K _0. FF ₁ , FF ₂ , FF ₃ ... flip-flop, PRT ... protection circuit,
SEL… Selector, NOT… Inverter, CLK ₁ , CLK ₂ ……
Clock signal, 1, 2, 3, 4 ...... data, D _in ...... input signal, D _out ...... output _{signal, D, D 0, D 1} ...... data input terminal,
Q: Data output terminal, C: Clock terminal, S: Selection control terminal.

Claims (4)

(57) [Claims] 1. A bit phase synchronization circuit for synchronizing a bit of an input signal on a receiving side of a synchronous signal transmission circuit, comprising: a first clock signal supply means having an occupancy of 50%; Means for supplying a second clock signal having the same synchronization as that of the second clock signal and having a phase shifted by 1/4 cycle, and a first clock signal is input to a data input terminal, and the input signal is input to a clock terminal. A first flip-flop for latching an input first clock signal when a signal level rises or falls, an inverter for inverting a second clock signal, and a latch previously output from the first flip-flop One of the two clock signals of the second clock signal and the clock signal output from the inverter. A selector for selecting one corresponding clock signal from the two clock signals input according to the output level of the flip-flop input to the selection control terminal; A second flip-flop for inputting the input signal to a data input terminal, inputting a clock signal output from the selector to a clock terminal, and latching the input signal when the clock signal rises or falls; and A bit phase synchronization circuit having: 2. An output signal of the second flip-flop is input to a data input terminal, and the first clock signal is input to a clock terminal, and is input when a signal level of the clock signal rises or falls. 2. The bit phase synchronization circuit according to claim 1, further comprising a third flip-flop for latching the output signal. 3. A means for permitting selection by the selector only when a setting permission signal is input from the outside, and prohibiting change of the selection content of the selector when the setting permission signal is not input. A bit phase synchronization circuit as described. 4. A data output terminal of the first flip-flop, the output data of the first flip-flop being input to a data input terminal, the input signal being input to a clock terminal, and being input to a clock terminal. During the n times (n is a positive integer) rising or falling of the input signal,
4. The bit phase synchronization circuit according to claim 1, further comprising a protection circuit for transmitting the input signal to the selection control terminal of the selector only when there is no change in the signal input to the data input terminal. .