JPS583121A - Discriminating circuit for digital data - Google Patents

Abstract

PURPOSE:To use the same circuit with different mode and to limit an output bit of counter to the prescribed number, by using integration effect of a counter, and comparing a reproducing signal and a reference signal. CONSTITUTION:A clock source 1 is switched with the recording density and reproducing speed. Further, the polarity of a reproducing signal 9 and of a synchronizing reference signal 10 is discriminated for the coincidence with an EOR circuit 2. A counter 3 is controlled for up and down with an output 13 of an exclusive logical sum circuit (EOR) 2, and the direction of coincidence goes to UP count and the direction of discidence goes to Down count (or can be inversed), and reset is made with a reset signal 11 for each bit cell. The output of the counter 3 has bits of Q0-Qn. When Q0-Qn-1 all go to 1 at the UP side and they all go to 0 at Down side, feedback is made through an AND circuit 5 or 6, and an OR circuit 7 for count stop.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital data discrimination circuit, and more particularly to a digital data discrimination circuit in a magnetic recording/reproducing circuit.

Conventionally, as a digital data discrimination circuit, the reproduced signal for each bit cell is compared with the reference signal which is the output of a phase-locked oscillator synchronized with the reproduced signal, and the matched and mismatched parts are integrated into capacitors, and both are integrated at the end of each bit cell. It has been proposed to perform all 1.0 determinations depending on which of the classification values is larger, but since such a circuit is an analog circuit, it is difficult to implement LSI and high integration.

The present invention aims to provide such a digital data discriminating circuit in which the circuit is switched according to the recording/reproducing mode and the reproducing speed, and the digital integrator is not saturated.

Therefore, according to the present invention, there is provided a coincidence determination circuit that determines whether or not the polarities of the reproduced signal and the synchronization reference signal match, and an up/down counter that is reset every fixed interval and whose counting direction is fully controlled by the output of the coincidence determination circuit. A digital data discriminating circuit includes a clock switching circuit that switches and supplies a plurality of clocks to the up/down counter in response to a control signal, and a storage circuit that stores the most significant bit of the output of the up/down counter and outputs it as discrimination data. provided.

That is, the digital data discriminating circuit according to the present invention utilizes the integration effect of the counter to compare the reproduced signal and the reference signal, and updates the matching portion and the mismatching portion, respectively.
This is a digital data discriminating circuit that performs all the integrals in the counter, and compares whether the count value is on the UP count side or the Down count side at the end of each bit cell.

By switching the counter clock in accordance with all recording modes and playback speeds, the relative ratio of the clock cycle to the cycle between 1 bit cells of the playback signal is kept constant, and the count value is saturated and stopped at a constant value, making it possible to All upper bits are fixed at a constant value on the UP [or Down side, so that they are switched only on UP-Down, and the count (Il UP or Down or f) is determined.

FIG. 1 shows the configuration of a digital data discrimination circuit according to the present invention.

In the figure, a clock source 1 has a reproduction mode control signal 12.
The frequency is determined by the switching circuit 17, for example, recording density,
Switchable depending on playback speed. On the other hand, the FOR circuit 2 determines whether the polarities of the reproduced signal 9 and the synchronization reference signal 10 (generated from the output of a phase-locked oscillator synchronized with the reproduced signal 9) match. The counter 3 is an exclusive OR circuit 10R)2
tlUP and Down are controlled by the output 13 of , the direction of coincidence becomes the UP count and the direction of mismatch becomes the Down count (or vice versa), and is reset for each bit cell by the reset signal 11. The output of counter 3 is Qo
, QI...Qn has a pill, and the UP side has Qo...
...When all Qn-s become 1 and all the Down side becomes 0, it is fed back through the AND circuit 5 or 6 and the OR circuit 7t-, and the count is stopped. Therefore, the most significant bit Qn
If the output 15 is 0, it indicates UP, and if it is 1, it indicates Down. The output 15 of the most significant bit Qn is taken into the register 8 by the reset signal 11 and stored. The register 8 outputs demodulated data (discrimination data) 16.

Note that 4 is an inverter circuit.

3- Figure 2 shows a time chart of data discrimination using the GCR method as an example. In the figure, the numbers on the left side correspond to the respective parts in FIG.

The place where the count stops is 3, which is the length of 1 bit cell.
/4 later. Therefore, the number of output lines of the counter 3 can be reduced. Even if there is a phase shift as shown by the broken line 9a, the count value never returns to the θ count.

According to the present invention, the same circuit can be used in different modes, and the output bits of the counter can be limited to a constant number. Moreover, since 0 or 1 can be determined only by the most significant bit, the circuit configuration is simple and integration is extremely easy.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the configuration of a digital data discrimination circuit according to the present invention, and Figure 2 is a curve diagram showing a time chart of the circuit shown in Figure 1. In the figure, l is a clock source, 2 is a match determination circuit (EO
R), 3 is counter, 4 is inverter, 5.6 is AND
7 indicates an OR circuit, and 8 indicates a register 4. Further, 9 is a reproduction signal, 10 is a reference signal, 11
is a reset signal, 12-digit clock switching control signal, 13 is a coincidence determination output signal, 14 is a count stop signal, 15
16 indicates the output signal of the most significant pin) Qn, and 16 indicates the demodulated data (discrimination data) signal. Furthermore, 17 is a clock switching circuit.

Claims (1)

[Claims] a coincidence determination circuit that determines whether or not the polarities of the reproduced signal and the synchronization reference signal match; an up-down counter that is reset at regular intervals and whose sicrant direction is fully controlled by the output of the coincidence determination circuit; A digital data discriminating circuit comprising: a clock switching circuit that switches and supplies a plurality of clocks in response to a control signal; and a storage circuit that stores the most significant value of the output of the a.p-down counter and outputs it as discrimination data.