JPH022716A - Bit clock regenerating circuit - Google Patents

Abstract

PURPOSE:To regenerate the bit clock of input data, to eatimate phase error data, and to form a pre-set timing pulse for correcting a phase error by performing the 2N-ary count of a fast clock with a frequency of 2 times that of the bit clock of the input data by a pre-set counter. CONSTITUTION:The edge of the input data is detected by the edge selection part 10 of a bit clock generation circuit, and the fast clock with the frequency of 2N(N: integer) times that of the bit clock of the input data is counted by a 2N-ary counter part 20. The preset data for correcting the phase error is formed from the count output data of the counter part 20 by a pre-set data forming part 30. And phase comparison between an edge detecting pulse from the detecting part 10 and the 2N-ary output pulse of the counter part 20 is performed at a phase comparison part 40, and the pre-set timing pulse for correcting the phase error corresponding to the phase error data is outputted to the counter part 20 by a pre-set timing pulse formation circuit 50 which inputs the phase error data on which the phase comparison is applied at the comparison part 40.

Description

[Detailed description of the invention]

A. Industrial Application Field The present invention is directed to the so-called digital PLL (PLL: PLL).
The present invention relates to a bit clock reproducing circuit using a locked loop (locked loop) and is used, for example, to reproduce a bit clock on the receiving side of a digital transmission system such as a digital tape recorder or CD player. B. Summary of the Invention The present invention provides a bit clock regeneration circuit using a so-called digital PLL.
(N is an integer) to count high-speed clocks with twice the frequency 2''
A digital PLL operation with a large time constant is performed by controlling the preset timing of data to the preset counter section in accordance with the phase error data obtained by the phase comparison section using a forward recent counter section, This enables highly stable bit clock reproduction. C Conventional technology Traditionally, digital transmission systems such as digital tape recorders and CD players use 3 PM (ThreePos)
ition Modulation), MPM (Mo
Didied Frequency Modulation
n) Various self-clock modulation methods such as M"FM (Modidied MFM) are used. In the digital transmission system that uses the above-mentioned self-clock modulation method,
It is necessary to reproduce the bit clock of the transmitted data on the receiving side and extract the data using that bit clock. As the bit clock reproducing circuit, a so-called digital PLL configuration is used, which generates a bit clock by frequency-dividing a high-speed clock and also increases the phase of the bit clock by 1 m using a data edge. For example, as disclosed in Japanese Patent Application Laid-Open No. 56160157, phase correction data corresponding to the output state of a counter that counts high-speed clock pulses and generates a bit clock is loaded into the counter for each data edge. 2. Description of the Related Art A bit clock reproducing circuit having a digital PLL configuration is known in which the occurrence of sick is prevented by correcting the phase of the bit clock. D Problems to be Solved by the Invention By the way, in digital transmission systems such as digital tape recorders and CD players, there is data instability due to lack of data itself such as the tron knob 1- or disturbances in the servo system. It is necessary to perform highly stable bit clock recovery by slowing down the response to such disturbances. However, in the conventional pit clock regeneration circuit having a digital PLL configuration, the responsiveness is determined by the value of phase correction data loaded into the counter. Even if the phase correction data of the bit clocker is loaded into the counter for each data edge to perform the phase correction of the bit clock, the PLL The time constant of the loop filter cannot be made that large. Therefore, in view of the above-mentioned conventional problems, the present invention has been made to:
In a bit clock regeneration circuit with a digital PLL configuration, the purpose is to perform highly stable bit clock regeneration that suppresses the occurrence of jitter due to external disturbances, and is capable of performing digital PLL operation with a large time constant. It is an object of the present invention to provide a pit clock regeneration circuit with a new configuration. E. Means for Solving the Problems In order to achieve the above-mentioned object, the bit crotter reproducing circuit according to the present invention has the following basic configuration as shown in FIG.
an edge detection section (10) that detects edges of human data; a 2Nl recent counter section (20) that counts a high-speed clock with a frequency 2N (H is an integer) times the bit clock of input data; and the preset counter. Part (20
), which forms preset data for phase error correction from counting output data by the above, edge detection pulses from the edge detection section (10), and 2N-ary counting output from the preset counter section (20). A phase comparator (40) that performs phase comparison with the pulse and phase error data obtained by the phase comparator (40) are integrated to generate a recent timing pulse for phase error correction according to the phase error data. a timing pulse forming section (50) for forming a timing pulse;
The preset timing of the recent data relative to the input data (20) is controlled in accordance with the phase error data obtained by the phase comparator (40), and the pit clock whose phase is fixed to the edge of the input data is output to the recent counter unit (20).
It is characterized by outputting from 0). F Function In the bit clock regeneration circuit according to the present invention, the preset counter unit (20) regenerates the bit clock of input data by counting the high speed clock having a frequency 2N times the bit clock of human data in 2N base. do. The preset data forming section (30) forms preset data for phase error correction from the count output data from the preset counter section (20). Further, the phase comparator (40) compares the phase of the 2M-ary counting output pulse by the preset counter unit (20) with the edge detection pulse of the input data by the edge detector (10). The phase error of the bit clock generated by the counter section (20) is detected. Further, the preset timing pulse forming section (50) integrates the phase error data obtained by the phase comparison section (30) to form a preset timing pulse for phase error correction corresponding to the phase error data. The bit clock generated by the preset counter section (20) is generated at the timing of the preset data given by the preset data forming section (30) and the preset timing pulse given by the preset timing pulse forming section (50). The phase is corrected by being preset in the preset counter section (20), and the phase is fixed to the edge of the input data. G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 2 showing a specific embodiment of the pit clock regeneration circuit according to the present invention, (1) is input data (IIDM).
(2) is the data input terminal to which the input data (11D old, , ) is supplied with the bit clock (
A high-speed clock (FCLK) that is 2N (N is an integer) times the
This is the clock input terminal to which the clock signal (LK) is supplied. In this example, N=3 and the above input data (IIIMI
A high-speed clock (FCLK) with a frequency eight times that of the bit clock (BCLK) of i,) is connected to the clock input terminal (
1). The data input terminal (1) is connected to the data output terminal (3) via first and second non-inverting buffers (2A) and (2B), and the first and second non-inverting buffers (2B) are connected to the data output terminal (3). Edge detector (1) via buffer (2A)
0). Further, the clock input terminal (2) is connected to the first and second clock input terminals.
The edge detection section (10) and the preset counter section (20) are connected via the inverters (4A) and (4B).
, a preset data forming section (30), a timing pulse forming section (45), an unlock detecting section (60), and the like. The edge detection section (10) is composed of a 4-bit D-type flip-flop (11) and an EXOR gate (12) as follows. In other words, the above-mentioned flip-flop (]1) receives the high-speed clock (FCLK) at the clock input terminal, and the input data (old HD, 7) at the input terminal of the fourth pin input data (40). It is meant to be given. Further, the EXOR gate (12) has its respective input terminals connected to the respective output terminals of the third and fourth bit output data (3Q) and (4Q) of the above-mentioned flip-flop (11). Further, the above type flip-flop (11) has the output terminal of the fourth pinpoint output data (4Q) connected to the input terminal of the third bit input data (3D), and furthermore, the output terminal of the fourth pinpoint output data (4Q) is connected to the input terminal of the third bit input data (3D). The output terminal of the EXOR gate (12) is connected to the input terminal of the EXOR gate (2D). In this embodiment, the above-mentioned flip-flop (11) only needs to have a substantially N (N=3) focus configuration, and the input terminal of the first bit input data (In) and The output terminal of the first bit output data (10) is in a disconnected state. The edge detection unit (10) then receives input data (I
IDMI i, , ), the high speed clock (F
The edge detection operation is performed in synchronization with the EXO
The edge detection pulse (['DGE) obtained as the output of (12) and the above-mentioned flip-flop
11) The edge detection pulse (EDGE) with a delay of two clocks obtained at the output terminal of the second focus negative output data (2a)
-1) is supplied to the timing pulse forming section (45) and unlock detecting section (60). Further, the preset counter section (20) is a 4-pin, ie, 24 counter (21) having a preset function.
The 3-8 line decoder (22) is configured as follows. That is, the counter (21) receives the high speed clock (FCLK) at its clock input terminal, and
The recent timing pulse (PLO) output from the timing pulse forming section (45) is the load pulse (
The 3-bit preset data (D,) to (D,) output from the recent data forming section (30) are input to the load input terminal as input data (A) to the lower three pins. (C) is applied to the data input terminal, and furthermore, the input terminal of the most significant bit of human input data (D) is grounded. and,
The counter (21) controls the preset data (O) at the timing of the preset timing pulse (Pl).
n) to (D,) are preset (loaded), and the rising edge of the high speed counter (FCLK) is 2N.
Performs (N=3) base counting operation. Further, the line decoder (22) has the counter (
The output data (Q,) to (mouth C) obtained at the data output terminal of the lower 3 bits of 21) is the 3-bit input data (8).
~(C) is given to the data input terminal. This line decoder (22) performs the decoding operation as shown in Table 1, and the count value [0 ~7], the logic is alternatively ``
Output data (Yo) to (Y, ) that become "L" are formed. Then, in the preset counter (20), the 3-bit output data (
OA) to (Qc) are supplied to the unlock detecting section (60), and the third focus output data (Qc) is supplied to the preset data forming section (30) as well as the D type output stage. It is supplied to the data input terminal of the flip-flop (5). In addition, the line decoder (22
The output data (Yo) to (Y, ) obtained in ) are supplied to the timing pulse forming section (45), and further,
Output data for 4 lines (Y,) to (Y,)
is supplied to the preset data forming section (30). Here, the above-mentioned flip-flop (5) uses a high-speed clock (FC) supplied to the above-mentioned clock input terminal (2).
A high-speed clock (FCLK) obtained by inverting the high-speed clock (FCLK) by the first inverter (4A) is applied to the clock input terminal, and the preset counter section (FCLK) performs a counting operation in synchronization with the high-speed clock (IIcLK). 20) 3rd bit output data (Q, ) by the above counter (21)
The positive output data (Q), which is delayed by 172 clocks of the high speed clock (HCLK), is input to the pit clock (BCLK).
LK) from a clock output terminal (7) via a non-inverting buffer (6). The recent data forming section (30) is composed of three NOR gates (31) to (33), and the first NOR gate (31) is connected to the line decoder (22). The output data (Y,) to (Y,) are given to the input terminal, and the second NOR gate (32) receives the counter (21) of the preset counter section (20).
) and the output data (y, ) of the line decoder (22) are given to the third NOR gate (33). (Ya) and (ys) are given. The preset data forming section (30) processes the count output data ([lA) to (port C) of the counter (21) to the first to third NOR gates (31) to (3).
3) Preset data (D,) as shown in Table 2
〜(D,) is formed, and this preset data (D,)〜
(DC) is applied to the data input terminal of the counter (21) as input data (A) to (C) of the lower three pins. In addition to the nib reset data section, the timing pulse forming section (45) also controls the line decoder (20) of the preset counter section (20).
22) output data (yo), (y,), (yz
) is given to the input end of the NOR gate (41), the output data (YO) of the line decoder (22), (Y
2) A coefficient generation section (42) to which ~(Y, ) is given, an adder (43) to which coefficient data formed in the coefficient generation section (42) is given to one data input end, and the adder (43), an accumulator (44) to which the added output data is applied; a first and a second NAND gate ( 51L (5
2) etc., it is structured as follows. That is, the output end of the NOR gate (41) is connected to the first NAND gate (51) via an inverter (46). This NOR gate (41)
is the output data (Yo) of the above line decoder (22)
, (Yl), (Yz) is logic rL, that is, the recent counter unit (2
A signal indicating a period in which the count value of the counter (21) of 0) is "0 to 2" is formed by logic rH, and the count value of the counter (21) of
), (1), (2: A gate control signal that becomes logic rH during periods other than l is applied to the first NAND gate (51). The first NAND gate (51) is configured to detect the unlock The unlock detection pulse (INLO) by the section (60)
CK) is given, and this unlock detection pulse (
During the unlock period when both the gate control signal (UNI, 0CK) and the gate control signal are logic "H", the edge detection section (UNI, 0CK) is activated.
10) by using the edge detection pulse (EDGIE) as the preset timing pulse (PL) (OR game) (
53). Further, the coefficient generating section (42) includes three NOR games).
(42A) to (42G), and the first NOR gate (42A) is connected to the line decoder (2).
The output data (yo), (Y2) to (Y4) of 2) are given to the second NOR gate (42B), and the output data (yo), (Y4) of the line decoder (22) are given to the second NOR gate (42B).
yi) , (Y4) are given, and further, the third NO
The output data (Yo), (Ys) to (Y, ) of the line decoder (22) are applied to the R gate (42C). This coefficient generator (42) uses the first to third NOR gates (42A) to (42C) to generate output data (Yo), (yz) of the line decoder (22).
) to (Y, ) to obtain the count value [0 to 7] of the counter (21) of the preset counter section (20).
In contrast, the output data of the first NOR gate (42A) is the first bit data (DI), and the output data of the second NOR gate (42A) is the first bit data (DI).
Let the output data of the R gate (42B) be the second and third bit data ([+2), (o3), and the third N
Coefficient data (Dl) as shown in Table 3 with the output data of the OR gate (42C) as the fourth bit data (D4)
~(D4) is formed. Then, the coefficient generating section (42
) is the coefficient data (Paste) ~ (D4) that is added to the adder (
43) to one of the input data (IB) to (4B), and the highest focus data (D4
) as the first and second EXOR gates (47), (
48) to one input terminal of each. Further, the adder (43) includes the accumulator (
The output data (IQ) to (40) of 44) are given to the data input ends of the other input data (IA) to (4A). This addition 1γjs (43) is the accumulator (44
) output data (IQ) ~ (40) and the above coefficient data (
Dl) to (D4) and the addition output data (1Σ
) to (4Σ) to the accumulator (44), and the most significant bit data (4Σ) of the addition output data (1Σ) to (4Σ) is applied to the first EXOR gate (
47). The first EXOR gate (47) directly supplies its gate output to the second NAND gate (52), and the second EXOR gate (48) supplies its gate output to the inverter (49). through the second NAND
It is given to the gate (52). And the above second NA
The ND gate (52) is connected to the first EXOR gate (4).
7) gate output is logic r l('' and the second EXO
During the period when the gate output of the R gate (48) becomes the logic rLJ, the edge detection pulse (EDGE) from the edge detection section (10) is set to the preset timing pulse (p
tn) through an OR gate (53). Furthermore, the accumulator (44) is configured as follows with first and second D-type flip-flops (44A) and (44B) each having a 6-bint configuration. In other words, the first D-type Frisopfromp (44A)
The above-mentioned high-speed clock (FCLK) is applied to the clock input terminal, and the addition output from the adder (43) is applied to the data input terminal of the first to fourth human input data (10) to (4D). Data (1Σ) ~ (4Σ)
is applied to the fifth bit input data (5D), and the first and second NAND gates (51) and (52
) are provided via an OR gate (53). This first D-type flip-flop (44A) receives the first to fifth bit input data (ID) to (5D).
is launched on every rising edge of the above-mentioned high speed clock (FCLK). The fifth bit output data (5Q) of the first D-type flip-flop (448) is 4(
Fixed AND gates (44C,) to (44C,) are provided, and the first to fourth bit output data (IQ) to (40) of the first D-type flip-flop (44A) are applied to each of the AND gates. (44C,) to (44C,), the first
to the fourth bit are given to the data input terminals of the input data (10) to (4D). Further, the second D-type flip-flop (44B) is
The above-mentioned high-speed clock (FCLK) is applied to the clock input terminal, and the edge detection pulse (EDGE-1) from the above-mentioned edge detection section (10) is applied to the control input terminal.
) is given as latch control data (ENB). This second D-type flip-flop (44B) receives the first to fourth focus input data (ID) to (4D) that are applied to the data input terminal via the respective AND gates (44G,) to (44C,). Regarding the above high speed clock (
The latch operation is performed in synchronization with the latch control data (ENB), that is, the edge detection pulse (EDGE).
-1). Then, the second D-type frisopfromp (44B) converts the first to fourth bit output data (IQ) to (40) into the other manual data (ID) to (4D) of the adder (43). At the same time as giving it to the input terminal,
The most significant bit data (4Q) of the integrated data is given to the second EXOR gate (48). The accumulator (44) uses the latch system for the addition output data (1Σ) to (4Σ) from the adder (43). By latching with the ff1l data (ENII), that is, the edge detection pulse ([DGIE-1), the repetitive phase of the binary counting operation of the counter (21) of the preset counter section (20) and the input data ( A phase comparison is made with the edge phase of IIDMli, , ) to form phase error data for the edge phase of the input data (IIDMI, fi), and this phase error data is provided to the adder (43). The error data is accumulated in the accumulator (44) by latching the addition output data (lΣ) to (4Σ) from the adder (43) every edge detection pulse (IEDGE-1). (44) Output data (IQ) ~ (
4Q) That is, the integrated value of the above phase error data is the above O
It is cleared by the preset timing pulse (PLO) outputted through the R gate (53), and is
0]. The first and second EXOR gates (47), (
The second NAND gate (52) to which the gate output of the accumulator (48) is supplied changes the value of the output data (IQ) to (4Q) of the accumulator (44) from [7] to [8], or , the edge detection pulse (EDGE) detected by the edge detection unit (10) two clock periods before the timing of changing from [8] to [7] is set as the preset timing pulse (PLII) (OR game) (53) Output via. The preset timing pulse (PTO) is generated in the timing pulse forming circuit (45) at a timing synchronized with the edge detection pulse (EDGE) by the edge detection section (10), that is, the edge phase of the input data (IID old 87). It is applied to the load input terminal of the counter (21) of the preset counter section (20). In the preset counter section (20), every time the preset timing pulse (Ptn) is given from the timing pulse forming section (45), the preset data (D) is given by the preset data forming section (30).
A) to (D,) are preset in the counter (21). The counter (21) has precent data (D
, ) to (D, ) is performed, and as shown in the time chart of FIG.
The repetitive phase of the base counting operation is determined by the high speed clock (FCL).
The phase is corrected by one clock of K). In this embodiment, a digital PLL with the above phase correction is used.
By performing the operation, the counting output data (OA) to (QC) of the counter (21) becomes the input data (1
At the timing of the edge detection pulse (EDGE) of (D old 3,), the repetition phase of the 23-ary counting operation is fixed in a state where the count value becomes [1]. The unlock detector (60) also detects an edge detection pulse (ED) obtained by the edge detector (12).
first and second timer parts (61) that count G 14 ) by aI; (62), an adder (6) that adds a constant [-1] to the count value indicated by the count output data (OA) to (Qc) of the counter (21) of the preset counter section (20);
3), addition output data (1Σ) of the adder (63) ~
(3Σ) are provided to the first and second adders (64A
), (64B), the first and second adders (64B),
4A), (64B) each addition output data (lΣ1)
~(4Σ,), (lΣ2) ~(4Σ2) is the edge detection pulse (EDGE-1) by the edge detection section (12).
We had lunch at the above-mentioned adders (64A), (64
The accumulator (65) etc. supplied to B) are configured as follows. That is, the first timer part (61) detects the edge detection pulse (ED) obtained by the edge detection section (12).
GE) is applied to the control input terminal as a control signal (ET, EP), and the carry output (CY) of this counter (61A) is applied to the control input terminal as a control signal (ETEP). Second 24 given
It is equipped with a digit counter (61B), and each of the above counters (61A
), (61B), the edge detection pulse (EDGE) is counted in synchronization with the high speed clock (FCLK) given to each clock input terminal of
The carry output (CY) of the quaternary counter (61B) is the first
The inverter (
61C). Each of the counters (61A) and (61B) is set to a constant value at each output timing of the first timer output (EDGE+□8).

The precent data (A) to (D) of [0] are the first
24 counter (61A), and the precent data (A) to (D) of constant [8] are preset to the second 2' counter (61B), so that the 128-decimal performs counting operations. The first timer part (61) outputs a first timer output (EDGElzs) every time it counts 128 edge detection pulses (EDGU,), and outputs the first timer output (EDGE+zJ) as described above. First D-type flip-flop (44A) of timing pulse forming section (45)
It is applied as a clear signal to the accumulator (65) through the sixth bit stage. Further, the second timer part (62) is configured to control the edge detection pulse (IEDG) obtained by the edge detection section (12).
li) is used as a control signal (EP) by an AND gate (62A
) are provided to each control input terminal through a first and second 2'-base counter (62B), (62C), and an upper jrk high-speed clock (62C) is provided to each clock input terminal.
The above edge detection pulse (EDGB
), and the first 24-decimal counter (62
The carry output (CY) of B) is applied as a control signal (ET) to the control input terminal of the second 24-ary counter (62C), and the carry output (CY) of the second 24-ary counter (62C) is It is designed to be output as a lock detection pulse (UNLOCK) via an inverter (6211). Each of the counters (61A) and (61B) has a detection output of a detection logic circuit (66) that detects a carry of the accumulator (65) as a load pulse (LD).
is given to each load input terminal as a constant [
0] preset data (A) to (D) are respectively preset to perform a 256-base counting operation. The second timer part (62) uses a constant [
0] by presetting the preset data (A) to (D), the second 24-decimal counter (62C
)'s carry output (CY) becomes logic "L" and outputs a logic "H" unlock detection pulse (UNLOCK) via the inverter (62A). The first and second 2'-base counters (62B) and (62G) forming the second timer part (62) are as follows:
The above logic rH. The above AN at the unlock detection pulse (UNLOCK) of
When the D gate 62A) is opened, the edge detection pulse (EDG) obtained by the edge detection section (12) is
E) is applied to each control input terminal as a control signal (EP) to start the counting operation of the edge detection pulse (EDGE) synchronized with the high speed clock (FCLK). The first and second 24-decimal counters (62B), (62
C) is the edge detection pulse (IEDG'E) of 25
Before counting 6 shots, the preset data (8) of constant [0] is output from the carry output of the accumulator (65).
When ~(D) is preset, its preset value [0
], the second 24-decimal counter (62C) passes through the impark (62D) to detect a logic "H" unlock detection 0 pulse (IINLOcK).
The edge detection pulse (EDGE) continues to be output.
), the second 24-decimal counter (
62G) carry output (CY) becomes logic rH,
Logic r output via the inverter (62A)
The AND gate (62^) is closed by the unlock detection pulse (UNLOCK) of [,'', and the counting operation is completed. Further, the accumulator (65) has first and second 8-bit D-type flip-flops (65A), respectively.
, (65B) and 8 AND gates (65C,) ~
(65C,) is configured as follows. That is, the first D-type flip-flop (44A)
The above-mentioned high-speed clock (FCLK) is applied to the clock input terminal, and the first and second adders are connected to the data input terminals of the first to eighth bit input data (ID) to (8D). Addition output data (1Σ) to (4Σ) from (64A) and (64B) are given. This first D-type flip-flop (65A) receives the first to eighth bit input data (ID) to (8D).
is launched at every rising edge of the above-mentioned high-speed clock (FCLK), and the output data of each bit (10) to (8
Q) to each of the above AND gates (65G,) to (65c,
) through the second D-type flip-flop (65B)
1st to 8th bit input data (ID) ~ (8D)
is given to the data input end. Moreover, the second D-type flip-flop (65B) is
The above-mentioned high-speed clock (to FCL) is given to the clock input terminal, and the edge detection pulse (EDGEi) from the above-mentioned edge detection section (10) is given to the control input terminal as latch control data (IENIl). . This second D-type flip-flop (65B) receives the first to eighth bit input data (10) to (8D) applied to the data input terminal via the AND gates (65G, ) to (65C1). Regarding the above high speed clock (
The latch operation is performed in synchronization with the launch control data (ENB), that is, the edge detection pulse (EDGE).
-1). The second D-type flimp flop (65B) outputs its lower 4-bit output data (IQ
) to (40) are applied to the input terminals of the other input data (10) to (4D) of the first adder (64A), and the upper 4-bit output data (50) to (80) are applied to the second input data (10) to (4D). The other human input data (ID) of the adder (64[1) ~
(4D), and furthermore, the most significant focus data (8Q) is applied to the first EX of the detection logic circuit (66).
It is given to the OR gate (66^). The accumulator (44) generates the launch control data (ENB), that is, the edge detection pulse ( EDGE
-1), the repetition phase of the 23-ary counting operation of the counter (21) of the preset counter section (20) and the input data (HDMI in
) to form phase error data with respect to the edge phase of the input data ()IDMl, 7), and this phase error data is sent to the adder (64A).
), (64B) and integrate it. Output data (IQ) of the above accumulator (65) ~ (
8Q), that is, the integrated value of the phase error data is determined by the first timer part (61) when the edge detection pulse (ED
GE), the first D-type flip-flop (44A) of the timing pulse forming section (45) is
) through the sixth bit stage of each AND gate (65C
I) to (65C*) are supplied to the first timer output (
Cleared by EDGE+□,)

It becomes [0]. Further, the detection logic circuit (66) includes first and second
At the EXOR gates (66A), (66B), inverter (66C) and N A N D (660),
It is structured as follows. Each of the above EXOrl games 1- (66A), (66B
) is supplied with the most significant pinout (3Σ) of the adder TK27t (63), and the most significant bit output (4Σ) of the second adder (64B) is supplied with the EXOR.
The most significant bit data (80) of the accumulator (44) is supplied to the EX
It is supplied to the OR gate (66B). In addition, the above N
A N D (66D) is the edge detection section (1
0) is supplied, the output of the first EXOR gate (66A) is directly supplied as a gate control signal, and the output of the second EXOR gate (668) is supplied directly. is supplied as a gate control signal via an inverter (66C). In the unlock detecting section (60) configured as described above, the first timer part (61) detects the edge detection pulse (
EDGE), the most significant bit data (4Σ) of the integrated value of the phase error data latched in the accumulator (65) changes from logic "L" to logic r.
When the logic changes to H, or from logic rH to logic L, a carry detection pulse is output from the detection logic circuit (66), and the second timer part (66) outputs a carry detection pulse.
2) outputs a logic "H" unlock detection pulse (UNLOCK) via an inverter (62D). H Effects of the Invention In the bit clock regeneration circuit according to the present invention, the bit clock generated by counting high-speed clocks with a frequency 2N times the bit clock of input data in the preset counter section that performs a 2N-ary counting operation is as follows. A phase error with respect to the edge of the input data is detected by the phase comparator, and preset data is presented to the preset counter at the timing of a preset timing pulse formed by the preset timing pulse forming unit based on the phase error data. By doing so, the phase is corrected and the phase is fixed to the edge of the input data. The preset timing pulse forming section integrates the phase error data obtained by the phase comparing section, thereby
Forms a preset timing pulse for phase error correction. In the bit clock reproduction circuit according to the present invention, the preset timing pulse forming section that integrates phase error data to form a preset timing pulse for phase error correction functions as a loop filter with a large time constant, and By performing a PLL operation, it is possible to perform highly stable bit clock playback that suppresses the occurrence of zinc due to disturbances.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a bit clock recovery circuit according to the present invention, FIG. 2 is a circuit configuration diagram of a bit clock recovery circuit showing a specific embodiment of the present invention, and FIG. 3 is a block diagram showing the above embodiment. 3 is a time chart for explaining the precent operation of the preset counter section in FIG. 1... Data input terminal 2... Clock input terminal 3... Data output terminal 7... Bit clock output terminal 10... Edge detection section 20... Preset counter section 30 ...Preset data forming section 40...Phase comparison section 45...Timing pulse forming section

Claims (1)

[Scope of Claims] An edge detection unit that detects edges of input data; and a 2^N preset counter unit that counts high-speed clocks with a frequency 2^N (N is an integer) times the bit clock of input data. , a preset data forming section that forms preset data for phase error correction from count output data from the preset counter section; and a phase between the edge detection pulse from the edge detection section and the 2^N-adic counting output pulse from the preset counter section. A phase comparison section that performs comparison; and a timing pulse formation section that integrates phase error data obtained by the phase comparison section and forms a preset timing pulse for phase error correction according to the phase error data, The preset timing of the preset data to the preset counter section is controlled according to the phase error data obtained by the phase comparison section, and a bit clock whose phase is fixed to the edge of the input data is output from the preset counter section. bit clock regeneration circuit.