JP2921014B2 - Digital PLL - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a digital PL suitable for forming a clock based on a reproduced EFM signal of a compact disk.
About L.

[Summary of the Invention]

The present invention provides, for example, a digital PLL for forming a clock based on a reproduced EFM signal of a compact disk, by setting a dead zone in a short pattern in a measurement range of a cycle without deteriorating an error rate even with a disk having poor asymmetry. It can be played.

The present invention provides, for example, a digital PLL for forming a clock based on a reproduced EFM signal of a compact disk, by making the weight in a short pattern smaller than a theoretical value, thereby reproducing a disk with poor asymmetry without deteriorating an error rate. It is made possible.

[Conventional technology]

A digital PLL is used to form a clock based on a reproduced EFM (8-14 modulation) signal from a compact disc.

In a digital PLL, a digitally controlled oscillator whose oscillation frequency is controlled according to setting data is used. When forming a clock based on a reproduced EFM signal with a digital PLL, the phase difference between the phase of the reproduced EFM signal and the phase of the output signal of the digitally controlled oscillator is measured by a counter, and the oscillation frequency of the digitally controlled oscillator is controlled by this phase difference. Is done. Since the reproduced EFM signal contains a jitter component, a frequency control loop is required together with such a phase control loop. The frequency difference of the reproduced EFM signal is detected by measuring the period between the changing points of the EFM signal with a counter. The digitally controlled oscillator is controlled according to this frequency.

[Problems to be solved by the invention]

In a compact disc, a pit defect having a polarity in which the duty ratio of each length of the pit irregularities is different may occur. Such a defect is called asymmetry. High-range jitter occurs on disks with poor asymmetry. In addition, jitter may occur due to intersymbol interference or pit abnormalities.

In a conventional compact disc player in which a clock based on a reproduced EFM signal is formed by a digital PLL, when a disc with poor asymmetry is reproduced, the TOC (T
error rates are worse between "able of Cotents" and songs.

This is a 3T pattern (all 0 EFM) between TOC and songs
Signals) are generated. Conventional digital PL
In L, if the asymmetry is bad, the oscillation frequency is not stable in the case of a short pattern such as the 3T pattern.

That is, the pattern of the EFM signal is 3T to 11T.
Now, a disc with poor asymmetry is played, for example, ±
Assume that 0.5T jitter occurs. The jitter of ± 0.5T has a different weight for fluctuation between a short pattern such as a 3T pattern and a long pattern such as an 11T pattern. That is, the fluctuation of 0.5T with respect to the 3T pattern is a fluctuation of (0.5 / 3) × 100 = 16.6%. On the other hand, 0.5 for the 11T pattern
The variation of T is (0.5 / 11) × 100 = 4.5%.

In a conventional digital PLL, even in the case of a pattern having a short cycle such as a 3T pattern, the cycle measurement range is wide. In the 3T pattern, the weight with respect to the time axis fluctuation becomes large, so that the oscillation frequency of the digitally controlled oscillator is largely moved based on a wide period measurement range, and the operation of the numerically controlled oscillator is not stable. For this reason, the error rate deteriorates with a pattern having a short cycle such as the 3T pattern.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital PLL capable of improving an error rate even for a disk having poor asymmetry.

[Means for solving the problem]

The present invention includes a phase difference measuring unit that measures a phase difference between a phase of an oscillation output of a digitally controlled oscillator and a phase of an input signal, and a frequency difference measuring unit that measures a frequency difference of an input signal. In a digital PLL configured to control a digitally controlled oscillator based on a frequency difference, a frequency difference measuring unit includes: a pattern detecting unit that detects a pattern of an input signal; a period measuring unit that measures a period of the input signal; A conversion means for obtaining frequency correction data from a pattern of the input signal detected by the detection means and a cycle of the input signal detected by the cycle measurement means, wherein a dead zone is set in the cycle measurement range for short patterns. This is a digital PLL characterized by the following.

According to the present invention, the conversion means includes a memory in which frequency correction data formed by weighting in correspondence with the cycle and the pattern is stored, so that the weight in a short pattern is reduced.

[Action]

In the case of a short cycle pattern such as a 3T pattern,
A dead zone is set in the frequency measurement range. In this way, even in the case of a disk having poor asymmetry, the digitally controlled oscillator can be stabilized and the error rate can be improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes the phase of the reproduced EFM signal S _EFM and the clock P.
A phase difference measuring circuit for measuring a phase difference from the LCK phase, a frequency difference measuring circuit for measuring a frequency difference of the reproduced EFM signal,
Reference numeral 3 denotes a digitally controlled oscillator whose oscillation frequency is controlled according to numerical data.

The phase difference measurement circuit 1 is supplied with a reproduction EFM signal S _{EFM of a} compact disk from an input terminal 4. At the same time, the clock PLCK is supplied from the digitally controlled oscillator 3 to the phase difference measurement circuit 1. Also, the phase difference measurement circuit 1
, A system clock SCK is supplied from a terminal 7 as a clock for measurement. The frequency of the system clock SCK (for example, 34.5 MHz) is, for example, eight times the frequency of the clock PCLK (for example, 4,3218 MHz).

In the phase difference measuring circuit 1, using the system clock SCK, a phase difference between the output clock PLCK phase of the digital controlled oscillator 3 and reproduced EFM signal S _EFM phase is measured.

That is, in FIG. 2, the reproduced EFM signal (FIG. 2B)
In the time T ₁ of the the data change point t ₁ for example to the fall t ₂ clocks PLCK (FIG. 2 C), as shown in FIG. 2 D, the system clock SCK (FIG. 2 A) is counted .

The system clock SCK is, as shown in FIG.
Are counted in the order of "0, -3, -2, -1, 0, 1, 2, 3, ...". Conventionally, the system clock SCK is
.. Are counted in the order of "-4, -3, -2, -1, 0, 1, 2, 3,...", But in this embodiment, the count value "-4" is processed as 0. This is because, as described later, the dead zone of the phase lock is set so that the phase lock can be performed even on a disk having poor asymmetry.

In Figure 2, at time T ₁ of the the data change point t ₁ of the reproduced EFM signal to the falling t ₂ clocks PLCK, the system clock SCK is 4 clocks counted. The system clock SCK has a frequency eight times the frequency of the clock PLCK. Therefore, the time T from the data change point t ₁ of the reproduced EFM signal to the falling t ₂ of the clock PLCK
_{When 1} , the system clock SCK is 4 clocks (clock PL
When counting is performed (） cycle of CK), the phase of the reproduced EFM signal is synchronized with the phase of the clock PLCK. The system clock SCK is "0, -3, 2, -1, 0, 1, 2,.
In this case, the count value of the system clock SCK becomes “0” as shown in FIG. 2D.

As shown in FIG. 3, the phase of the clock PLCK is the reproduction EFM.
When leads the signal of the phase, the system clock SCK is less than 4 clocks counted by the time T _1. In FIG. 3D, the system clock SCK is counted for two clocks, and the count value is a negative value (for example, “−2”).
become. When the count value is a negative value, the phase of the clock PLCK output from the digitally controlled oscillator 3 is delayed.

As shown in FIG. 4, the phase of the clock PLCK is
When delayed from the signal S _EFM, the system clock SCK is greater than 4 clocks counted during a time T _1. In FIG. 4D, the system clock SCK is counted for five clocks, and the count value becomes a positive value (for example, “1”). When the count value is a positive value, the phase of the clock PLCK output from the digitally controlled oscillator 3 is advanced.

Thus, by controlling so that the time T ₁ of the the data change point t ₁ of the reproduced EFM signal to the falling t ₂ of the clock PLCK is 4 clocks, the phase of the phase and clock PLCK playback EFM signal Is locked.

Incidentally, in this embodiment, not only when the system clock SCK is 4 clocks counted during a time T _1, even if it becomes zero clocks (or 8 clocks), the phase difference measuring circuit 1 Output "0". That is, conventionally, the count value “−4”
Is processed as "0". Therefore, as shown in FIG. 5, the phase is locked even when the data change point of the reproduced EFM signal is synchronized with the falling edge of the clock PLCK. In other words, the reproduced EFM signal S
_{Even when} the phase of the _{EFM and} the phase of the clock PLCK are shifted by ± 180 degrees, the phase is locked.

This is to enable phase locking even if the asymmetry of the compact disc being reproduced is poor and the reproduced EFM signal contains ± 180 degrees of jitter.

That is, the asymmetry is poor reproduction EFM signal S eg jitter ± 0.5 T min in _EFM occurs. The ± 0.5T jitter corresponds to a ± 180 degree variation of the clock PCK.

Conventionally, since there is no dead zone for fluctuations of ± 180 degrees, the phase of the reproduced EFM signal S _EFM and the clock PLCK
Phase lock is applied only when the phase of
When jitter of ± 180 degrees occurs, locking cannot be performed in a stable state. This is because it is impossible to judge whether the phase is advanced or delayed with ± 180 degrees of jitter.

In contrast, in one embodiment of the invention, when also the phase of the clock PLCK of the reproduced EFM signal S _EFM is 180 degrees sly ±, a phase locked consuming. Therefore, ±
Even when jitter of 180 degrees is included, the phase lock is applied and the error rate can be improved even for a disc with poor asymmetry.

In Figure 1, the phase difference measuring circuit 1, the phase correction data obtained by measuring the phase difference between the reproduced EFM signal S _EFM phase and clock PLCK phase is output as described above. This phase correction data is supplied to the adder 5.

The frequency difference measuring circuit 2 includes an edge differentiating circuit 10, a ΔT measuring counter 11, an N detection counter 12, a frequency error amount conversion ROM 13, and a low-pass filter 14.

The reproduced EFM signal S _EFM from the input terminal 4 is the edge differentiator 1
Supplied to 0. The edge differentiating circuit 10 detects a change point of the reproduced EFM signal. The output of the edge differentiating circuit 10 is ΔT
Supplied to the measurement counter 11 and an N detection counter
Supplied to 12.

The system clock SCK is supplied from the terminal 8 to the ΔT measurement counter 11 as a measurement clock. The ΔT measurement counter 11 counts the system clock SCK between the changing points of the reproduced EFM signal _SEFM .

The output of the ΔT measurement counter 11 is supplied to the N detection counter 12. Since the system clock SCK is eight times the clock PLCK, the ΔT measurement counter 11 counts eight system clocks SCK during the 1T pattern. Δ
Every time the T measurement counter 11 counts eight system clocks SCK, the N detection counter 12 counts up. From the output of the N detection counter 12, the reproduction EF
The pattern of the M signal is detected.

The output of the ΔT measurement counter 11 and the output of the N detection counter 12 are supplied to a frequency error amount conversion ROM 13. As shown in FIG. 6, the frequency error amount conversion ROM 13 stores frequency correction data corresponding to the frequency difference for each pattern. The frequency correction data stored in the frequency error amount conversion ROM 13 is set by weighting according to the ratio of the time axis variation for each pattern with respect to the error of the predetermined clock. However, as described later in detail, in the case of the 3T pattern, the weighting is not followed in this manner. That is, in the 3T pattern, a point where the output of the ΔT measurement counter 11 becomes “3” or “5” is a dead zone. Also,
The frequency correction data at the point where the output of the ΔT measurement counter 11 becomes “2” or “6” is smaller than the theoretical value. This is to prevent the error rate from deteriorating with the 3T pattern in the case of a disc with poor asymmetry.

Frequency correction data is read from the frequency error amount conversion ROM 13 according to the output of the ΔT measurement counter 11 and the output of the N detection counter 12. This frequency correction data is supplied to the adder 5 via the low-pass filter 14.

As shown in FIG. 7, the reproduced EFM signal S _EFM change point t ₁₁ of the data, at ΔT measurement counter 11, the system clock SCK (FIG. 7 A) causes the count. The ΔT measurement counter 11 counts the system clock SKC for eight clocks from 0 to 7 (corresponding to one cycle of the clock PLCK). Each time the ΔT measurement counter 11 counts eight system clocks SCK, the N detection counter 12 counts up as shown in FIG. 7D. This N
From the output of the detection counter 12, a pattern of the reproduced EFM signal is detected. Then, at the change point t ₁₂ of the next reproduced EFM signal S _EFM data output of the output and N detection counter 12 of ΔT measurement counter 11 is taken in the frequency error quantity conversion ROM 13.

If no frequency error, as shown in FIG. 7 C, the output of ΔT measurement counter 11 at the transition point t ₁₂ of the next data is "0".

On the other hand, when the frequency of the reproduced EFM signal S _EFM becomes lower, as shown in FIG. 8C, the data change point t ₁₁ K
The number of the system clock SCK is counted until a change point t ₁₂ of the next mud is greater than a multiple of 8. In FIG. 8C, the output of the ΔT measurement counter 11 is “2”. When the output of the N detection counter 12 is a 3T pattern and the output of the ΔT measurement counter 11 is “2”, the output of the frequency error amount conversion ROM 13 becomes “38” as shown in FIG. When the output of the frequency error amount conversion ROM 13 is positive, the phase of the digitally controlled oscillator 3 is advanced.

Further, as the frequency becomes higher, as shown in FIG. 9 C, the number of the system clock SCK is counted between the transition points t ₁₁ the data until the change point t ₁₂ of the next data 8
Less than a multiple of. In FIG. 9C, the output of the ΔT measurement counter 11 is “6”. When the output of the N detection counter 12 is a 3T pattern and the output of the ΔT measurement counter 11 is “6”, the output of the frequency error amount conversion RCM 13 becomes “−38” as shown in FIG. When the output of the frequency error amount converter RCM13 is negative, the phase of the digitally controlled oscillator 3 is delayed.

Therefore, the frequency of the digitally controlled oscillator 3 is controlled so that the output of the ΔT measurement counter 11 becomes “0”.

By the way, the frequency error amount per cycle can be obtained by dividing the count value obtained by the ΔT measurement counter 11 by the number of patterns, and weighting based on this is used to obtain frequency correction data. The frequency correction data of a large value (for example, “63”, “−63”) is set for the points where “3” and “5” become.
However, with the 3T pattern, the ΔT measurement counter
By storing the frequency correction data at the point where the output of 11 becomes "3" or "5", if a large jitter is generated on a disk with poor asymmetry, the frequency error amount conversion RCM13 constantly outputs a large value of frequency. The correction data is output, and the digitally controlled oscillator 3 becomes unstable.

Therefore, in one embodiment of the present invention, in the 3T pattern,
A dead zone is provided for time axis fluctuations of ± 3 clocks. In the 3T pattern, the frequency correction data for the fluctuation of ± 2 clocks is reduced. For this reason,
In the case of a disk with poor asymmetry, if a large frequency variation occurs in the 3T pattern, the oscillation frequency of the digitally controlled oscillator 3 is not changed, and the digitally controlled oscillator 3 is stabilized, and the error rate is improved.

In FIG. 1, the adder 5 adds the phase difference data from the phase difference measurement circuit 1 and the frequency difference data from the frequency difference measurement circuit 2. The output of the adder 5 is supplied to the digitally controlled oscillator 3. The frequency of the digitally controlled oscillator 3 is controlled according to the data from the adder 5.

〔The invention's effect〕

According to the present invention, in the 3T pattern, a dead zone is provided for the time axis fluctuation of ± 3 clocks, and the frequency correction data for the fluctuation of ± 2 clocks is reduced. Therefore, even in the case of a disk having poor asymmetry, the oscillation frequency of the digitally controlled oscillator 3 is stabilized, and
Error rate can be improved.

FIG. 10 shows an error rate when a disk with poor asymmetry is reproduced by a compact disk player using a conventional digital PLL, and FIG. 11 shows a digital PLL to which the present invention is applied.
3 shows an error rate when the data is reproduced by a compact disk player using the. 10 and 11, the horizontal axis indicates time, and the vertical axis indicates an error rate. E1
Is a block error, and E2 is an error that cannot be corrected and is interpolated.

Conventionally, as shown in FIG. 10, many errors have occurred particularly in the space between songs and in the TOC. When this invention is applied,
As shown in FIG. 11, errors hardly occur.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIGS. 2 to 5 are timing diagrams used to explain phase control in one embodiment of the present invention, and FIG. 6 is a frequency diagram in one embodiment of the present invention. 7 to 9 are timing charts used for explaining frequency control in one embodiment of the present invention, and FIGS. 10 and 11 are graphs showing the effect of the present invention. . Explanation of main symbols in the drawings 1: phase difference measurement circuit, 2: frequency difference measurement circuit, 3: digitally controlled oscillator, 11: ΔT measurement counter, 12: N detection counter, 13: frequency error amount conversion ROM.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/06-7/199 G11B 20/14

Claims (2)

(57) [Claims] 1. A phase difference measuring means for measuring a phase difference between a phase of an oscillation output of a digitally controlled oscillator and a phase of an input signal; and a frequency measuring means for measuring a frequency difference of the input signal. In a digital PLL configured to control the digitally controlled oscillator based on a phase difference and the frequency difference, the frequency difference measuring unit measures a pattern of the input signal, and measures a period of the input signal. Cycle measuring means, and converting means for obtaining frequency correction data from the pattern of the input signal detected by the pattern detecting means and the cycle of the input signal detected by the cycle measuring means. A digital PLL characterized by setting a dead zone for short patterns. 2. The apparatus according to claim 1, wherein said converting means comprises a memory for storing frequency correction data formed by weighting in correspondence with said period and said pattern, wherein said weight of a short pattern is reduced. The digital PLL according to claim 1, wherein: