JPH08149418A - Synchronizing signal detector for disk reproducing device - Google Patents

Abstract

PURPOSE: To output the detected synchronizing signal as much as possible even if a clock has the jitters when the defect of the synchronizing signal is compensated. CONSTITUTION: When a counter 3 of a count device 5 counts the clocks synchronized with a reproduced signal up to (N + K) clocks, a decoder 4 generates the output DT. A detected synchronizing signal SYNC and the output DT clear the counter 3 via a composing circuit 6. Then the signal SYNC and the output DT are taken out as an output synchronizing signal WSYNC via a synchronizing circuit 8. In a normal operation mode, the counter 3 is cleared by the signal SYNC before the output DT is generated and the SYNC is adopted as an output via a shift register 7. When the SYNC is missed, the synchronizing signal is compensated by the output DT of the decoder 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal detecting device provided in a disk reproducing device, and more particularly to a device for compensating for a missing sync signal.

[0002]

2. Description of the Related Art In an optical disk such as a recordable optical disk, a sector synchronization signal and an address are preformatted on the disk for each sector. By reproducing the sector synchronization signal and the address, data is recorded on the disc and the data is reproduced from the disc. A specific bit pattern of the sector synchronization signal is detected from the reproduction signal, and the detected output is used as the reproduction synchronization signal. The recording start position on the disc can be defined by the reproduction synchronization signal.

When the reproduction signal disappears or an error occurs in the reproduction signal due to a scratch on the disk, the sector synchronization signal cannot be detected and the sector synchronization signal may be lost. In this case, it is necessary to compensate (also called interpolation or interpolation) the missing sector synchronization signal. Conventionally, as shown in FIG. 12, a 16-bit counter 3
When the number of data in one sector is set to N bits by the decoder 51 and the decoder 51, a counter device 52 that counts N clocks (frequency of a bit clock synchronized with the reproduction signal) makes one round, and a pseudo synchronization signal DT for compensation ´
Is generated, and the missing sector synchronization signal is interpolated by this DT '.

That is, the synchronizing signal SYNC detected from the reproduced signal is supplied to the input terminal 1, and the 16-bit counter 3 outputs the input synchronizing signal SYNC and the output DT of the decoder 51.
Is cleared by the output signal of the synthesis circuit 6 supplied with
The output synchronizing signal WSYNC is taken out to the output terminal 2 from the combining circuit 8 to which the input synchronizing signal SYNC and the output DT 'are supplied.

In the above structure, the synthesis circuits 6 and 8
Is configured to preferentially output what was input in advance. Therefore, as shown in FIG. 13, when the output DT 'of the decoder 51 occurs at the same time as or slightly behind the input synchronization signal SYNC, the counter 3 is cleared by the input synchronization signal SYNC and the input synchronization signal SYNC is It is output as the output synchronization signal WSYNC.

[0006]

The clock counted by the counter 3 is formed by the PLL so as to be synchronized with the reproduction signal. However, the performance of the PLL, track jump, and
The clock cannot be perfectly synchronized due to disturbances such as uneven rotation, and the clock has temporal fluctuation (jitter). As a result, a phase shift occurs between the output DT 'and the input synchronization signal SYNC which are generated when N clocks are counted. For example, when the frequency of the clock is slightly higher than the frequency of the bit clock of the reproduction signal and the timing of the output DT 'of the decoder 51 is earlier than the timing of the input synchronization signal SYNC, as shown in FIG. 14, DT'.
Then, the counter 3 is cleared and DT 'is output as the output synchronization signal WSYNC.

In this way, the detected original synchronization signal S
Even if YNC is not missing, it is ignored. Therefore, if the timing of the recording process is defined based on the output synchronization signal WSYNC, the discrepancy between the portion to be recorded and the portion to be actually recorded is on the disc. Occurs in In order to absorb this shift, a gap is defined between recorded data units (called clusters) in the format. Since a long gap leads to a decrease in recording density, it is preferable that the gap is as short as possible.

Therefore, an object of the present invention is to allow the detected sync signal to be outputted as much as possible while allowing a slight time difference between the detected sync signal and the generated sync signal for compensation. An object of the present invention is to provide a sync signal detecting device for a reproducing device.

[0009]

SUMMARY OF THE INVENTION According to the present invention, in a sync signal detecting apparatus for a disk reproducing apparatus in which a digital signal to which a synchronizing signal is added for every N of data to be recorded / reproduced is recorded, synchronization is performed from the reproduced signal. A synchronization signal detection circuit for detecting a signal, a counting device for counting a clock synchronized with the reproduction signal, reset by an input synchronization signal from the synchronization signal detection circuit, and making a round with N + K (K is an arbitrary natural number) clocks, When the input sync signal is missing, N
And a circuit for interpolating an input synchronizing signal missing due to a signal generated by a counting device at a timing of every + K, which is a synchronizing signal detecting device for a disc reproducing apparatus.

[0010]

The counter is cleared by the input synchronizing signal SYNC, and when the N + K clocks are counted, the output signal DT is generated. Input sync signal SYNC and output signal D
The output combined with T clears the counting device. Therefore, in the normal operation in which there is no defect in the synchronizing signal, the counting device is cleared by the input synchronizing signal SYNC. The input sync signal SYNC is delayed by K clocks, and the delayed SYNC
C and the signal DT are supplied to the synthesizing circuit, and the output synchronizing signal WSYNC is obtained from the synthesizing circuit. During normal operation, even if the clock has jitter, the K clock absorbs this jitter and outputs the input synchronization signal SYNC.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic configuration of a synchronizing signal detecting device according to the present invention. From the input terminal shown by 1,
An input synchronization signal SYNC detected from the signal read from the disc is supplied. Reference numeral 3 is a 16-bit counter that counts the clock extracted from the read signal, and reference numeral 4 is a decoder to which the count value of the counter 3 is supplied. The counter 3 and the decoder 4 constitute a counting device 5 that makes a cycle of (N + K) times.

Input synchronization signal SYNC and counting device 5
The output DT of (decoder 4) is supplied to the synthesis circuit 6,
The output of the synthesis circuit 6 clears the counter 3. Further, the input synchronization signal SYNC is supplied to the K-stage shift register 7, the signal delayed by K clocks by the shift register 7 is supplied to the combining circuit 8, and the output DT of the decoder 4 is supplied.
Is synthesized with The output synchronizing signal WSYNC is taken out from the synthesizing circuit 8 to the output terminal 2. The synthesis circuits 6 and 8 are
The one input earlier in time is given priority and output.

As shown in FIG. 2, when the accuracy of the clock counted by the counter 3 is high, the input synchronization signal SYNC clears the counter 3 before the output DT is generated.
It is output as the output synchronization signal WSYNC. Decoder 4
Is cleared before K clocks, so DT is not output. Further, as shown in FIG. 3, when the timing at which the output DT is generated is earlier because the clock counted by the counting device 5 has jitter, in other words, when the input synchronization signal SYNC is slightly behind the DT. If the phase difference between the input synchronization signal SYNC and DT is within K clocks, the counter 3 is cleared by the input synchronization signal SYNC. Therefore, similarly to the operation of FIG. 2, the output DT is not generated from the decoder 4, and the input synchronization signal SYNC that has passed through the shift register 7 is output as the output synchronization signal WSYNC. 2 and 3, the broken line intervals represent clock timings. Therefore, here, K = 1 (clock).

If the clock has a large jitter and the phase exceeds K clocks as compared with the input synchronizing signal SYNC,
When the counting device 5 quickly generates DT, the counter 3 is cleared by the signal DT, and the signal DT is taken out as the output synchronization signal WSYNC. Further, even when the input synchronization signal SYNC is missing, the signal DT is adopted as the output synchronization signal WSYNC. Although the value of K can be arbitrarily selected, increasing K allows a large degree of synchronization loss. Therefore, in practice, K is selected to be about 1 clock or 2 clocks.

An embodiment of the present invention will be described more specifically. In FIG. 4, reference numeral 11 denotes a recordable optical disc such as a CLV (constant linear velocity) system, such as a magneto-optical disc. This invention is a CAV (constant angular velocity),
It can also be applied to a disc of a system such as zone CAV (variable data rate for each zone).

The disk 11 is rotated by a spindle motor 12, and an optical pickup 13 records / reproduces digital data (digital audio data, digital video data, MPEG type video and audio data, etc.) on the disk 11. . Although not shown, a control circuit for the spindle motor 12 is provided, and a mechanism for moving the disc 11 or the pickup 13 is provided so that the pickup 13 can move in the radial direction of the disc 11.

On the disk 11, as shown in FIGS. 5 and 6, in the step of injection molding a disk substrate,
The pre-groove G is formed in a spiral shape. In FIG. 5, where data can be recorded in the land portion or groove of the pre-groove G, R is the disc radial direction, and S is the disc rotation direction. The pre-groove G is wobbled so as to have undulations in the disc radial direction R, that is, in the amplitude direction. This waviness is formed by a sine wave signal having a predetermined frequency. The rotation of the spindle motor 12 is controlled and the disk 11 is rotated at CLV so that the frequency of the reproduction signal obtained by scanning the wobbling pregroove with the light spot becomes a predetermined frequency.

Further, when wobbling the pre-groove G, the sector synchronization signal and the address signal are FM-modulated by the sector synchronization signal and the address signal, and the biphase-modulated signal is superposed on the sine wave so that the sector synchronization signal and the address are distributed over the entire disc. Recording the signal. One sector is, for example, 98 frames, and a synchronization signal is inserted at a sector cycle. The sector sync signal indicates the start and end of the recording area on the disc. Further, the cluster, which is a unit of the amount of data to be recorded, is 36 sectors. The address information is, for example, a time code,
Specify the position on the disc. Although not shown, a digital signal processing system, a tracking servo circuit of a pickup, a focus servo circuit, a system controller for controlling the operation of the reproducing apparatus, and the like are provided.

The reproduced signal read by the pickup 13 is supplied to another RF processing system, and the FM demodulation circuit 1 is passed through the bandpass filter 14 and the limiter 15.
6. The FM demodulation circuit 16 can obtain a sector synchronization signal and an address to be superimposed as wobbling information of the pre-groove G. A low-pass filter 17 for removing unnecessary signal components is connected to the FM demodulation circuit 16. The data obtained from the low-pass filter 17 is, for example, biphase-modulated.

The output signal of the low-pass filter 17 is a PLL.
18 and the synchronization signal detection circuit 19. The synchronization signal SYNC detected by the synchronization signal detection circuit 19 is supplied to the compensation circuit 20, and the synchronization signal SYNC and data are supplied to the separation circuit 21. In the separation circuit 21, the output synchronization signal WSYN supplied from the compensation circuit 20.
Use the window formed from C to correct the next period sync signal contained within the width of the window,
Further, the data (address) and the sync signal WSYNC are separated.

The separated data is supplied to the demodulation circuit 22 for biphase modulation, and the demodulation output is taken out. The separated synchronization signal WSYNC is supplied to the timing generation circuit 23. The timing generation circuit 23 includes the demodulation circuit 22.
To generate a timing signal necessary for processing a reproduction signal such as a timing signal and a clock WCLK. Note that P
The clock CLK formed by the LL 18 is supplied to the synchronization signal detection circuit 19, the compensation circuit 20, the demodulation circuit 22, and the timing generation circuit 23.

The present invention is applied to the synchronizing signal detecting circuit 19 and the compensating circuit 20, and a more specific structure in the case of (K = 1) is shown in FIG. Sync signal detection circuit 19
Is composed of comparison circuits 31 and 32, and detects a prescribed bit pattern from the FM demodulation output from the low pass filter 17. As an example, the comparison circuit 31 uses (11101
000) bit pattern, and the comparison circuit 32 detects
(00010111) is detected. These bit patterns do not appear in the biphase-modulated data. The detection output of the comparison circuits 31 and 32 is A
It is supplied to the ND gate 33. When one of the two bit patterns is detected, the AND gate 33 generates a detection signal of'L '.

The detection output of the AND gate 33 is used as the data input of the D flip-flop 34, and the data is synchronized with the clock (each part of the compensation circuit 20 operates with the clock CLK from the PLL 18). The input synchronizing signal from the D flip-flop 34 is supplied to the D flip-flop 41 and the AND gate 42 of the compensation circuit 20. This D flip-flop 41 delays (K = 1) clocks. The output of the D flip-flop 41 is taken out via the AND gate 43 as the output synchronizing signal WSYNC.

Reference numeral 44 denotes 1 for counting the clock CLK.
It is a 6-bit counter. The count value of the counter 44 is supplied to the comparison circuit 45. The comparison circuit 45 receives (MSB (most significant bit) ... LS as a reference input.
B (least significant bit) is (011000QQ ^) (QQ
^ Means the output Q of the JK flip-flop 47 and its inverted output Q ^). When the count value of the counter 44 coincides with this reference input, an output of'L 'is generated from the comparison circuit 45. The comparison circuit 45 corresponds to the decoder 4. Counter 44 and comparison circuit 45
A counting device is constituted by the.

The output DT of the comparison circuit 45 is the inverter 46.
Is input to the JK flip-flop 47 via
At the same time, the output of the inverter 46 is supplied to the AND gate 42 via the inverter 48. The input synchronization signal SYNC is supplied as the K input of the JK flip-flop 47 via the inverter 49. The output of the AND gate 42 is supplied to the clear terminal of the counter 44, and when the output of the AND gate 42 becomes “L”, the counter 44 is cleared. .

The operation of the compensation circuit 20 shown in FIG. 7 will be described below. First, when there is no defect in the input synchronization signal SYNC detected by the synchronization signal detection circuit 19, the compensation circuit 20
Operates as shown in the timing chart of FIG. The counter 44 counts the clock CLK from the PLL 18 which has been synchronized with the pre-groove signal since it was previously cleared, and if the input synchronization signal SYNC is not defective, the comparison circuit 45 generates a count value [Xc = 98. ]
AN with a count value [Xc = 97] one clock earlier than
It is cleared by the next input synchronization signal SYNC via the D gate 42. Thus, the count value Xc is [98]
Since the counter 44 is cleared before reaching, the output signal DT of the comparison circuit 45 is not generated.

In this case, the JK flip-flop 47
Output is Q = 'L', Q ^ = 'H', and the comparison circuit 45 receives 8 of (01100010) as a reference input.
Bits (ie, [98]) are given. FIG.
0 indicates the operation of the JK flip-flop 47 when there is no defect in the synchronization signal. The flip-flop 47 is
Since the clock CLK is inverted and supplied, it operates at the falling edge of the clock. When the output (J input) of the inverter 46 is'L 'and the output (K input) of the inverter 49 is'L', the state of (Q = 'L', Q ^ = 'H') does not change. When the synchronization signal SYNC is generated, the K input becomes'H 'and (Q =' L ', Q ^ =' H ').
This is the same as before. After that, the J and K inputs are both “L”, and the output does not change.

When the sync signal is defective and cannot be detected as shown in FIG. 9, when the count value Xc of the counter 44 reaches the reference input value [98],
The output DT is generated from the comparison circuit 45, which clears the counter 44. Therefore, the AND gate 43
The output synchronization signal WSYNC from is interpolated by the output DT of the comparison circuit 45.

Once the interpolation is done, then the counter 44
When the count operation is performed, the reference input value is [98].
If it is left as it is, when the next synchronization signal SYNC is also lost, the timing at which the counter 44 is cleared by the output DT of the comparison circuit 45 is delayed by two clock cycles with respect to the timing of the synchronization signal to be originally detected. Synchronization signal SYN
During the period in which the loss of C continues, this delay accumulates, causing a problem that the phase shift of the interpolation output becomes large. In this embodiment, such a problem is solved by supplying the output of the JK flip-flop 47 to the lower 2 bits of the reference input of the comparison circuit 45.

FIG. 11 shows the operation of the JK flip-flop 47 when the missing sync signal is interpolated. When both the J input (that is, the output of the inverter 46) and the K input (that is, the output of the inverter 49) are'L ', the output does not change, and Q =' L 'and Q ^ =' H '. . Then, the synchronization signal SYNC is lost and the comparison circuit 45
When the output DT of becomes "L", the J input becomes "H",
As a result, Q = 'H' and Q ^ = 'L'. After this, the J and K inputs are'L 'and the state does not change. However, if the synchronization signal SYNC is detected after that,
The K input becomes'H 'and the output Q becomes'L'.

The output of the flip-flop 47 is (Q =
'H', Q ^ = 'L'), the reference input to the comparison circuit 45 changes to (01100001), and as described above, the output DT of the comparison circuit 45 has the count value Xc.
Reaches the changed reference input value [97], 'L'
Becomes As a result, the set value is decremented by 1, and the timing of the interpolated sync signal can be prevented from being delayed from the original timing. Further, the output Q of the JK flip-flop 47 is output as a status signal WCOP indicating whether or not the synchronization signal has been compensated. This status signal WCOP can be used to perform processing such as prohibiting recording on the disc.

The above embodiment is an example in which the sync signal is recorded as a pregroove signal on the disc, but the present invention is not limited to this, and preformatted as prepits at predetermined positions on the track. But good. Further, the present invention can be applied to a phase-change type optical disc, and can be applied not only to an optical disc but also to a magnetic disc. The present invention can also be applied as a sync signal detecting device in a disc reproducing system.

[0033]

As described above, according to the present invention, the counting device that makes one cycle with N + K clocks is provided and the counting device is cleared by the detected synchronizing signal and the output of the counting device.
Even if the clock to be counted includes jitter, the ratio of the detected sync signal output can be increased in normal operation. Therefore, in the recordable disc, the margin for absorbing the phase shift of the synchronization signal can be further reduced, and the recording density can be improved. As an example,
In the example of K = 1, this margin can be reduced to 10%.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a synchronization signal detecting device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the basic configuration of the synchronization signal detection device according to the present invention.

FIG. 3 is a timing chart for explaining the operation of the basic configuration of the synchronization signal detecting device according to the present invention.

FIG. 4 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 5 is an enlarged view of a part of the pre-groove formed on the disc in the embodiment of the present invention.

FIG. 6 is a schematic diagram showing a pre-groove formed on a disc according to an embodiment of the present invention.

FIG. 7 is a block diagram of an embodiment of the present invention.

FIG. 8 is a timing chart showing an operation when a sync signal can be detected in the embodiment of the present invention.

FIG. 9 is a timing chart showing an operation when the synchronization signal is interpolated in the embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the JK flip-flop according to the embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the JK flip-flop according to the embodiment of the present invention.

FIG. 12 is a block diagram showing a basic configuration of a conventional synchronization signal detection device.

FIG. 13 is a timing chart showing an operation of a basic configuration of a conventional synchronization signal detection device.

FIG. 14 is a timing chart showing an operation of a basic configuration of a conventional synchronization signal detection device.

[Explanation of symbols]

 1 Detected sync signal input terminal 2 Compensated sync signal output terminal 3 Counter 4 Decoder 5 Counter that makes a loop with N + K 7 Shift register 44 Counter 45 Comparison circuit 47 JK flip-flop

Claims (4)

[Claims] 1. A synchronization signal detecting device for a reproduction device of a disc in which a digital signal to which a synchronization signal is added for every N of data to be recorded / reproduced is recorded, for detecting the synchronization signal from the reproduction signal. Means for counting clocks synchronized with the reproduction signal, resetting by an input synchronization signal from the synchronization signal detection means, and making a cycle of N + K (K is an arbitrary natural number) clock, and the input synchronization signal A synchronizing signal detecting device for a disc reproducing apparatus, comprising means for interpolating a missing input synchronizing signal by a signal generated by the counting means at the timing of every N + K when it is missing. 2. The synchronizing signal detecting device according to claim 1, further comprising a combining means for combining and outputting the input synchronizing signal that has passed through the delay means for delaying the K clock and the output of the counting means. A synchronization signal detecting device having. 3. The synchronization signal detecting device according to claim 1, further comprising means for changing the number of clocks cycled by the counting means to N when the synchronization signal is interpolated. Sync signal detector. 4. The synchronization signal detecting device according to claim 1, wherein the disc is a recordable disc, and the synchronization signal is previously recorded on the disc.