JP2001148161A - Jitter suppressing circuit, and data reproducing circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a jitter-suppressing circuit which can reduce influence of jitter of an input signal and can supply a stable clock signal, and a data- reproducing circuit using it. SOLUTION: A clock signal PL-CLK is generated by a PLL circuit 100 according to an input signal RF-IN, delay signals of N lines are outputted by a delay circuit 130 consisting of delay elements of N stages, delay signals of N lines from the delay circuit 130 are latched in accordance with a rice edge of a signal RF-DAT to which the input signal RF-IN is delayed, latch data LDAT of N bits is outputted, edge data EDAT reflecting jitter quantity of the input signal RF-IN is outputted by a binary conversion circuit 150 according to this, an average value of edge data EDAT in the prescribed value is calculated by an adder 160, a latch circuit 170, and a divider 180, and a delay circuit 120 selects one of delay signals of N lines of the delay circuit 130 according to the average value and outputs it as a clock signal CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter suppressing circuit for suppressing a jitter contained in a clock signal generated by using a PLL circuit or the like in response to an input signal containing the jitter, and a jitter suppressing circuit for controlling the jitter. The present invention relates to a data reproducing circuit that reproduces data from, for example, the binary input signal using a clock signal in which is suppressed.

[0002]

2. Description of the Related Art For example, a binary input signal having a phase error (jitter) is used as a reference signal by a PLL circuit so that the jitter is converged to the average value of low frequency components of the phase error with respect to the reference signal. A suppressed clock signal can be generated. The input signal is input to a CD (Compact Disk), DV,
This is a pickup signal read from a recording medium such as D (Digital Video Disk).

FIG. 6 is a circuit diagram showing a configuration example of a general PLL circuit. As shown, this PLL circuit 10
0 is a frequency comparison circuit (FD) 10 and a phase comparison circuit (P
D) 20, a low-pass filter (LPF) 30, and a voltage-controlled oscillation circuit (VCO) 40. P
LL circuit 100 uses input signal RF_IN as a reference signal, and generates transmission signal PL_
CLK is output.

[0004] The frequency comparison circuit 10 receives an input signal RF_I.
Comparing the frequency of the output signal PL_CLK N and VCO 40, and outputs the frequency error signal S _FD according to the result of comparison. Phase comparing circuit 20 compares the phases of the input signal RF_IN and output signal PL_CLK, and outputs a phase difference signal S _PD according to the result of comparison.

The low-pass filter 30 outputs a transmission control signal S _C for controlling the transmission frequency of the VCO 40 according to the frequency error signal S _FD from the frequency comparison circuit 10 and the phase difference signal S _PD from the phase comparison circuit 20. . VCO40
Controls the transmission frequency according to the transmission control signal S _C from the low-pass filter 30, and outputs the clock signal PL_CLK.

The above-described PLL circuit 100 suppresses a high-frequency phase error contained in the input signal RF_IN by the low-pass filter 30 provided as a loop filter.
The frequency of LK is controlled depending on the average value of the low frequency components of the input signal RF_IN. Therefore, the PLL circuit 10
A value of 0 can sufficiently cope with a low frequency deviation or phase deviation of the input signal RF_IN.

[0007]

Incidentally, the above-mentioned general PLL circuit cannot sufficiently cope with a medium-high frequency component of the frequency deviation of the input signal RF_IN. In this case, if the frequency characteristics of the low-pass filter are forcibly adjusted to the high-frequency side in an attempt to follow the medium-to-high-frequency component of the frequency deviation of the input signal RF_IN, a problem such as phase rotation occurs, and the correct clock signal PL_CLK cannot be obtained. There is a benefit.

Normally, in a signal reproducing device such as a CD or DVD, the signal RF_IN is a pickup signal obtained by a reading device such as an optical pickup. For this reason, the signal RF_IN contains various frequency components due to servo fluctuation, eccentricity and distortion of the optical disk, in addition to the original EFM signal component. Since the PLL circuit generates the clock signal PL_CLK in accordance with the average value of the low frequency components of these error signals, it cannot sufficiently cope with various jitter components other than the original EFM signal components included in the input signal RF_IN. . For this reason, PL
It is difficult to correctly generate EFM modulated data from the input signal RF_IN using the clock signal PL_CLK generated by the L circuit. In particular, high-speed DVD
In such a reader, the influence of jitter is remarkable, so that it is increasingly difficult to generate data from a pickup signal.

The present invention has been made in view of the above circumstances, and has as its object to reduce the effects of input signal jitter, suppress high-frequency phase fluctuation components, and generate a stable clock signal. An object of the present invention is to provide a suppression circuit and a data reproduction circuit using the suppression circuit.

[0010]

In order to achieve the above object, a jitter suppressing circuit according to the present invention has a PLL circuit for generating a first clock signal based on a reproduction signal including reproduction data, and a predetermined delay time. N connected in series (N is 2
A first delay circuit including the above (natural number) number of delay elements and receiving the first clock signal; and reproducing the delay time about half the delay time included in the output signal of the Nth delay element. A second delay circuit for giving a signal and outputting it as a delay signal, and a selection circuit for selecting a predetermined one of the output signals of the N delay elements according to control data and outputting the selected signal as a second clock signal An edge detection circuit that latches each output signal of the N delay elements based on the second clock signal and the delay signal and outputs edge data corresponding to the latched data; And a control circuit for generating the control data in response.

In the jitter suppression circuit according to the present invention, the edge detection circuit latches each output signal of the N delay elements based on the second clock signal and the delay signal. Then, the latch data of the jitter detection circuit is converted into a binary signal and output as edge data. Further, in the jitter suppression circuit according to the present invention, the jitter detection circuit includes a first flip-flop that inputs the delay signal and the second clock signal to a data input terminal and a clock input terminal, respectively, A second flip-flop for inputting an output signal of the first flip-flop and the second clock signal to a data input terminal and a clock input terminal, respectively; and a delay signal and an output terminal of the second flip-flop. An exclusive-OR circuit for inputting, and latches the output signals of the N delay elements according to the output signal of the exclusive-OR circuit.

In the jitter suppressing circuit according to the present invention, the control circuit includes an adder for adding the edge data and the accumulated data stored in advance, and holding an output signal of the adder as integrated data. A latch circuit for supplying the adder with the latch circuit; a divider for dividing the integrated data held in the latch circuit to generate the control data; a latch circuit for counting the delay signal; And a counter for controlling the vessel.

A data reproducing circuit according to the present invention includes any one of the above-mentioned jitter suppressing circuits, the above-mentioned delay signal and the above-mentioned second clock signal inputted to a data input terminal and a clock input terminal, respectively. And an output flip-flop.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a jitter suppressing circuit and a data reproducing circuit using the same according to the present invention. As shown in the figure, the input signal RF_IN is input to the PLL circuit 100, and the clock signal P
L_CLK is generated. The jitter suppression circuit 200 of the present embodiment suppresses the jitter included in the clock signal PL_CLK generated by the PLL circuit 100, and supplies the data reproduction clock signal CLK to the D flip-flop 300. The jitter suppression circuit 200 includes a delay circuit 110, a selection circuit 120, a delay circuit 130, a jitter detection circuit 140, a binary conversion circuit 150, an adder 160, a latch circuit 170, a divider 180, and a loop counter 190.
It is constituted by.

The PLL circuit 100 has, for example, almost the same configuration as the general PLL circuit shown in FIG. That is, P
Using the input signal RF_IN as a reference signal, the LL circuit 100 controls the frequency of the clock signal PL_CLK according to the average value of the low frequency components of the jitter included in the signal RF_IN.

In the jitter suppressing circuit 200, each of the delay circuits 110 and 130 is a delay circuit in which a plurality of delay elements are connected in series. For example, the delay circuit 110 is composed of N / 2 (N is a natural number of 2 or more) delay elements having a delay time Δt, and the total delay time ΔT1 is Δ
t × N / 2. On the other hand, the delay circuit 130 is composed of N delay elements having the same time Δt, and the total delay time ΔT2 is Δt × N. Here, the number N of delay elements is set in the range of 8 to 32, and each delay element is configured by, for example, a CMOS inverter, and the delay time Δt is usually 0.1 to 0.3 ns (nanosecond). )
It is. As an example, the delay time of the delay element Δt = 0.2
Assuming that 5 ns and the number of delay elements N = 16, the delay circuit 11
0 is 2 ns, and the delay circuit 130
Is 4 ns.

The delay circuit 110 outputs a delay signal RF_DAT obtained by delaying the input signal RF_IN by the time ΔT1. The delay circuit 130 supplies N delay signals S _D1 , S _D2 ,..., S _DN output from each delay element to the selection circuit 120 and the jitter suppression circuit 140, respectively.

The selection circuit 120 selects one of the N delay signals S _D1 , S _D2 ,..., S _DN input from the delay circuit 130.
One is selected according to the output data of divider 180, and the selected delay signal is output as clock signal CLK.

The jitter detection circuit 140 includes a delay circuit 110
In response to the output signal RF_DAT and the clock signal CLK output from the selection circuit 120, and outputs N-bit data LDAT accordingly.

FIG. 2 is a circuit diagram showing a configuration of the jitter detection circuit 140. As shown, the jitter detection circuit 140
Are D flip-flops 140-1, 140-2,.
140-N, 142 and 143, an exclusive OR gate 144 and a buffer 145.

The output signal RF_DAT of the delay circuit 110 is input to one input terminal of the exclusive OR gate 144 and the data input terminal D of the D flip-flop 142. The clock signal CLK from the selection circuit 120 is D
The clocks are input to the clock input terminals of the flip-flops 142 and 143, respectively. An output signal from the output terminal Q of the D flip-flop 142 is input to the data input terminal D of the D flip-flop 143. D flip-flop 14
The three output signals are input to the other input terminal of the exclusive OR gate 144.

The output signal RF_CLK of the exclusive OR gate 144 is input to each of the clock input terminals of the D flip-flops 141-1, 141-2,..., 141-N via the buffer 145. D flip-flop 141-1 and 141-2, ..., to the data input terminal D of 141-N, N number of delay signals output from the delay circuit _{130 S D1, S D2, ...} , S DN is input You.

In the above-described jitter detection circuit 140,
The output signal RF_CLK of the exclusive OR gate 144 rises in response to the rising edge of the output signal RF_DAT of the delay circuit 110, and the output signal of the D flip-flop 143 goes to a high level during a period from then to the second rising edge of the clock signal CLK. Will be retained. That is, the exclusive OR gate 144 outputs a pulse signal RF_CLK having a width of 1 to 1.5 cycles of the clock signal CLK. Pulse signal RF_CL
In response to the rise of K, the output signal S of the delay circuit 130
_{D1, S D2, ..., S} DN the D flip-flop 141-1,
, 141-N. Therefore, the D flip-flops 141-1, 141-2,
, 141-N are divided into a continuous portion of data "0" and a continuous portion of data "1", and are switched between data "0" and "1". Points indicate positions of edges of the output signal RF_DAT of the delay circuit 110. That is, the latch data LDAT corresponds to the jitter included in the signal RF_DAT.

N obtained by the jitter detection circuit 140
Bit latch data LDAT is decoded by binary conversion circuit 150, and edge data EDAT is obtained. The edge data EDAT is stored in the edge position of the output signal RF_DAT of the delay circuit 110, that is, the delay circuit 1
10 is a numerical representation of the jitter of the ten output signals RF_DAT.

The binary conversion circuit 150 includes the jitter detection circuit 1
N-bit latch data LDAT obtained by
Into the edge data EDAT which is binary data,
This is supplied to the adder 160. That is, the binary conversion circuit 150
Is configured by a decoder, for example, and outputs edge data EDAT indicating the edge position of the output signal RF_DAT of the delay circuit 110 based on the N-bit latch obtained by the jitter detection circuit 140.

The edge data EDAT is input to the adder 160, and the addition data SDAT with the latch data SUM of the latch circuit 170 is obtained. The addition data SDAT is input to the latch circuit 170, and is held as new integrated data SUM. The integrated data SUM is subjected to a division operation with a predetermined constant by the divider 180, and a result SNRM of the division is output. Note that the division operation in the divider 180 is, for example, an operation of dividing the integrated data SUM by a value of a power of two, and is performed by a shift register.
This can be realized by shifting M to the right.

The division result S obtained by the divider 180
The NRM is input to the selection circuit 120, and accordingly,
The selection circuit 120 outputs N
One of the delay signals S _D1 , S _D2 ,..., S _DN is selected and output as a clock signal CLK.

The loop counter 190 includes a delay circuit 110
And outputs a reset signal to the latch circuit 170 and the divider 180 when the count value reaches a preset value. Latch circuit 170 is reset in response to a reset signal from loop counter 190, and integrated data SUM is reset to "0". On the other hand, the divider 180 responds to the integrated data SUM before being reset in response to the reset signal,
The division data SNRM is updated. Loop counter 190
, The latch circuit 170 controls the edge data ED in a predetermined cycle of the delay signal RF_DAT.
The AT is subjected to integration and averaging processing.

The clock signal CLK obtained by the jitter suppression circuit 200 is the delay signal R from the delay circuit 110.
The signal is input to the D flip-flop 300 together with F_DAT. D flip-flop 300 receives clock signal C
The signal RF_DAT at the timing set by the LK
Is sampled (sampled), and the sampled data is output as read data RDAT. Since the jitter suppression circuit 200 generates the clock signal CLK in which the high-frequency jitter component included in the clock signal PL_CLK generated by the PLL circuit 100 is suppressed, the output signal R of the delay circuit 110 is generated by the clock signal CLK.
As a result of sampling F_DAT, read data RDA
The error of T can be reduced.

FIG. 3 is a diagram showing input / output signals of the PLL circuit 100 and output signals and output data of the respective partial circuits in the jitter suppression circuit 200. Hereinafter, FIGS.
The operation of the jitter suppression circuit according to the present embodiment will be described with reference to FIG. The signal RF_IN shown in FIG.
Input to the circuit 100. Note that, as described above, the signal RF_IN is, for example, CD,
This is a pickup signal obtained from an optical recording medium such as a DVD. Here, assuming that the target period of the clock signal reproduced by the PLL circuit 100 and the jitter suppression circuit 200 is T, the period of the pickup signal RF_IN is 3T to
It is in the range of 14T.

In the PLL circuit 100, a clock signal PL_CLK shown in FIG. 3B is generated according to the input pickup signal RF_IN. As described above, the phase error of the clock signal PL_CLK generated by the PLL circuit 100 is different from the pickup signal RF_I
It converges to the average value of the low frequency components of the N phase errors. For this reason, the clock signal PL_CLK is
The phase error of the high frequency component included in F_IN, that is,
It is affected by jitter and contains phase errors of high frequency components.

The pickup signal RF_IN is supplied to the delay circuit 1
10, and a delayed signal RF_DAT delayed by (Δt × N / 2) is output (FIG. 3C). Also,
Clock signal PL reproduced by PLL circuit 100
_CLK is input to the delay circuit 130, and N delay signals S _D1 , S _D2 ,.
_{The DN} is obtained, and one delay signal selected according to the division result SNRM of the divider 180 by the selection circuit 120 is output as the clock signal CLK (FIG. 3D).

The delay signal RF_DAT and the clock signal C
LK is input to the jitter detection circuit 140. In the jitter detection circuit 140, a latch clock signal RF_CLK corresponding to the rising edge of the signal RF_DAT is generated, and the latch data LDAT (FIG.
(F)) is output. As shown in FIG. 3 (f), the latch data SDAT is, for example, 32-bit data. Of the 32 bits, a portion where data "0" is continuous and a portion where data "1" are continuous are included. is there. The transition point between the data “0” and the data “1” corresponds to the edge position of the signal RF_DAT, that is, the jitter amount of the pickup signal RF_IN.

The latch data LDAT is input to a binary conversion circuit 150 comprising a decoder, and the binary conversion circuit 150 outputs the binary data ED corresponding to the amount of jitter of RF_DAT.
AT (FIG. 3 (g)) is output. The adder 160 performs an addition operation on the binary data EDAT and the integrated data SUM of the latch circuit 170, and as a result of the addition, FIG.
The integrated data SDAT shown in (h) is obtained.

FIGS. 3F to 3J show latch data L
DAT, edge data EDAT, addition data SDAT,
An example of the integration data SUM and the division data SNRM is shown. As shown in the figure, for example, the number of bits N of the latch data LDAT is set to 32. That is, the 32-bit latch data LDA is
T is output.

At the rising edge of the latch clock signal RF_CLK, N delay signals S _{D1 to} S _DN output by the delay circuit 130 are latched, respectively.
The N-bit latch data LDAT shown in FIG. 3F is obtained. Here, it is assumed that the first 16 bits of the latch data LDAT are “0”, and the 17th and subsequent bits are “1”. That is, if it is described by hexadecimal data, LDAT =
“0000ffffh”. The latch data LD
Depending on the AT, by the binary conversion circuit 150, for example,
5-bit edge data EDAT is output. FIG.
As shown in (g), the edge data EDAT is described by hexadecimal data "11h". The edge data is data corresponding to the rising edge of the delay signal RF_DAT of the input signal RF_IN, and reflects the amount of jitter of the input signal RF_IN.

The edge data ED is added by the adder 160.
AT and integrated data SUM held in latch circuit 170
Is calculated. Here, the latch circuit 17
It is assumed that 0 is in a state immediately after resetting, that is, the integrated data SUM is “0”. Therefore, the addition data SDAT of the adder 160 is “011h”. The addition data is held as new addition data SUM by the latch circuit 170. In the divider 180,
Divided data SNR calculated based on previous integrated data
M is held. As shown in FIG. 3 (j), the divider 18
0 is divided data SNRM (“04” of hexadecimal data).
h ″) is held, and the selection circuit 120 responds accordingly.
Tap data TAP is set. One of the N delay signals S _{D1 to} S _DN obtained from the delay circuit 140 is selected and output according to the tap data TAP.

As described above, according to the present embodiment, the clock signal PL_CLK is generated by the PLL circuit 100 in accordance with the input signal RF_IN, and the time difference Δt is determined by the delay circuit 130 including N stages of delay elements. N delayed signals are output. The jitter detection circuit 140 outputs the signal RF obtained by delaying the input signal RF_IN.
In response to the rising edge of _DAT, N delay signals from delay circuit 130 are latched, N-bit latch data LDAT is output, and binary conversion circuit 150 outputs the edge of input signal RF_IN in response to latch data LDAT. The edge data EDAT corresponding to the position is output, and the average value of the edge data EDAT in a predetermined period is calculated by the adder 160, the latch circuit 170, and the divider 180. According to the average value, the selection circuit 120 delays. Since any one of the N output signals of the circuit 130 is selected and output as the clock signal CLK, the input signal R
The phase of the clock signal CLK is controlled according to the jitter of F_IN, the influence of the jitter included in the input signal can be suppressed, the increase in the circuit scale can be suppressed to a minimum, and the jitter can be reduced by a simple digital circuit. further,
The error rate of the reproduced data RDAT can be reduced by reproducing the data RDAT by sampling the delay signal RF_DAT using the clock signal CLK in which the jitter is suppressed.

Second Embodiment FIG. 4 is a circuit diagram showing a jitter suppression circuit and a data reproduction circuit using the same according to a second embodiment of the present invention. The jitter suppression circuit 200a of the present embodiment is
The jitter contained in the input signal RF_IN is suppressed in accordance with the clock signal PL_CLK generated by 0.
As illustrated, the jitter suppression circuit 200a includes a delay circuit 1
10a, selection circuit 120a, delay circuit 130a, jitter detection circuit 140a, binary conversion circuit 150, adder 16
0, a latch circuit 170, a divider 180, and a loop counter 190.

The PLL circuit 100 receives the input signal RF_IN
Is a reference signal, the output signal P is calculated according to the average value of the low-frequency components of the phase error included in the input signal RF_IN.
Controls the frequency of L_CLK.

In the jitter suppression circuit 200a, the delay circuits 110a and 130a each include a plurality of delay elements,
For example, a delay circuit in which N delay elements having a delay time Δt are connected in series. The delay signal RF_DL obtained by the delay element in the middle of the delay circuit 110a is supplied to the jitter detection circuit 140a and the loop counter 190, respectively. The delay signal obtained by the delay element in the middle of the delay circuit 130a is supplied to the jitter detection circuit 140a as the clock signal CLK, and is output to the outside. Output signals from the N delay elements constituting the delay circuit 110a are respectively supplied to the selection circuit 120a, and output signals from the N delay elements constituting the delay circuit 130a are respectively supplied to the jitter detection circuit 140a.

The number N of stages of the delay elements constituting the delay circuits 110a and 130a is, for example, in the range of 8 to 32, similarly to the delay circuit 130 in the jitter suppression circuit 200 of the first embodiment described above. , And each delay element is configured by, for example, a CMOS inverter, and the delay time Δt is usually 0.1 to 0.3 ns (nanosecond). As an example, the delay time Δt of the delay element =
Assuming that 0.25 ns and the number of delay elements N = 16, the maximum delay time ΔT of the delay circuits 110a and 130a is 4n
s. The delay signal RF_DL output from the intermediate delay element of the delay circuit 110a is the same as the input signal RF_I
This signal is delayed by about 2 ns with respect to N.

The selection circuit 120a selects one of N output signals from the N delay elements of the delay circuit 110a according to the division data SNRM from the divider 180,
The selected delay signal RF_DAT is output.

The jitter detection circuit 140a includes the delay circuit 11
The jitter is detected in accordance with the output signal RF_DL of 0a and the clock signal CLK output from the delay circuit 130a, and the N-bit data LDAT is output in response thereto. The jitter detection circuit 140a has a latch circuit that latches N delay signals supplied from the delay circuit 130a at a timing set by the delay signal RF_DL supplied from the delay circuit 110a. By the latch circuit, N indicating the position of the edge of the delay signal RF_DL
Bit latch data LDAT is output. Note that the jitter detection circuit 140a according to the present embodiment has substantially the same configuration as the jitter detection circuit 140 shown in FIG. However, in the edge detection circuit 140a according to the present embodiment,
A delay signal RF_DL is used instead of the delay signal RF_DAT shown in FIG.

The N-bit latch data LDAT obtained by the jitter detection circuit 140a is
By 0, it is converted into edge data EDAT indicating the edge position of the delay signal RF_DL. The adder 160 calculates the sum SDAT of the edge data EDAT and the integrated data SUM held in the latch circuit 170. The operation result SDAT of the adder 160 is held by the latch circuit 170 as new integrated data SUM.

The integrated data SUM held in the latch circuit 170 is subjected to a division operation with a preset constant by the divider 180, and the result SNRM of the division is output. Note that the division operation in the divider 180 is, for example, an operation of dividing the integrated data SUM by a power of 2 and can be easily realized by shifting the integrated data SUM to the right by a shift register.

Division result S obtained by divider 180
The NRM is input to the selection circuit 120a, and in response, the selection circuit 120a selects one of the N delay signals output by the delay circuit 110a, and
Output as _DAT. That is, the division result SNRM obtained by the divider 180 indicates the amount of jitter of the delay signal RF_DL output by the delay circuit 110a. For this reason, the selection circuit 120a selects one of the N output signals of the delay circuit 110a in the direction to suppress the jitter according to the calculated jitter amount SNRM, and outputs the selection signal RF_DAT. I do.

As described above, according to the jitter suppression circuit of the present embodiment, the jitter of the delay signal RF_DL of the input signal RF_IN is detected based on the clock signal PL_CLK generated by the PLL circuit 100 in accordance with the input signal RF_IN. Then, the data SNRM indicating the jitter amount is calculated. Then, according to the jitter amount, the input signal RF_
IN selects one of the delay signals obtained by the N delay elements and outputs a delay signal RF_DAT. Therefore, the amount of relative jitter between the delay signal RF_DAT and the clock signal CLK is reduced, and as shown in FIG.
Is input to the D flip-flop 300, the signal RF_DAT is sampled in accordance with the timing of the clock signal CLK, and the sample data is output as the read data RDAT, whereby the error rate of the read data RDAT can be reduced.

Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the jitter suppression circuit according to the present invention. As shown in the figure, the jitter suppression circuit of the present embodiment is configured by connecting the jitter suppression circuits 200-1 and 200-2 in series. Jitter suppression circuit 200-
1 and 200-2 are the jitter suppression circuits 200 or 20 according to the above-described first or second embodiment of the present invention, respectively.
0a.

Clock signal PL_CLK is generated by PLL circuit 100 in accordance with input signal RF_IN. Input signal RF_IN and clock signal PL_CLK
Is input to the first stage jitter suppression circuit 200-1. The first-stage jitter suppression circuit 200-1 outputs a delay signal RF_D1 and a clock signal CLK1 in which the jitter contained in the delay signal RF_IN or the clock signal CLK is suppressed in accordance with the input signal RF_IN and the clock signal PL_CLK, Next-stage jitter suppression circuit 200
-2.

In the jitter suppression circuit 200-2, the delay signal R input from the first stage jitter suppression circuit 200-1
According to F_D1 and the clock signal CLK1, further,
A delay signal RF_DAT and a clock signal CLK in which jitter has been suppressed are generated and output.

As described above, in this embodiment, by connecting the jitter suppression circuits in two stages in series, for example, a plurality of jitters having different frequency bands can be suppressed by the respective jitter suppression circuits. , The input signal RF is higher than when only one stage of the jitter suppression circuit is used.
Jitter contained in _IN can be more effectively suppressed. Therefore, according to the timing of the clock signal CLK obtained from the second-stage jitter suppression circuit 200-2,
By sampling the delay signal RF_DAT output from the jitter suppression circuit 200-2 at the stage, the error rate of the reproduction data RDAT can be suppressed to be low.

[0053]

As described above, according to the jitter suppressing circuit of the present invention and the data reproducing circuit using the same, the DV
High frequency band jitter contained in a pickup signal from an optical recording medium such as D can be suppressed, and the density of the recording medium and the speed of the reading device can be further increased. Further, according to the present invention, a jitter suppression circuit can be constituted by a digital logic circuit and a simple arithmetic circuit with respect to a conventional jitter suppression circuit by an analog circuit, and the jitter can be effectively suppressed by a simple circuit configuration, and reproduction can be performed. The data error rate can be reduced. Further, since the amount of jitter can be obtained as a digital amount, there is an advantage that circuit calibration and the like can be easily performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a jitter suppression circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a jitter detection circuit of the jitter suppression circuit shown in FIG.

FIG. 3 is a waveform chart showing an operation of the jitter suppression circuit.

FIG. 4 is a circuit diagram showing a jitter suppression circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the jitter suppression circuit according to the present invention.

FIG. 6 is a block diagram illustrating a configuration example of a conventional PLL circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Frequency comparison circuit, 20 ... Phase comparison circuit, 30 ... Low-pass filter, 40 ... Voltage control oscillation circuit (VCO), 100 ... PLL circuit, 110, 110a ... Delay circuit, 120, 120a ... Selection circuit, 130, 130a ... Delay circuit, 140, 140a: Jitter detection circuit, 150: Binary conversion circuit, 160: Adder, 170: Latch circuit, 180: Divider, 190: Loop counter, 200, 200a, 200-1, 200-2 ... Jitter suppression circuit, 300 ... D flip-flop.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (5)

[Claims] 1. A PLL circuit for generating a first clock signal based on a reproduction signal including reproduction data, and N (N is a natural number of 2 or more) serially connected delay elements having a predetermined delay time A first delay circuit for inputting the first clock signal, and a second delay circuit for providing a delay time of about half of a delay time included in an output signal of the Nth delay element to the reproduction signal and outputting the same as a delay signal. A delay circuit, a selection circuit for selecting a predetermined one of the output signals of the N delay elements according to control data and outputting the selected signal as a second clock signal, An edge detection circuit that latches each output signal of the N delay elements based on the delay signal and outputs edge data according to the latched data; and generates the control data according to the edge data. Jitter suppression circuit having a control circuit. 2. The jitter detection circuit according to claim 1, wherein said edge detection circuit latches each output signal of said N delay elements based on said second clock signal and said delay signal. And a binary conversion circuit for converting the data into a binary signal and outputting it as edge data.
3. The jitter suppression circuit according to claim 1. A first flip-flop for inputting the delay signal and the second clock signal to a data input terminal and a clock input terminal, respectively; and an output of the first flip-flop. Signal and the second
A second flip-flop for inputting the clock signal to the data input terminal and the clock input terminal, respectively, and an exclusive OR circuit for inputting the delay signal and the output terminal of the second flip-flop. 3. The jitter suppression circuit according to claim 2, wherein output signals of said N delay elements are latched according to output signals of said exclusive OR circuit. 4. The control circuit according to claim 1, wherein said control circuit includes an adder for adding said edge data and prestored integrated data, and a latch circuit for storing an output signal of said adder as integrated data and supplying the integrated signal to said adder. A divider for dividing the integrated data held in the latch circuit to generate the control data, and a counter for counting the delay signal and controlling the latch circuit and the divider. Item 4. The jitter suppression circuit according to any one of Items 1, 2, and 3. 5. A data reproduction circuit, comprising: inputting the delay signal and the second clock signal to a data input terminal and a clock input terminal, respectively; A data reproduction circuit including a flip-flop that outputs a signal.