JPH03289820A - Digital pll - Google Patents

Abstract

PURPOSE:To improve an error rate of even a disk with poor symmetry by setting a dead band in the vicinity of a phase difference of + or -180 deg. between a phase of an oscillated output of a digital control oscillator and a phase of an input signal. CONSTITUTION:A phase difference measuring counter 1 measures a phase difference between a phase of an output clock PLCK of a digital control oscillator 3 and a phase of a reproduced EFM signal SEFM by using a system clock SCK. Suppose that the symmetry of a disk is bad and jitter of, e.g. + or -0.5T takes place in the reproduced EFM signal SEFM, then the jitter of + or -0.5T corresponds to a fluctuation of the clock PLCK by + or -180 deg.. Then a dead band is set to a point where a phase difference between the phase of the SEFM and the phase of the PLCK is + or -180 deg.. As a result, even when the phase of the reproduced EFM signal SEFM and the phase of the clock PLCK are deviated by + or -180 deg., phase lock is applied, even in the case of a disk with symmetry, the error rate is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a digital PLC suitable for forming a clock based on a reproduction EFM signal of a compact disc.
Regarding LL.

[Summary of the invention]

The present invention provides a digital PDT suitable for forming a clock based on a reproduced EFM signal of a compact disc.
In LL, by setting a dead zone near the 180 degree phase difference between the phase of the oscillation output of the digitally controlled oscillator and the phase of the input signal, it is possible to improve the error rate when playing a disc with poor asymmetry. This is what I did.

[Conventional technology]

To form a clock based on the reproduced EFM (8-14 modulation) signal from a compact disc, a digital P
LL is used.

A digital PLL uses a digitally controlled oscillator whose oscillation frequency is controlled according to setting data. When a digital PLL generates a clock based on a reproduced EFM signal, a counter measures the phase difference between the reproduced EFM signal and the output signal of the digitally controlled oscillator, and this phase difference controls the oscillation frequency of the digitally controlled oscillator.

[Problem to be solved by the invention]

In a compact disc, the duty ratio of each length of the pit unevenness is not 50%, and polar defects may occur. Such a defect is called asymmetry.

Discs with poor asymmetry cause high-frequency jitter. Furthermore, jitter may occur due to code amount interference, pit abnormality, or the like.

Suppose that such a pit defect causes jitter of, for example, ±0.5T in the reproduced EFM signal. Regeneration EFM
When forming a pit clock of a signal, jitter of ±0.5T corresponds to jitter of 180 degrees of the clock. In the conventional digital PLL, when jitter of ±180 degrees occurs in this way, it becomes impossible to lock in a stable state, resulting in a problem that the error rate worsens.

In other words, in a conventional digital PLL, the period from the change point of the EFM signal to the falling edge of the clock, for example, is 180 degrees.
The control direction of the digitally controlled oscillator is determined depending on whether the value is greater than or equal to degrees. However, in the case of jitter of ±180 degrees, it is not possible to determine whether the phase is advanced or delayed. Therefore, the digitally controlled oscillator becomes unstable.

Therefore, an object of the present invention is to provide a digital PL that can improve the error rate even for disks with poor asymmetry.
The aim is to provide L.

[Means for Solving the Problems] The present invention provides a digital control oscillator that measures the phase difference between the phase of the oscillation output of the digitally controlled oscillator and the phase of the input signal, and controls the digitally controlled oscillator based on the phase difference. This digital PLL is characterized in that a dead zone is set in the vicinity of ±180 degrees where the phase difference between the phase of the oscillation output of the digitally controlled oscillator and the phase of the input signal is ±180 degrees.

[Effect]

A dead zone is provided at a point where the phase of the reproduced EFM signal s vys and the phase of the clock PLCK are ±180 degrees. Therefore, the phase of the reproduced EFM signal S EFM and the clock P
Phase lock is applied even when the phase of LCK is shifted by ±180 degrees. Therefore, phase lock is achieved even when jitter of ±180 degrees is included, and the error rate can be improved even on a disk with poor asymmetry.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. 1st
In the figure, 1 is a phase difference measuring circuit that measures the phase difference between the phase of the reproduced EFM signal S17M and the phase of the clock PLCK, 2 is a frequency difference measuring circuit that measures the frequency difference of the reproduced EFM signal, and 3 is a numerical data This is a digitally controlled oscillator whose oscillation frequency is controlled accordingly.

The phase difference measuring circuit 1 is supplied with a compact disc reproduction EFM signal S 17M from an input terminal 4. At the same time, the phase difference measuring circuit 1 is supplied with a clock P L CK from the digitally controlled oscillator 3 . The phase difference measurement circuit 1 also has a system clock SCK from the terminal 7.
is supplied as a measurement clock. The frequency of this system clock SCK (for example, 34.5 MHz) is the same as the frequency of clock PCLK (for example, 4.3218 MHz).
For example, it is assumed to be 8 times.

A phase difference measuring circuit 1 measures the phase difference between the phase of the output clock PLCK of the digitally controlled oscillator 3 and the phase of the reproduced EFM signal SEFM using the system clock SCK.

In other words, in Figure 2, the reproduced EFM signal (Figure 2B)
Data change point 1. to clock PLCK (Figure 2 C)
For example, the system clock 5CK (FIG. 2A) is counted at the time T until the falling edge L2, as shown in the second diagram.

The system clock SCK is as shown in the second diagram.
0, -3, -2, -1.0, 1.2.3...'' are counted in this order. Conventionally, the system clock SCK is "-4, -3, -2, -1, 0.1.2.3..."
However, in this embodiment, the count value "-4" is treated as O. This is to set a phase lock dead zone so that phase lock can be achieved even with a disk with poor asymmetry, as will be explained later.

In FIG. 2, the system clock SCK is counted for four clocks in the time T1 from the data change point t1 of the reproduced EFM signal to the falling edge t2 of the clock PLCK. The system clock, TSCK, has a frequency eight times that of the clock PLCK. Therefore, in this way, from the data change point t of the reproduced EFM signal to the clock PLCK
In the time TI until the falling edge of t2, the system clock SCK is 4 clocks (A period of the clock PLCK)
During counting, the phase of the reproduced EFM signal and the phase of the clock PLCK are synchronized.

The system clock SCK is “0, -3, -2.1.0.
1.2.3,...'', so in this case, as shown in the second diagram, the system clock S
The count value of CK becomes "0".

As shown in FIG. 3, the phase of the clock PLCK is
If it is ahead of the phase of the FM signal, the system clock SCK counted at time T will be less than four clocks. In the third diagram, the system clock SCK is counted for two clocks, and the count value becomes a negative value (for example, '-2J). When the count value is a negative value, the phase of the clock PLCK output from the digitally controlled oscillator 3 is delayed.

As shown in FIG. 4, the phase of the clock PLCK is
If it lags behind the FM signal S08, the system clock SCK counted during time TI will be more than 4 clocks. In the fourth diagram, the system clock SCK is counted for five clocks, and the count value becomes a positive value (for example, "1"). When the count value is a positive value, the phase of the clock PLCK output from the digitally controlled oscillator 3 is advanced.

In this way, by controlling the time T1 from the data change point L1 of the reproduced EFM signal to the falling edge t2 of the clock PLCK to be equal to 4 clocks, the reproduced EFM signal
The phase of the signal and the phase of the black/7-digit PLCK are locked.

By the way, in this embodiment, the phase difference measurement is performed not only when the system clock SCK counted during time T is equal to 4 clocks, but also when it reaches 0 clocks (or 8 clocks). The circuit 1 is designed to output "0". That is, conventionally, the count value "-4
” is treated as “0”. Therefore, as shown in FIG. 5, even when the data change point of the reproduced EFM signal and the falling edge of the clock PLCK are synchronized, the phase is locked. In other words, regenerative EFM
Signal S. FM phase and clock PLCK phase are ±1
Phase lock is applied even if there is a difference of 80 degrees.

This is to enable phase locking even if, for example, the compact disc being reproduced has poor asymmetry and the reproduced EFM signal contains jitter of ±180 degrees.

In other words, assume that the asymmetry is poor and jitter of, for example, ±0.5T occurs in the reproduced EFM signal SEFM. ±0.
The 5T minute jitter corresponds to a variation of Cronk PCKO±180 degrees.

Conventionally, there is no dead zone for fluctuations of ±180 degrees, so phase lock is applied only when the phase of the reproduced EFM signal SEFM and the phase of the clock PLCK match, resulting in jitter of ±180 degrees. Then, it becomes impossible to lock in a stable state. This is because with jitter of ±180 degrees, it is not possible to determine whether the phase is advanced or delayed.

On the other hand, in one embodiment of the present invention, the phase of the reproduced EFM signal S42 and the phase of the clock PLCK are ±18
Phase lock is applied even if there is a shift of 0 degrees. Therefore, phase lock is achieved even when jitter of ±180 degrees is included, and the error rate can be improved even on a disk with poor asymmetry.

In FIG. 1, the reproduced EFM signal S! is output from the phase difference measurement circuit 1 as described above. : Phase correction data obtained by measuring the phase difference between the FM phase and the clock PLCK phase is output. This phase correction data is supplied to the adder 5.

The frequency difference measurement circuit 2 includes an edge differentiation circuit 10, a ΔT measurement counter 11, an N detection counter 12, a frequency error amount conversion ROM 13, and a low-pass filter 14.

The reproduced EFM signal S EFM from the input terminal 4 is supplied to the edge differentiator circuit 10 . An edge differentiating circuit 10 detects a change point in the reproduced EFM signal. The output of this edge differentiating circuit 10 is supplied to a ΔT measurement counter 11 and also to an N detection counter 12.

The system clock SCK is supplied from the terminal 8 to the ΔT measurement counter 11 as a measurement clock. The ΔT measurement counter 11 counts the system clock SCK between the changing points of the reproduced EFM signal SEF.

The output of the ΔT measurement counter 11 is supplied to the N detection counter 12. System clock SCK is clock PLCK
Therefore, during the IT pattern, the ΔT measurement counter 11 counts eight system clocks SCK. Every time the ΔT measurement counter 11 counts eight clocks of the system clock SCK, the N detection counter 12 counts up. From the output of this N detection counter 12, the pattern of the reproduced EFM signal is detected.

The output of the ΔT measurement counter 11 and the output of the N detection power counter 2 are supplied to a frequency error amount conversion ROM 13. As shown in FIG. 6, the frequency error conversion ROM 13 stores frequency correction data corresponding to the frequency difference for each pattern.

The frequency correction data stored in the frequency error amount conversion ROM 13 is weighted and set according to the ratio of time axis variation for each pattern to the error of a predetermined clock. However, as will be described in detail later, in the case of the 3T pattern, such weighting is not followed. That is, in the 3T pattern, the output of the ΔT measurement counter 11 is "
3'', r5j is considered to be the dead zone. Also, Δ
The frequency correction data at the points where the output of the T measurement counter 11 becomes "2" or "6" is made smaller than the theoretical value. This is to prevent the error rate from worsening with the 3T pattern in the case of a disk with poor asymmetry.

Frequency correction data is read from the frequency error amount conversion ROM 13 in accordance with the output of the ΔT measurement counter 11 and the output of the N detection counter 12. This frequency correction data is supplied to the adder 5 via the low-pass filter 14.

As shown in FIG. 7C, the system clock SCK (FIG. 7A) is counted by the ΔT measurement counter 11 from the data change point t11 of the reproduced EFM signal SEFM. The ΔT measurement counter 11 measures 8 clocks from 0 to 7 (
(corresponding to one period of the clock PLCK) and the system clock SCK are counted. Every time the ΔT measurement counter 11 counts eight clocks of the system clock SCK, the N detection counter 12 is amplified as shown in the seventh diagram. From the output of this N detection counter 12, the pattern of the reproduced EFM signal is detected.

Then, at the data change point t+z of the next reproduced EFM signal SEFM, the output of the ΔT measurement counter 11 and the output of the N detection counter 12 are taken into the frequency error amount conversion ROM 13.

If there is no frequency error, as shown in Figure 7C,
The output of the ΔT measurement counter 11 at the next data change point t+z becomes "0".

On the other hand, when the frequency of the reproduced EFM signal sir+ becomes lower, as shown in FIG. 8C, the system clock SCK counted from the data change point t11 to the next data change point t+z becomes more than a multiple of 8. In FIG. 8C, the output of the ΔT measurement counter 11 is "2".

When the output of the N detection counter 12 is a 3T pattern and the output of the ΔT measurement counter 11 is "2", the output of the frequency error amount conversion ROM 13 is "38" as shown in FIG.
"become. When the output of the frequency error amount conversion ROM 13 is positive, the phase of the digitally controlled oscillator 3 is advanced.

Moreover, when the frequency becomes high (as shown in FIG. 9C), from the data change point tll to the next data change point t1.
The number of system clocks SCK counted up to □ becomes less than a multiple of 8.

In FIG. 9C, the output of the ΔT measurement counter 11 is "6". When the output of the N detection counter 12 is a 3T pattern and the output of the ΔT measurement counter 11 is "6",
As shown in FIG. 6, the output of the frequency error amount conversion ROM 13 becomes r-38J. Frequency error amount conversion ROM1
When the output of oscillator 3 is negative, the phase of digitally controlled oscillator 3 is delayed.

Therefore, the frequency of the digitally controlled oscillator 3 is controlled so that the output of the ΔT measurement counter 11 becomes "0".

By the way, the amount of frequency error per cycle can be found by dividing the count value obtained by the ΔT measurement counter 11 by the number of patterns, and if the frequency correction data is calculated by weighting based on this, the amount of frequency error per cycle is calculated by dividing the count value obtained by the ΔT measurement counter 11. Frequency correction data with large values (for example, "63", r-63J) are set for the points where the output becomes "3" and "5". However, if you store the frequency correction data at the points where the output of the ΔT measurement counter 11 becomes "3" and "5" in the 3T pattern like this, it will be possible to correct the problem when large jitter occurs on a disk with poor asymmetry. , frequency correction data of a large value is constantly outputted from the frequency error amount conversion ROM 13, and the digitally controlled oscillator 3 becomes unstable.

Therefore, in one embodiment of the present invention, in the 3T pattern,
A dead zone is provided for time axis fluctuations of ±3 clocks. Furthermore, in the 3T pattern, the frequency correction data for fluctuations of ±2 clocks is reduced. Therefore, in the case of a disk with poor asymmetry, if large frequency fluctuations occur in the 3T pattern, the oscillation frequency of the digitally controlled oscillator 3 will not fluctuate, the digitally controlled oscillator 3 will become stable, and the error rate will be improved. Ru.

In FIG. 1, an adder 5 adds phase difference data from a phase difference measurement circuit 1 and frequency difference data from a frequency difference measurement circuit 2. The output of this adder 5 is supplied to the digitally controlled oscillator 3.

The frequency of the digitally controlled oscillator 3 is controlled according to the data from the adder 5.

〔Effect of the invention〕

According to this invention, a dead zone is provided at a point where the phase of the reproduced EFM signal 5EFN and the phase of the clock PLCK are ±180 degrees. Therefore, even if the phase of the reproduced EFM signal SEFM and the phase of the clock PLCK are shifted by ±180 degrees, the phase is locked. Therefore, ±1
Phase locking is achieved even when 80 degrees of jitter is included, and the error rate can be improved even on discs with poor asymmetry.

Figure 10 shows the error rate when a disc with poor asymmetry is played back using a compact disc player using a conventional digital PLL, and Figure 11 shows the error rate when a disc with poor asymmetry is played back using a digital PLL to which the present invention is applied. This shows the error rate when played back on a compact disc player. Figure 10 and 1
In FIG. 1, the horizontal axis shows time, and the vertical axis shows error rate. El is a block error, and E2 is an error that cannot be corrected and is interpolated. In this example, the disc is played back at double speed.

Conventionally, as shown by E2 in FIG. 10, many errors occur that cannot be corrected and are interpolated. When this invention is applied, as shown by El2 in FIG. 11, errors that cannot be corrected and are interpolated will hardly occur.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of this invention, FIGS. 2 to 5 are timing diagrams used to explain phase control in an embodiment of this invention, and FIG. 6 is a frequency diagram of an embodiment of this invention. A route map used to explain control, and FIGS. 7 to 9 are timing charts used to explain frequency control in an embodiment of the present invention. FIGS. 10 and 11 are graphs showing the effects of this invention. Explanation of main symbols in the drawings: Phase difference measurement circuit, 2: Frequency difference measurement circuit. 3: Digitally controlled oscillator, 11: ΔT measurement counter. 12: N detection counter, 13: Frequency error amount conversion RO
M.

Claims (1)

[Scope of Claims] A digital PLC that measures the phase difference between the phase of the oscillation output of the digitally controlled oscillator and the phase of the input signal, and controls the digitally controlled oscillator based on the phase difference.
A digital PLL characterized in that, in the LL, a dead zone is set in the vicinity of a phase difference of ±180 degrees between the phase of the oscillation output of the digitally controlled oscillator and the phase of the input signal.