JPH04284038A - Clock switching device - Google Patents

Abstract

PURPOSE:To prevent whisker from being generated when switching clock signals by switching the clock signals at timing when the levels of those two signals are made equal. CONSTITUTION:A clock selection circuit 3 always selects either a clock signal CLK #0 or a CLK #1 decided by a selection control signal B from a selection control circuit 6, and the selected clock signal is supplied to a signal processor 10. A comparator circuit 11 always compares the clock signals and when the levels of the both signals are '0' together, a coincidence detection signal A is turned on. Based on switching instruction information 7, the selection control signal is changed at timing when the coincidence detection signal is turned on. Therefore, even when the switching instruction information 7 is changed by contents instructing the switching of the clock signals, no whisker is generated in the case of switching since the clock signals are switched only during a period when the both levels are '0' together.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching device for a device such as a digital communication device that performs synchronous control using a clock signal. In the digital transmission equipment of the new synchronous network, the clock source receives independent reference clocks for the current and standby clocks, and the clocks are switched. If a failure occurs in the active clock during communication, a switch is made to the backup clock. At this time, if the clock signal is switched at a bad timing, narrow whisker-like pulses are generated, causing a synchronization error in the receiving device that performs synchronization control, and causing an error. The present invention consists of two independent
Provided is a clock switching device that smoothly switches two clock signals.

0002

2. Description of the Related Art FIG. 4 is a block diagram of an example of a conventional clock switching device. Further, FIG. 5 is an operation timing diagram of the apparatus of FIG. 4. In FIG. 4, 1 and 2 are clock signals CLK#0 and CLK#1 from independent clock sources, respectively.
3 is a clock selection circuit that selects one of the clock signals CLK#0 and CLK#1. Further, 4 and 5 are AND gate circuits that gate clock signals CLK#0 and CLK#1, respectively. 6 is a selection control circuit that controls the clock selection circuit, and 7 is switching instruction information that instructs whether to select CLK#0 or CLK#1 as the clock signal. 8 is the gate circuit 4 from the selection instruction information 7
, 5, and 9 and 9' are complementary gate circuits that generate two complementary selection control signals for controlling the generated 2
There are two selection control signals. Reference numeral 10 denotes a signal processing device that performs synchronous control according to a clock signal sent from the clock selection circuit 3. The operation will be explained below according to the operation timing diagram of FIG.

Clock signals CLK#0 and CLK#1 are illustrated in FIGS. 4(a) and 4(b), and are provided, for example, in each of the 0-system and 1-system digital communication devices in a duplex configuration (not shown). The clock is constantly supplied from an independent clock source, and the mutual phase relationship is not constant. For example, assume that in normal operating conditions, the 1st system is the active system, and the switching instruction information 7 instructs to select CLK#1. In this case, as shown in FIGS. 4(c) and 4(d), the value of the selection control signal 9 output from the complementary gate circuit 8 is "0" and the value of the selection control signal 9' is "1". CLK#1 is passed through AND gate circuit 5, and AND gate circuit 4 is controlled to block CLK#0. As a result, as shown in Figure 4(e), CL
K#1 is selected and sent to the signal processing device 10. In this state, if a failure is detected in the 1 system by means not shown, the 1 system is switched to the 0 system, and the switching instruction information 7 is inverted. As a result, ts in Figure 5
At the timing of , the selection control signal 9 becomes "1" and the selection control signal 9' becomes "0", and the AND gate circuit 4 outputs C.
LK#0 is selected. In other words, from CLK#1 to CL
Switching to K#0 is performed.

0004

[Problem to be Solved by the Invention] In the conventional clock switching device, due to the phase relationship between the two clock signals and the timing of switching, when switching, the output is changed as shown in the waveform in (e) of FIG. There have been cases where narrow pulse width whiskers (or cracks) occur in the clock signal, and the synchronization control of the signal processing device is unable to follow it or follows it excessively, resulting in an out-of-synchronization state. An object of the present invention is to provide a clock switching device that does not cause whiskers when switching clock signals.

[0005]

[Means for Solving the Problems] The present invention has been made by focusing on the fact that the existence of a level difference between two clock signals to be switched at the time of switching is a cause of whiskers. The problem is solved by switching the clock signals at a time when the levels of the two signals are equal.

FIG. 1 is a diagram showing the basic configuration of the present invention. Figure 1
, 1 and 2 are independent clock signals CLK#0 and CLK#1 to be switched, respectively. Reference numeral 3 denotes a clock selection circuit that switches and selects clock signals CLK#0 and CLK#1 according to instructions from a selection control signal. 6 is,
This is a selection control circuit that sends a selection control signal to the clock selection circuit 3 and gives an instruction to switch the selection of clock signals CLK#0 and CLK#1. 7 is switching instruction information that instructs the selection control circuit 6 which clock signal to switch and select. Reference numeral 10 denotes a signal processing device that performs synchronous control based on a clock signal, and the clocks are transferred. Reference numeral 11 denotes a comparison circuit that compares the levels of clock signals CLK#0 and CLK#1 and outputs a coincidence detection signal when, for example, both levels are 0 level. The coincidence detection signal enables switching control of the clock selection circuit 3 based on the switching instruction information 7.

[0007]

[Operation] In FIG. 1, the clock selection circuit 3 is in a state where it always selects either one of the clock signals CLK#0 and CLK#1 determined by the selection control signal output from the selection control circuit 6. The generated clock signal is supplied to the signal processing device 10. The comparison circuit 11 of the selection control circuit 6 constantly compares the levels of the clock signals CLK#0 and CLK#1, and turns on the coincidence detection signal when both levels are 0 level. The selection control signal is changed based on the switching instruction information 7 at the timing when this coincidence detection signal is on. Therefore, even if the switching instruction information 7 changes to the content that instructs switching of the clock signal, the selection control signal maintains the same value while the coincidence detection signal is off, and the selection control signal does not change until the coincidence detection signal turns on. to change the selection of the clock signal from the currently selected clock signal to the other clock signal. As a result, the switching of the clock signals is performed only during the period when both levels are at 0 level, so that a whisker as shown in FIG. 5(e) does not occur at the time of switching. In the above explanation, it is assumed that the comparator circuit 11 detects a 0-level coincidence between the two clock signals, but it is the same even if it detects a 1-level coincidence. A match may be detected by comparing each of them.

[0008]

[Example] Figure 2 shows the configuration of an apparatus according to the present invention, and Figure 3
shows its operation timing diagram. In Figure 2, 1, 2
are clock signals CLK#0 and CLK#1 supplied from independent clock sources, respectively. 3 is a clock selection circuit that switches and selects clock signals CLK#0 and CLK#1 based on a selection control signal. 4 and 5 are A gates for clock signals CLK#0 and CLK#1, respectively.
It is an ND circuit. Reference numeral 6 denotes a selection control circuit that controls the clock selection circuit 3. 7 is switching instruction information that indicates the clock signal to be selected. 9 and 9' are selection control signals, respectively. 10 is a signal processing device. 11
is a comparison circuit that compares the levels of clock signals CLK#0 and CLK#1. Here, it is composed of a NOR circuit, and outputs a coincidence detection signal when the 0 level of both is detected. 12 is a coincidence detection signal output from the comparison circuit 11. 13 is a delay circuit that delays the coincidence detection signal 12 by the maximum width of the whisker to be suppressed, for example, approximately 1/4 of the clock cycle;
If the phase difference between the two clocks is close to 180 degrees, the pulse will break even if the switching timing is within the 0 level period of both clocks (
This is used to shift the switching timing to a period in which the levels of both clocks are both at 1 level. 14 is the coincidence detection signal 12 from the delay circuit 13.
This is a D-type flip-flop D-FF which reads the instruction contents of the switching instruction information 7 and generates the selection control signals 9 and 9' when the switching instruction information 7 is output.

In this embodiment, when the comparator circuit 11 detects the coincidence of the 0 level of the clock signals CLK#0 and CLK#1, the delay circuit 13 outputs the coincidence detection signal 12 which turns on the output coincidence detection signal 12. Delayed, D-FF14
is input to the CK terminal of. The delay circuit 13 is the comparator circuit 1
1 is provided in order to guarantee a constant 0 level period from when the coincidence of the 0 levels of CLK#0 and CLK#1 is detected until the rising edge of the switching destination clock signal.

The switching instruction information 7 can take levels of 0 and 1, and is applied to the D terminal of the D-FF 14. Switching instruction information 7 selects CLK#0 when the level is 1, 0
When the level is , an instruction to select CLK#1 is given. Therefore, when the switching instruction information changes from 0 to 1 or from 1 to 0, switching of the clock signal is required. However, the switching instruction information 7 applied to the D terminal of the D-FF 14 changes to
-The selection control signals 9, 9 are read into the FF14 and output from the Q and *Q terminals of the D-FF14, respectively.
' is not the time point at which the switching instruction information 7 changes, but the time point at which the delay circuit 1 changes.
The clock signal CLK#0 and CLK by the AND circuits 4 and 5 change at a time delayed by the operation delay of the D-FF 14 itself from the rising timing of the coincidence detection signal delayed in step 3.
Controls switching of LK#1.

Next, the details of the operation will be explained using the operation timing diagram shown in FIG. In Figure 3, (A) is CLK#
An example of clock switching operation when the phases of CLK#0 and CLK#1 match, (B) is an example of clock switching operation when CLK#1 is lagging behind CLK#0 in phase, (C) is An example of a clock switching operation when CLK#1 is ahead in phase than CLK#0 is shown. Also (A), (B
), (C), (a) is CLK#0
, (b) is CLK#1, (c) is the selection control signal, (e) is the clock signal of the switching result, and (f) is the comparison result of 0 level between CLK#0 and CLK#1 by the comparator circuit 11. Coincidence detection signal, (g) is delay circuit 1
The coincidence detection signal delayed by 3 and (h) are switching instruction information, which are displayed at corresponding locations in the embodiment device of FIG. 2, respectively. Note that the signals shown in Figure 2
Although (d) is not shown in Figure 3, this means that (d) is (
This is because it is simply an inverted signal of c).

In (A), the CL of (a) and (b)
Results of comparison of 0 level of K#0 and CLK#1, (f)
A coincidence detection signal is obtained and further delayed (g)
signal is obtained. Here, the switching instruction information of (h) is 0
When the level changes from CLK#1 to CLK#0 and the selection state is switched from CLK#1 to CLK#0, 1 level is written to the D-FF14 at the next falling edge of the delayed coincidence detection signal in (g). c) Switching the selection control signals in (d) to generate a clock signal as a result of switching in (e).

In cases (B) and (C), the respective clock signals are switched in the same manner as in (A), and the clock signal shown in (e) is sent to the signal processing device. Figure 5
By comparing the case of the conventional example and the case of FIG. 3(C), it can be seen that the generation of whiskers is suppressed in FIG. 3(C). According to the present invention, the levels of the two clock signals are the same at the time of switching, and the switching timings are further shifted by the delay circuit, so that all cases where whiskers may occur can be dealt with. In addition, in a device that switches between two or more clock sources, any two of them
The invention can be applied between two clock sources.

[0014]

[Effects of the Invention] According to the present invention, it is possible to always obtain a stable clock signal without whiskers when switching between independent system clock sources, thereby preventing the occurrence of synchronization deviations, and is used in fields such as communication transmission. quality can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 3 is an operation timing diagram of the device according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional device.

FIG. 5 is an operation timing chart of a conventional device.

[Explanation of symbols]

1 Clock signal CLK#0 2 Clock signal CLK#1 3 Clock selection circuit 6 Selection control circuit 7 Switching instruction information 10 Signal processing device 11 Comparison circuit

Claims (2)

[Claims] 1. A clock switching device that switches and selects one of two clock signals supplied from two independent clock sources according to a switching instruction signal, the clock switching device selecting one of the two clock signals based on the switching instruction. and a clock selection control circuit including a comparison circuit that compares two clock signals and outputs a coincidence detection signal when the levels match, and the clock selection control circuit receives the coincidence detection signal from the comparison circuit. A clock switching device that instructs a clock selection circuit to switch a clock signal based on switching instruction information at the output timing. 2. The clock switching device according to claim 1, wherein a delay circuit having a delay amount greater than the maximum pulse width of a whisker to be suppressed is provided after the comparison circuit to delay the coincidence detection signal.