JP2602421B2 - Clock reception distribution system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock receiving and distributing system for minimizing a phase difference between duplicated clocks.

[0002]

2. Description of the Related Art Conventionally, in a communication system (switches, redundant components, etc.) which uses clocks from a plurality of transmission lines while switching, there is a synchronous system in which the whole system operates by a clock having a constant frequency called a system clock. Has been adopted. Since such a clock is duplicated in terms of the reliability of the communication system or is connected to various transmission lines, the clock is switched for operation and is switched to a clock of a specific frequency.

Here, an example of a configuration showing a conventional dual clock receiving and distribution system will be described with reference to FIG.
In FIG. 3, the clock device 300 is a system 0 clock switching device and the clock device 310 is a system 1 clock switching device. The clock receiving circuits 201 and 211 are circuits that receive a clock supplied from another transmission path and supply the clock to the clock switching circuits 202 and 212.
The switching circuits 202 and 212 are connected to the receiving circuit 201.
And a circuit for selecting and outputting one of the clocks from the phase locked oscillators 203 and 211.
Reference numeral 3 outputs a clock phase-synchronized with the selected clock.

A connection example with a transmission line is, for example, in 1990
This is disclosed in Japanese Patent Application Laid-Open No. 2-82833 published on March 23, 2008. FIG. 4 is a principle diagram shown in the above-mentioned publication. Different network synchronization clocks are selected for the selector 1 and the selector 2 and the outputs of the selectors 1 and 2 are respectively monitored by the first and second clock pull-in monitors. It is sent to the circuits 3 and 4 and is in the synchronization pull-in state. if,
If there is an abnormality in the network synchronization clock, a clock abnormality signal indicating an asynchronous state is generated. The control circuit 5 fixes the network synchronization clock of the selector 1 if the network synchronization clock selected by the selector 1 has no abnormality and is in the synchronized state and has the highest priority. The selector 2 controls the selection of the selector 1 so that the selector 2 outputs the highest network synchronization clock in a synchronized state. That is, it monitors whether one of the plurality of network synchronous clocks is in a synchronous or asynchronous state, and if asynchronous, selects the network synchronous clock in the other synchronous state and the highest-priority network synchronous clock and outputs the same. I do. Thus, the phase difference between the two types of network synchronous clocks selected by the selectors 1 and 2 is not compared, only by monitoring only the synchronous asynchronous state of the selected network synchronous clock itself.

[0005]

By the way, in a dual clock receiving and distribution system as shown in FIG.
A clock input from another transmission path or an external clock supply device through a separate path usually has a phase difference between the clocks originally, and a delay time originally occurs in the clock receiving circuit between the 0 system and the 1 system. Therefore, the phase of the clock input to the phase-locked oscillation circuit greatly changes at the time of clock switching in the clock switching circuit, so that the time required for the phase-locked oscillation circuit to perform phase synchronization with the clock after switching becomes longer. During that time, the phase-locked oscillation circuit outputs an unstable free-running clock, so that there is a problem that the unstable state of the communication system, which must operate with a clock of a constant frequency, continues for a relatively long time.

As a method of solving this problem as a communication system, it is conceivable to prevent data slip between communication systems by a free-running clock. For this purpose, a large-capacity memory for absorbing a phase difference is used. , A new problem arises at the expense of increased hardware scale and economy.

[0007] It is an object of the present invention to reduce the clock size at the time of clock switching without increasing the hardware scale and sacrificing economy.
It is an object of the present invention to provide a clock receiving and distributing system for minimizing a clock phase difference between a system and a system and supplying a clock stably in a state almost without instantaneous interruption.

[0008]

According to the present invention, in order to minimize the clock phase difference between the duplicated systems (0 system, 1 system), the received clock is delayed by a fixed delay time as a basic unit. A delay circuit that can be varied to set an arbitrary delay time, a selector that inputs and selects a plurality of clocks output from the delay circuit, a specific clock selected by the selector, and a circuit that configures a duplex system. And a delay control circuit for selecting a clock having a specific delay time by a selector based on an output result of the phase comparison circuit. Therefore, in the system 0 and system 1 constituting the dual system, the output of the phase comparison circuit and the control of the delay control circuit are controlled so that the phase difference between the clock received in the system 0 and the clock received in the system 1 is minimized. Thus, the clock having the smallest phase difference is selected and fixed by the selector. For this reason, since two clocks having the minimum phase difference are input to the clock switching circuit from the beginning, a stable clock with almost no instantaneous interruption to the clock switching operation can be obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, in which a clock device 200 shows a system 0 and a clock device 210 shows a system 1 and is duplicated.

Each clock device has a clock receiving circuit 2
01 and 211, delay circuits 204 and 214,
It includes selectors 205 and 215, phase comparison circuits 207 and 217, delay control circuits 206 and 216, clock switching circuits 202 and 212, and phase locked oscillation circuits 203 and 213. Clock receiving circuits 201 and 211 receive a clock from another transmission path. The delay circuits 204 and 214 provide the clocks from the clock receiving circuits 201 and 211 with an integer multiple of 0T, 1 as a basic unit using a certain delay time T as a basic unit.
T, 2T, 3T... NT delay time added (N +
1) Output clocks. Selectors 205 and 2
Reference numeral 15 inputs all clocks of the delay times 0T, 1T, 2T, 3T... NT output from the delay circuits 204 and 214, and selects a clock having any one of the delay times from (N + 1) inputs. Output. That is, N delay lines composed of a delay coil and a gate and having a delay time T are cascaded, and a total of (N + 1) signals output from each delay line are input to the selector, and any one input Is selected and output to change the delay time.

The phase comparison circuits 207 and 217 are connected to the clocks output from the selectors 205 and 215 and a delay circuit 2 of another system (1 system for 0 system and 0 system for 1 system).
Receiving a clock having a delay time of (N + 1) T / 2, which is the center value of the (N + 1) outputs 0T, 1T, 2T, 3T... NT generated at 14 and 204;
A phase comparison is performed to determine whether the phases of the two clocks match or not, and a result of the determination is output as a signal. When the phase determination results of phase comparison circuits 207 and 217 are out of phase, delay control circuits 206 and 216 sequentially change the selection signals of selectors 205 and 215 to output a clock having the next delay time. This operation is repeated until the phase determination results match. When the phase determination results match, the selection signal is fixed, and the selectors 205 and 21
5 is fixed, and only a clock having a specific delay time is output. As described above, the inputs of the selectors 205 and 215 are sequentially switched, and the phase comparison circuits 207 and 217 are switched.
Since the switching is stopped when the phases coincide with each other, the initial state of the selector may be arbitrary. This operation is performed by the 0-system phase comparison circuit 207 so that the 0-system selector selects the clock closest to the phase of the clock of the delay time (N + 1) T / 2 generated by the 1-system delay circuit 214. The operation starts when the control circuit 206 operates.

The clock switching circuit 202 generates and outputs (N +) the selected clock output from the selector 205 of the own system (system 0) and the delay circuit 214 of the other system (system 1).
1) Select and output one of the clocks having a delay time of T / 2. At this time, since the phase difference between the two clocks input to the clock switching circuit is suppressed to a minimum of T / 2 or less, the clocks have almost the same phase. Is output.

The phase-locked oscillation circuits 203 and 213 output clocks that are phase-locked with the input clock.
Delay control circuits 206 and 21 such that the phase comparison results in phase comparison circuits 207 and 217 are equal in phase, that is, the absolute value of the phase difference is always equal to or less than minimum delay time T / 2.
6 operates and the selectors 205 and 215 are feedback-controlled, so that the clock switching circuits 202 and 21
The clock phase difference between the 0 system and the 1 system at the input of 2 is always T
/ 2 or less. That is, almost the same clock with the smallest phase difference between the two clocks is always input to the input of the clock switching circuit. Therefore, if the value of the delay time T itself is reduced in the delay circuits 204 and 214, it is possible to set a very fine delay time. Therefore, the clock switching circuits 202 and 2
Even if the clocks are switched at 12, the phases of the two clocks input to the phase-locked oscillation circuits 203 and 213 can always be almost the same value, that is, clocks having the same phase. The same clock is supplied to the phase-locked oscillation circuits 203 and 21.
3, a stable clock with almost no interruption to the clock switching operation is always obtained.

The clock devices 200 (0-system) and 210 (1-system) are usually operated in a HOT-STANDBY system in which both the 0-system and 1-system are always powered on, the 0-system is in operation, and the 1-system is inactive. Fixed in state.

Therefore, since the system 0 is in operation, the system 0 clock switching circuit 202 inputs its own system (system 0) clock. Since the clock of the system (0 system) is input, a clock having the same phase as the clock selected in the 0 system is output from the clock switching circuits 202 and 212 of both systems. That is, although one signal line is shown from the 0-system delay circuit 204 to the 1-system phase comparison circuit 217,
Since this signal line is simultaneously scanned in response to the 0-system selector 205 sequentially scanning for clock selection, a clock having the same phase as the clock selected by the selector 205 is output. Here, if the system 0 clock fails, the system 0 clock switching circuit 2
02 operates to select the 1-system clock,
This time, clocks having the same phase as the clock selected in the first system are output from the clock switching circuits 202 and 212 in both systems. When the failure is recovered, the system 0 returns to the operating state and the system 1 returns to the beginning of the sleep state again. Accordingly, the clock switching circuits 202 and 212 have a function of detecting a clock failure and a function of controlling switching of the 0-system and the 1-system.

Next, a clock phase comparison operation will be described with reference to FIG.

The clocks output from the clock receiving circuits 201 and 211 are delayed by delay circuits 204 and 21.
4 is 0T, 1T, 2T.
A clock having a delay time of N (= 9) T is generated, and all clocks are output to the selectors 205 and 215. The delay time (N + 1) T / 2 = 5 of the center value among the N + 1 = 10 clocks is output from the delay circuit 214 of the first system.
A clock having T is output, and the delay control circuit operates so that the 0-system selector 205 selects the clock closest to the phase of the 5T delayed clock by the 0-system selector 205. Note that the first system delay circuit 214 does not necessarily need to start fixedly from a clock having a delay time (N + 1) T / 2, but may start from an arbitrary clock as an initial operation.

The phase comparison circuit 207 determines that a match has occurred when the compared phase difference is smaller than T / 2, and notifies the delay control circuit 206 of the result of the match. Phase difference is 1 / 2T
If it is larger, it is determined that they do not match, and the result of the mismatch is notified to the delay control circuit 206. When the delay control circuit 206 receives the mismatch notification, the delay control circuit 206 changes the selection signal (1 to N = 9) supplied to the selector 205 to the current set value, for example, N = 3.
Is set to N + 1 = 4. Thereafter, since the notification from the phase comparison circuit 207 becomes inconsistent again, the delay control circuit 206 selects a clock with a delay time 5T in which the selection signal is set to N + 1 = 5 obtained by adding 1 to the current set value N = 4. Since this clock coincides with a clock having a delay time of 5T from the delay circuit 214 of the first system, the phase comparison circuit 2
07 determines the match, and the delay control circuit 206 keeps the current setting value. As described above, this series of operations is repeated until a notice of coincidence is received from the phase comparison circuit 207.

Incidentally, the delay control circuits 206 and 216 may be constituted by external independent system controllers. As an operation example, the frequency of the clock is 2 MHz for the input clock to the clock receiving circuits 201 and 211.
At this time, the phase-locked oscillation circuits 203 and 213
Input clock is 2MHz, this is multiplied to 32MHz
Is output as

[0021]

As described above, the clock receiving and distributing system according to the present invention can minimize the phase difference between clocks from a plurality of transmission paths or a plurality of external devices or a duplicated clock. It is possible to reduce the unstable operation time until the clock of the phase-locked oscillation circuit is generated when the clock is switched. As a result, an operation that is almost instantaneous interruption or non-switching can be realized, so that there is an effect that the reliability of a system malfunction at the time of clock switching or a fear of occurrence of a failure is significantly improved.

Further, in the clock receiving and distributing system according to the present invention, it is not necessary to have a large-capacity storage circuit for coping with data loss due to an instantaneous interruption at the time of clock switching, and a low-cost general-purpose IC circuit. Therefore, economical effects can be expected.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clock reception and distribution system showing an embodiment of the present invention.

FIG. 2 is a time chart showing a clock phase difference correction operation.

FIG. 3 is an overall configuration diagram of a conventional duplex clock device.

FIG. 4 is a diagram illustrating the principle of a conventional synchronous clock selection device in connection with a transmission line.

[Explanation of symbols]

 200, 210 clock devices 201, 211 clock receiving circuits 202, 212 clock switching circuits 203, 213 phase-locked oscillation circuits 204, 214 delay circuits 205, 215 selectors 206, 216 delay control circuits 207, 217 phase comparison circuits 300, 310 clock devices

Claims (2)

(57) [Claims] 1. A clock receiving and distributing system having a duplicated clock device, wherein each of the duplicated clock devices receives a clock from an external device, and the received clock is generated based on a fixed delay time. A delay circuit that outputs a plurality of clocks delayed by an arbitrary integral multiple of the delay time, a selector that selects one specific clock from the plurality of delayed clocks, and a clock and duplex of the selector output A phase comparison circuit that compares the phase difference between the two types of clocks with the clock output from the other delay circuit, and a clock selected by the selector based on the match / mismatch determination output result of the phase comparison circuit. A delay control circuit that automatically changes to a delayed clock or uses the currently selected clock. And a clock switching circuit for switching between the two types of clocks, and a phase-locked oscillation circuit for outputting a clock that is phase-locked with the clock switched by the switching circuit, and the clock when the two types of clocks are switched. Wherein the phase difference is minimized. 2. The clock reception and distribution system according to claim 1, wherein said delay circuit, said selector, said delay control circuit, and said phase comparison circuit are constituted by external independent system controllers.