JPH0897750A - Clock reception distribution system - Google Patents

Abstract

PURPOSE: To attain uninterruptible operation or close thereto by reducing an unstable operation time till a time of phase synchronization achievement caused at clock switching. CONSTITUTION: The system uses clock reception circuits 201, 211 in duplicate, delay circuit 204, 214 providing plural clocks delayed by an optional integeral multiple of a prescribed delay time from the received clock, selectors 205, 215 selecting a specific clock, phase comparator circuits 207, 217 comparing a phase difference between the selected clock and the clock outputted from the delay circuits 214, 204 and delay control circuits 206, 216 replaces the clock selected by the selectors 205, 215 with the other delayed clock or the clock selected at present. The delay control circuits 206, 216 supply a clock to phase synchronization oscillated circuits 203, 213 without hit when the clock changeover circuits 202, 212 select the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock receiving / distributing system for minimizing the phase difference between duplicated clocks.

[0002]

2. Description of the Related Art Conventionally, in communication systems (switches, redundant components, etc.) that switch and use clocks from a plurality of transmission lines, there is a synchronous system in which the entire system operates with a clock of a certain frequency called a system clock. Has been adopted. Since such a clock is duplicated for reliability of the communication system and is connected to various transmission lines, the clock is switched in operation and is switched to a clock of a specific frequency.

An example of the configuration of a conventional dual clock receiving / distributing system will be described with reference to FIG.
In FIG. 3, a clock device 300 is a 0-system clock device, and a clock device 310 is a 1-system clock switching device, and they are duplicated. The clock receiving circuits 201 and 211 are circuits that receive a clock supplied from another transmission path and supply the clock to the clock switching circuits 202 and 212.
The switching circuits 202 and 212 are the receiving circuits 201.
Is a circuit for selecting and outputting any one of the clocks from
3 outputs a clock that is in phase with the selected clock.

An example of connection with a transmission line is, for example, 1990.
It is disclosed in Japanese Patent Application Laid-Open No. 2-82833 published on Mar. 23, 2013. FIG. 4 is a principle diagram shown in the above publication, in which different network synchronization clocks are selected for the selector 1 and the selector 2, and the outputs of the selectors 1 and 2 are the first and second clock pull-in monitors, respectively. It is sent to the circuits 3 and 4 and is in the synchronous pull-in state. if,
If there is an abnormality in the network synchronization clock, a clock abnormality signal indicating an asynchronous state is generated. The control circuit 5 fixes the network synchronization clock of the selector 1 if the network synchronization clock selected by the selector 1 has no abnormality and is in the synchronization state and the highest priority network synchronization clock is given, but when it becomes the asynchronous state. The selector 2 controls the selection of the selector 1 so that the selector 1 outputs the highest network synchronization clock in the synchronized state. That is, it monitors whether one of the plurality of network synchronization clocks is in the synchronous or asynchronous state, and if it is asynchronous, selects and outputs the highest-order network synchronization clock with the other network synchronization clock in the synchronized state. To do. Thus, only the synchronous / asynchronous state of the selected network synchronization clock itself is monitored, and the phase difference between the two types of network synchronization clocks selected by the selectors 1 and 2 is not compared.

[0005]

By the way, in the dual clock receiving and distributing system as shown in FIG.
A clock input from another transmission line or an external clock supply device through a separate route usually has a phase difference in the clock originally, and a delay time originally between the 0-system and the 1-system causes a difference in the clock reception circuit. Therefore, when the clock is switched in the clock switching circuit, the phase of the clock input to the phase-locked oscillation circuit changes greatly, so that it takes a long time until the phase-locked oscillation circuit is phase-locked with the clock after switching. During that time, the phase-locked oscillator circuit outputs an unstable free-running clock, which causes a problem that the unstable state of the communication system, which originally has to operate with a clock of a constant frequency, continues for a relatively long time.

As a method for solving this problem in a communication system, it is possible to prevent data slip between communication systems by a free-running clock. For this reason, a large-capacity memory for absorbing the phase difference is used. , Which creates new problems at the expense of increased hardware scale and economy.

The object of the present invention is to achieve zero clock switching without sacrificing hardware scale and economy.
It is an object of the present invention to provide a clock receiving / distributing system in which a clock phase difference between a system and a system 1 is minimized to stably supply a clock in a state of almost no interruption.

[0008]

According to the present invention, in order to minimize the clock phase difference of the duplicated system (0 system, 1 system), the delay time of the received clock is set with a constant delay time as a basic unit. A delay circuit that can be varied and set an arbitrary delay time, a selector that inputs and selects a plurality of clocks output from the delay circuit, a specific clock selected by this selector, and a dual system A phase comparison circuit for comparing the phase with the clock from the delay circuit, and a delay control circuit means for selecting a clock having a specific delay time by a selector according to the output result of the phase comparison circuit. Therefore, in the 0-system and the 1-system that compose the dual system, the output of the phase comparison circuit and the control of the delay control circuit are controlled so that the phase difference between the clock received by the 0-system and the clock received by the 1-system is minimized. As a result, the clock with the smallest phase difference is selected and fixed by the selector. Therefore, since the two clocks having the smallest phase difference are input to the clock switching circuit from the beginning, it is possible to obtain a stable clock that is almost non-instantaneous to the clock switching operation.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, in which a clock device 200 shows a 0 system and a clock device 210 shows a 1 system, which are duplicated.

Each clock device has a clock receiving circuit 2
01 and 211, delay circuits 204 and 214,
It includes selectors 205 and 215, phase comparison circuits 207 and 217, delay control circuits 206 and 216, clock switching circuits 202 and 212, and phase locked oscillator circuits 203 and 213. The clock receiving circuits 201 and 211 receive clocks from other transmission lines. The delay circuits 204 and 214 have an integral multiple of 0T, 1 with respect to the clocks from the clock receiving circuits 201 and 211 with a certain delay time T as a basic unit.
T, 2T, 3T ... NT delay time is added (N +
1) Output clocks. Selector 205 and 2
15 inputs all the clocks of the delay times 0T, 1T, 2T, 3T, ... NT output from the delay circuits 204 and 214, and selects a clock having any one delay time from (N + 1) inputs. Output. That is, N delay lines having a delay time T composed of a delay coil and a gate are cascade-connected, and a total of (N + 1) signals output from the respective delay lines are input to a selector to input any one input. The delay time is changed by selecting and outputting.

The phase comparison circuits 207 and 217 are the delay circuits 2 of the clocks output from the selectors 205 and 215 and the other system (1 system for 0 system and 0 system for 1 system).
Receiving a clock having a delay time of (N + 1) T / 2, which is the central value of 0T, 1T, 2T, 3T ... NT which are (N + 1) outputs generated in 14 and 204,
Phase comparison is performed, it is determined whether the phases of the two clocks match or mismatch, and the determination result is output as a signal. When the phase determination results of the phase comparison circuits 207 and 217 are out of phase, the delay control circuits 206 and 216 sequentially change the selection signals of the selectors 205 and 215 and output a clock having the next delay time. This operation is repeated until the phase determination results match. When the phase determination results match, the selection signal is fixed and the selectors 205 and 21
5 is fixed and only clocks having a specific delay time are output. In this way, the inputs of the selectors 205 and 215 are sequentially switched, and the phase comparison circuits 207 and 217 are performed.
Since the switching is stopped when the phases coincide with each other, the initial state of the selector may be arbitrary. The operation is delayed by the 0-system phase comparison circuit 207 so that the 0-system selector selects the clock closest to the phase of the clock of the delay time (N + 1) T / 2 generated by the 1-system delay circuit 214. It starts with the operation of the control circuit 206.

The clock switching circuit 202 is generated and output by the selected clock output from the selector 205 of its own system (0 system) and the delay circuit 214 of another system (1 system) (N +).
1) Either one of the clocks having a delay time of T / 2 is selected and output. At this time, the phase difference between the two clocks input to the clock switching circuit is suppressed to a minimum value of T / 2 or less, so that the clocks have almost the same phase. Therefore, there is almost no phase difference even when the clocks are switched. Is output.

The phase-locked oscillator circuits 203 and 213 output a clock that is in phase with the input clock.
In the phase comparison circuits 207 and 217, the delay control circuits 206 and 21 are arranged so that the phase comparison results are in phase agreement, that is, the absolute value of the phase difference is always the minimum delay time T / 2 or less.
6 operates and the selectors 205 and 215 are feedback-controlled, so that the clock switching circuits 202 and 21
At the input of 2, the clock phase difference between the 0 system and the 1 system is always T
It can be suppressed to / 2 or less. In other words, the clock switching circuit always receives almost the same clock having the smallest phase difference between the two clocks. Therefore, by reducing the value of the delay time T itself in the delay circuits 204 and 214, it is possible to set a very fine delay time. Therefore, the clock switching circuits 202 and 2
Even if the clock is switched in 12, the phases of the two clocks input to the phase-locked oscillator circuits 203 and 213 can always be set to almost the same value, that is, the clocks of the same phase. Therefore, even if the clock switching circuit 202 is switched. The same clock is used for the phase locked oscillators 203 and 21.
Since 3 is input, a stable clock in a state close to a momentary interruption with respect to the clock switching operation is always obtained.

The clock devices 200 (0 system) and 210 (1 system) are normally operated by HOT-STANDBY in which both the 0 system and the 1 system are constantly powered on, and the 0 system is in the operating state and the 1 system is inactive. It is fixed in the state.

Therefore, the 0-system clock switching circuit 202 inputs the clock of its own system (0-system) because the 0-system is in the operating state, and the 1-system clock switching circuit 212 is the rest because the 1-system is in the idle state. Since the system (0 system) clock is input, the clocks of the same phase as the clock selected in the 0 system are output from the clock switching circuits 202 and 212 of both systems. That is, although one signal line is illustrated from the 0-system delay circuit 204 to the 1-system phase comparison circuit 217,
Since this signal line is simultaneously scanned in response to the 0-system selector 205 sequentially scanning for clock selection, a clock having the same phase as the clock selected by the selector 205 is output. If the 0-system clock becomes an obstacle here, the 0-system clock switching circuit 2
02 operates to select the 1-system clock, so
This time, a clock having the same phase as the clock selected in the first system is output from the clock switching circuits 202 and 212 of both systems. When the fault is restored, the 0 system is returned to the operating state and the 1 system is returned to the initial state of the dormant state. Therefore, the clock switching circuits 202 and 212 include a function of detecting a clock failure and a 0-system and 1-system switching control function.

Next, the clock phase comparison operation will be described with reference to FIG.

Delay circuits 204 and 21 are provided for the clocks output from the clock receiving circuits 201 and 211.
In the case of 4, the delay time T is used as a basic unit for 0T, 1T, 2T.
.. Generate a clock having a delay time of N (= 9) T and output all clocks to the selectors 205 and 215. From the 1-system delay circuit 214, the delay time (N + 1) T / 2 = 5 of the central value out of N + 1 = 10 clocks.
A clock having T is output, and the 0-system phase comparison circuit 207 operates so that the 0-system selector 205 selects the clock closest to the phase of the 5T delayed clock. Note that the 1-system delay circuit 214 does not necessarily have to start fixedly from a clock having a delay time (N + 1) T / 2, and the initial operation may start from an arbitrary clock.

The phase comparison circuit 207 determines that they match when the compared phase difference becomes smaller than T / 2, and notifies the delay control circuit 206 of the result of the match. Phase difference is 1 / 2T
When it is larger than the above, it is determined that they do not match and the delay control circuit 206 is notified of the result of the mismatch. When the delay control circuit 206 receives the notification of non-coincidence, the delay control circuit 206 outputs the selection signal (the numerical value of 1 to N = 9) supplied to the selector 205 to the current set value, for example, N = 3.
Is set to N + 1 = 4. After that, since the notification from the phase comparison circuit 207 again becomes inconsistent, the delay control circuit 206 selects the clock having the delay time 5T in which the selection signal is set to N + 1 = 5 by adding 1 to the current set value N = 4. Since this clock coincides with the clock having the delay time 5T from the delay circuit 214 of the 1-system, the phase comparison circuit 2
07 determines the coincidence, and the delay control circuit 206 keeps the current set value. As described above, this series of operations is repeated until the phase comparison circuit 207 notifies the agreement.

The delay control circuits 206 and 216 may be constituted by external independent system control devices. As an operation example, the clock frequency is 2 MHz for the input clock to the clock receiving circuits 201 and 211.
At this time, the phase-locked oscillator circuits 203 and 213
Input clock is 2MHz, which is multiplied by 32MHz
Is output as.

[0021]

As described above, the clock receiving / distributing system according to the present invention can suppress the phase difference between the clocks from a plurality of transmission lines or a plurality of external devices or the duplicated clocks to a minimum amount. It is possible to reduce the unstable operation time until the clock is pulled in the phase-locked oscillator generated when the clock is switched. For this reason, since an operation similar to no interruption or no switching can be realized, there is an effect that the reliability against the malfunction of the system and the fear of the occurrence of a failure at the time of clock switching is significantly improved.

Further, in the clock receiving / distributing system according to the present invention, it is not necessary to have a large-capacity memory circuit for coping with a data loss caused by a momentary interruption at the time of clock switching as in the conventional case, and a general-purpose IC circuit with low cost is provided. Since it can be easily configured with, economic effects can be expected.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a clock reception distribution system showing an embodiment of the present invention.

FIG. 2 is a time chart showing a clock phase difference correction operation.

FIG. 3 is an overall configuration diagram of a conventional dual clock device.

FIG. 4 is a principle diagram of a conventional synchronous clock selection device in connection with a transmission line.

[Explanation of symbols]

 200, 210 Clock device 201, 211 Clock receiving circuit 202, 212 Clock switching circuit 203, 213 Phase synchronous oscillation circuit 204, 214 Delay circuit 205, 215 Selector 206, 216 Delay control circuit 207, 217 Phase comparison circuit 300, 310 Clock device

Claims (2)

[Claims] 1. A clock receiving / distributing system having a dual clock device, wherein each of the dual clock devices receives a clock from the outside, and the received clock is based on a fixed delay time. A delay circuit that outputs a plurality of clocks delayed by a delay time of an arbitrary integral multiple as a unit, a selector that selects a specific one clock from the plurality of delayed clocks, a clock of the selector output, and a duplexer The phase comparison circuit for comparing the phase difference between the two types of clocks with the clock output from the other delay circuit, and the clock selected by the selector based on the match / mismatch determination output result of the phase comparison circuit Delay control time that automatically changes to the delayed clock or sets it as the currently selected clock A clock, a clock switching circuit for switching between the two types of clocks, and a phase-locked oscillation circuit for outputting a clock phase-synchronized with the clocks switched by the switching circuit, and the clock when the two types of clocks are switched. A clock receiving / distributing system characterized in that the phase difference between the two is minimized. 2. The clock reception / distribution system according to claim 1, wherein the delay circuit, the selector, the delay control circuit, and the phase comparison circuit are constituted by an external independent system control device.