JP2002328743A - Clock signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a clock signal whose frequency is close to a desired frequency from a reference clock signal. SOLUTION: A frequency of a clock signal CLK10 is divided into 1/2, 1/4, 1/8, 1/16, and 1/32 by a frequency-dividing circuit 10 to generate clock signals CLK12, CLK14, CLK16, CLK18, and CLK20. Frequency detecting circuits 12-20 compare the frequencies of the clock signals CLK12-CLK20 with a preliminarily set reference frequency fST, and when the frequencies are higher than the reference frequency fST, set the levels of detection signals C10-C18 so as to be H, and set them so as to be L in the other case. A frequency selecting circuit 22 selects the clock signal having a frequency close to the reference frequency fST from among the clock signals CLK10-CLK20 outputted from the frequency- dividing circuit 10 based on the pattern of the levels of the detection signals C10-C18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generating circuit capable of obtaining a clock signal close to a desired frequency from a reference clock signal having a frequency which is extremely stable against voltage and temperature fluctuations.

[0002]

2. Description of the Related Art In a digital device, various timing signals are generally generated by an internal clock signal and supplied to each circuit in the device. Conventionally, as a clock signal generation source for generating the internal clock signal, a crystal oscillator using a crystal oscillator, a ring oscillator configured with a logic circuit, and the like have been widely used.

[0003]

However, a crystal oscillator can generate a clock signal having an extremely stable frequency with respect to a change in ambient temperature and a change in power supply voltage. Since the oscillation frequency of the crystal unit used depends on the desired frequency at which the user wants to operate the digital device, the user selects the crystal unit according to the desired frequency and selects the crystal unit. There is a trouble that the crystal oscillator is configured by using the crystal.

A ring oscillator is an inverter or NA
Since it can be configured using a logic circuit such as an ND circuit, it is relatively easy to realize a ring oscillator having a desired oscillation frequency, but the stability of the oscillation frequency against changes in ambient temperature and fluctuations in the power supply voltage is relatively low. Since it is extremely lower than that of a crystal oscillator, it was necessary to perform temperature compensation and voltage compensation. However, there is a problem that it is difficult to keep the oscillation frequency stability within a predetermined range by these compensations.

The present invention solves the above-mentioned problems of the prior art, and provides a clock signal generation circuit capable of obtaining a clock signal close to a desired frequency from a reference clock signal having an extremely stable frequency. The purpose is to:

[0006]

In order to solve the above problems, the present invention provides a frequency dividing means for dividing an input clock signal to generate a plurality of clock signals, and a plurality of clock signals generated by the frequency dividing means. A plurality of frequency detecting means for comparing the frequency of the clock signal with a preset reference frequency for each clock signal; and a frequency close to the reference frequency from among the plurality of clock signals in accordance with a comparison result obtained by the plurality of frequency detecting means. Frequency selecting means for selecting a clock signal having the following.

The present invention also provides frequency dividing means for dividing an input clock signal to generate a plurality of clock signals, and switching means for sequentially selecting a plurality of clock signals generated by the frequency dividing means in a predetermined order. And a frequency detecting means for comparing the frequency of the clock signal selected by the switching means with a preset reference frequency; and a frequency close to the reference frequency from the plurality of clock signals according to the comparison result obtained by the frequency detecting means. Frequency selecting means for selecting a clock signal having the following.

Further, the present invention provides a multiplying means for multiplying an input clock signal to generate a plurality of clock signals, a switching means for sequentially selecting a plurality of clock signals generated by the multiplying means in a predetermined order, Frequency detecting means for comparing the frequency of the clock signal selected by the means with a preset reference frequency; and a clock having a frequency close to the reference frequency from among a plurality of clock signals in accordance with the comparison result obtained by the frequency detecting means. Frequency selecting means for selecting a signal.

Further, the present invention provides a frequency dividing means for dividing an input clock signal to generate a plurality of clock signals, a frequency multiplying means for multiplying the input clock signal to generate a plurality of clock signals, and a frequency dividing means. Switching means for sequentially selecting a plurality of clock signals generated by the multiplying means according to a predetermined order; frequency detecting means for comparing the frequency of the clock signal selected by the switching means with a preset reference frequency; Frequency selecting means for selecting a clock signal having a frequency close to a reference frequency from a plurality of clock signals generated by the frequency dividing means and the multiplying means in accordance with the comparison result obtained by the detecting means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a clock signal generating circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a first embodiment of a clock signal generation circuit according to the present invention. This clock signal generating circuit includes a frequency dividing circuit 10, frequency detecting circuits 12 to 20.
And a frequency selection circuit 22. A clock signal CLK10 is input to the frequency dividing circuit 10 from outside. This clock signal CLK10 is a reference clock signal generally supplied from a crystal oscillator, and its frequency is extremely stable against fluctuations in ambient temperature and power supply voltage. The frequency divider 10 sets the frequency f10 of the input clock signal CLK10 to 1 / N (N is an integer)
In this embodiment, the frequency is divided by f10.
Is divided into 1/2, 1/4, 1/8, 1/16 and 1/32 so that the frequencies are f10 / 2, f10 / 4, f10 / 8, f10 / 16 and f1 respectively.
Generate 0/32 clock signals CLK12, CLK14, CLK16, CLK18 and CLK20. Note that the above N can be set to any integer.

FIG. 2 is a block diagram showing an example of the frequency dividing circuit 10. The frequency dividing circuit 10 comprises five D-type flip-flops (D-FF) 100 to 108 connected in cascade. In FIG. 2, the input clock signal CLK10 is successively frequency-divided by 1/2 by flip-flops 100 to 108, and output from the flip-flops 100 to 108 respectively by 1/2, 1/4, 1/8, 1/16 and 1/32. The frequency-divided clock signals CLK12 to CLK20 are extracted. The input clock signal CLK10 is also output. FIG. 3 shows a schematic waveform of the clock signals CLK10 to CLK20 output from the frequency dividing circuit 10.

The frequency dividing circuit 10 is connected to frequency detecting circuits 12 to 20 and a frequency selecting circuit 22, and receives clock signals CLK12 to CLK2.
0 is input to the frequency detection circuits 12 to 20, respectively, and the clock signals CLK10 to CLK20 are input to the frequency selection circuit 22. The frequency detection circuits 12 to 20 are circuits for detecting the frequency of the input clock signal. In the present embodiment, the frequency detection circuits 12 to 20 compare the frequency of the clock signal with a preset reference frequency fs and indicate a determination result. The signals C10 to C18 are output. The frequency detection circuits 12 to 20 have the same configuration,
The set reference frequency fs is the same frequency. One example of the frequency detection circuits 12 to 20 is shown in FIG.

The frequency detection circuit of FIG.
A charge / discharge circuit including a resistor R and a capacitor C, a non-inverter 120, and an RS including NAND gates 122 and 124.
It comprises a flip-flop and an inverter 126. Then, a clock signal CLK is externally supplied to the charge / discharge circuit.
Is input, one end of the capacitor C is connected to the voltage V,
The reset signal RST is supplied to the NAND gate 124, and the detection signal C is output from the inverter 126. FIGS. 5A and 5B show schematic waveforms at respective parts of the frequency detection circuit thus configured. FIG. 5A shows the case where the frequency of the clock signal CLK is higher than the reference frequency fs, and FIG. FIG. 9 is a waveform chart when the frequency is lower than fs. Note that V
a and Vb are non-inverter 120 and NAND gate 122, respectively.
Input voltage.

The operation of the above-described frequency detection circuit will be described with reference to FIG.
Reset signal RST supplied to 124 is H (high level)
Is set to At this time, since the clock signal CLK is not input, the input voltage Va of the non-inverter 120 becomes L (low level). As a result, the input voltage Vb of the NAND gate 122 becomes L. Therefore, the flip-flop is reset, and the detection signal C output from the inverter 126 is output.
Becomes L.

When the frequency detection is started and the clock signal CLK changes from L to H at time t1, a current flows through the capacitor C via the diode D, and the diode D is turned on. Inverter 120
Is input to Therefore, the input voltage Va of the non-inverter 120 and the input voltage Vb of the NAND gate 122 become H, respectively. At this time, the reset signal RST is set to L for a predetermined period in synchronization with the rise of the clock signal CLK at time t1. Therefore, the flip-flop is set,
The detection signal C output from the inverter 126 becomes H.
It is assumed that the reset signal RST is set to H except for the period set from time t1 to L.

Next, when the clock signal CLK changes from H to L at the time t2, the diode D is turned off, so that the charge charged in the capacitor C is discharged through the resistor R, and the input voltage of the non-inverter 120 is reduced. Va is the capacitor C
And the resistance R gradually decreases according to the time constant determined by the resistance R. When the frequency of the clock signal CLK is high, FIG.
As shown in (a), the clock signal CLK changes to H before the input voltage Va of the non-inverter 120 does not decrease to L (time t3). Therefore, the output of the non-inverter 120 is held at H, and the input voltage Vb of the NAND gate 122 remains at H. At this time, since the reset signal RST is H,
Both the set input and reset input of the flip-flop are H
And the flip-flop is held in the previous state, and the detection signal C output from the inverter 126 remains at H. Thereafter, even if the clock signal CLK is input, the detection signal C is held at H.

However, when the frequency of the clock signal CLK is low, the input voltage Va of the non-inverter 120 decreases to L before the clock signal CLK changes from L to H, as shown in FIG. Therefore, the output of the non-inverter 120 changes to L before time t3, and the input voltage Vb of the NAND gate 122 changes to L. At this time, the reset signal RST is H
Therefore, the set input of the flip-flop becomes L, the reset input becomes H, and the flip-flop is reset. As a result, the detection signal C output from the inverter 126 changes to L. Thereafter, even if the clock signal CLK is input, the detection signal C is held at L. As described above, the frequency detection circuit sets the detection signal C to H or L at a certain frequency, and this frequency (hereinafter referred to as a reference frequency fST).
Is determined by the time constant of the circuit consisting of the resistor R and the capacitor C. Therefore, this capacitor C and resistance
By selecting the value of R, the reference frequency fST can be set to a desired frequency.

Incidentally, the frequencies of the clock signals CLK12 to CLK20 input to the frequency detection circuits 12 to 20 in FIG. 1 are 1/2 to 1/32 of the clock signal CLK10, and differ for each frequency detection circuit. Taking the frequency detection circuit 20 as an example, since the frequency of the input clock signal CLK20 is 1/32 of the frequency f10 of the clock signal CLK10, if the frequency f10 of the clock signal CLK10 is higher than 32 * fST, the detection signal C18 to H
And L if low. The frequency detection circuit 18
In this case, the frequency of the input clock signal CLK18 is 1/16 of the frequency f10 of the clock signal CLK10. Therefore, when the frequency f10 of the clock signal CLK10 is higher than 16 * fST, the detection signal C16 is set to H, If low, L is set. The other frequency detection circuits 12 to 16 similarly perform detection signals C10 to C1.
Set level 4

FIG. 6 summarizes changes in the detection signals C10 to C18 of the frequency detection circuits 12 to 20 with respect to the frequency f10 of the input clock signal CLK10. From this figure, for example, when the frequency f10 of the clock signal CLK10 is lower than 32 * fST, all the detection signals C10 to C18 become H, and when the frequency f10 is higher than 16 * fST and lower than 32 * fST, The detection signals C10 to C18 are H, H, H, H, L, respectively.
When the frequency f10 is higher than 8 * fST and lower than 16 * fST, the detection signals C10 to C18 are H, H,
It turns out that it becomes H, L, L.

As described above, the levels of the detection signals C10 to C18 change according to the frequency f10 of the clock signal CLK10, and the pattern of the levels of the detection signals C10 to C18 has a frequency of 32 * fS
It changes for each frequency range bounded by T, 16 * fST, 8 * fST, 4 * fST, and 2 * fST. In this embodiment,
The frequency range in which the frequency f10 of the clock signal CLK10 exists is determined based on the level patterns of the detection signals C10 to C18. Then, either the upper limit or the lower limit of the frequency range obtained by the determination is selected, and the selected frequency (N * fST)
From the clock signal output from the frequency dividing circuit 10.
A clock signal divided by 1 / N is selected from CLK10 to CLK20. Thereby, a clock signal having a frequency close to the reference frequency fST can be obtained.

For example, when the levels of the detection signals C10 to C18 are all H, if the frequency f10 of the clock signal CLK10 is
Is higher than 32 * fST. Therefore, in this embodiment, a frequency close to the reference frequency fST is determined as f10 / 32, and the frequency dividing circuit 10
Selects the clock signal CLK20 divided by 1/32. The levels of the detection signals C10 to C18 are H, H,
In the case of H, H, L, the frequency f1 of the clock signal CLK10
0 is higher than 16 * fST and lower than 32 * fST. Therefore,
In this case, the frequency close to the reference frequency fST is f10 / 16 or
In this embodiment, a frequency close to the reference frequency fST is determined as f10 / 16, and the clock signal CLK18 frequency-divided by 1/16 in the frequency dividing circuit 10 is selected.

Returning to FIG. 1, the frequency detection circuits 12 to 20 are respectively connected to the frequency selection circuit 22, and the detection signals C10 to C1
8 is input to the frequency selection circuit 22. Frequency detection circuit 22
Selects a clock signal having a frequency close to the reference frequency fST from the clock signals CLK10 to CLK20 output from the frequency dividing circuit 10 based on the input detection signals C10 to C18 according to the method described above. The clock signal CLK2
It is a circuit that outputs as 2. This clock signal CLK22
Is used as an internal clock signal.

Next, the operation of the clock signal generating circuit thus configured will be described. A reference clock signal output from a crystal oscillator or the like is input to the frequency dividing circuit 10 as a clock signal CLK10. In the frequency divider 10, the clock signal CL
Clock signal whose frequency is f10 / 2 to f10 / 32 by dividing K10
Generate CLK12 to CLK20. Clock signals CLK10 to CLK2
0 is input to the frequency selection circuit 22 and the clock signal CLK12
.About.CLK20 are further input to the frequency detection circuits 12 to 20, respectively.

In the frequency detection circuits 12 to 20, a clock signal
The frequency of CLK12 to CLK20 is set to a preset reference frequency fS.
Compared with T, when the frequency of the clock signals CLK12 to CLK20 is higher than the reference frequency fST, the levels of the detection signals C10 to C18 are set to H, and when they are lower, they are set to L. The detection signals C10 to C18 generated by the frequency detection circuits 12 to 20 are input to the frequency selection circuit 22. In the frequency selection circuit 22, based on the level pattern of the input detection signals C10 to C18, the clock signals CLK10 to
A clock signal having a frequency close to the reference frequency fST is selected from the clock signals CLK20 and output as a clock signal CLK22.

As described above, according to the first embodiment, the frequency of the input clock signal CLK10 having a stable frequency is divided to generate a plurality of clock signals CLK12 to CLK20 having different frequencies, and the clock signals CLK12 to CLK20 and the clock signal CLK12 are output. Since a clock signal having a frequency close to the reference frequency fST is selected from CLK10, by setting the reference frequency fST to a desired frequency, an internal clock signal having a desired frequency having the same frequency stability as the clock signal CLK10 is set. Can be obtained. In addition, since the frequency divider, frequency detector, and frequency selector can be configured using basic logic circuits, the circuit becomes simpler than when using an analog circuit such as a phase-locked loop (PLL). It is more stable than conventional ring oscillators against process fluctuations.

FIG. 7 is a block diagram showing a second embodiment of the clock signal generation circuit according to the present invention. This clock signal generating circuit includes a frequency dividing circuit 10, a switching circuit 24, a frequency detecting circuit 26, and a frequency selecting circuit 28, and the clock signals CLK12 to CLK20 generated by the frequency dividing circuit 10 are switched one by one by the switching circuit 24. The frequency of the selected clock signal is detected by the frequency selection circuit 26. This reduces the number of frequency detection circuits to one. The frequency dividing circuit 10 and the frequency detecting circuit 26 are the same as the frequency dividing circuit 10 and the frequency detecting circuits 12 to 20 shown in FIG.

In FIG. 7, the frequency dividing circuit 10 divides the frequency of the input clock signal CLK10 in the same manner as in the first embodiment, and outputs the divided clock signals CLK12 to CLK20 and the input clock signal CLK10. . Switching circuit 24
And the frequency selection circuit 28 are connected. The switching circuit 24 is a circuit that selects the clock signals CLK12 to CLK20 output from the frequency dividing circuit 10 one by one in a predetermined order. In addition,
The switching circuit 24 sends a timing signal indicating a switching timing to the frequency detection circuit 26 and the frequency selection circuit 28.

A frequency detecting circuit 26 is connected to the switching circuit 24. The frequency detection circuit 26 compares the frequency of the clock signal input from the switching circuit 24 with the reference frequency fST. When the frequency of the clock signal is higher than the reference frequency fST, the frequency becomes H, and when the frequency is lower, the detection becomes L. This is a circuit for generating the signal C20. Note that the frequency detection circuit 26 is
Every time a clock signal is input according to the timing signal from the CPU.

A frequency selection circuit 28 is connected to the frequency detection circuit 26. Based on the detection signal C20 from the frequency detection circuit 26, the frequency selection circuit 28 selects the reference frequency fST from the clock signals CLK10 to CLK20 output from the frequency division circuit 10.
Is a circuit that selects a clock signal having a frequency close to the above and outputs this as a clock signal CLK22. For this reason,
Based on the timing signal from the switching circuit 24, the frequency selection circuit 28 converts the input detection signal C20 into a clock signal CL.
It has a function of determining which of K10 to CLK20 it corresponds to.

Next, the operation of the clock signal generating circuit thus configured will be described. In the frequency dividing circuit 10, the frequency of the input clock signal CLK10 is divided by f10 / 2 to f10 / 2.
Generate clock signals CLK12 to CLK20 of f10 / 32. Clock signals CLK10 to CLK20 are output from the frequency divider 10,
The clock signals CLK12 to CLK20 are input to the switching circuit 24 and the frequency selection circuit 28, and the clock signal CLK10 is input to the frequency selection circuit 28. The switching circuit 24 selects the input clock signals CLK12 to CLK20 one by one according to a predetermined order, and outputs this to the frequency detection circuit 26.

The frequency detection circuit 26 compares the frequency with a preset reference frequency fST every time a clock signal is input from the switching circuit 24, and sets the detection signal C20 to H when the frequency is higher than the reference frequency fST. If it is low, it is set to L. Detection signal C2 generated by frequency detection circuit 26
0 is input to the frequency selection circuit 28. Therefore, detection signals C20-12 to C20-20 corresponding to the respective clock signals CLK12 to CLK20 are input to the frequency selection circuit 28. In the frequency selection circuit 28, when all of the detection signals C20-12 to C20-20 are input, the frequency division circuit 10
A clock signal having a frequency close to the reference frequency fST is selected from among the clock signals CLK10 to CLK20 output from the CPU and output as a clock signal CLK22.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained.
Since the number of frequency detection circuits can be reduced to one, the circuit scale can be reduced. Instead of the frequency dividing circuit 10 shown in FIG. 7, a multiplying circuit for multiplying the input clock signal CLK10 to generate a plurality of clock signals may be used. In this case, the reference frequency fST can be set higher than the frequency of the clock signal CLK10.

FIG. 8 is a block diagram showing a third embodiment of the clock signal generation circuit according to the present invention. This clock signal generating circuit includes a frequency dividing circuit 30, a multiplying circuit 32, a switching circuit
34, a frequency detection circuit 26 and a frequency selection circuit 36, and is characterized in that a clock signal having a frequency higher than the frequency f10 of the input clock signal CLK10 is generated by the multiplication circuit 32. In this embodiment, the frequency detection circuit
The frequency range of the reference frequency fST set in 26 can be expanded.

In FIG. 8, an external clock signal CL
K10 is input to the frequency dividing circuit 30 and the multiplying circuit 32. The frequency dividing circuit 30 is a circuit that divides the clock signal CLK10 by 1 / N, and can be configured using a D-FF type flip-flop similarly to the frequency dividing circuit shown in FIG. In this embodiment, the frequency dividing circuit 30 has a frequency that is 1/2 to the frequency f10 of the clock signal CLK10.
1/16 clock signals CLK12 to CLK18 are generated. On the other hand, the multiplying circuit 32 is a circuit for multiplying the clock signal CLK10 by N. For example, a harmonic is generated by using a non-linear element, and a required frequency is selected by a filter. In this embodiment, the frequency of the multiplication circuit 32 is equal to the frequency of the lock signal CLK1.
Clock signal CLK24 to CL twice to 16 times the frequency f10 of 0
Generate K30.

Switching circuits are provided in the frequency dividing circuit 30 and the multiplying circuit 32.
34 is connected to the clock signal CL generated by the frequency divider 30.
K12 to CLK18 and the clock signal CLK10 are input to the switching circuit 34 and the frequency selection circuit 36, respectively. The clock signals CLK24 to CLK30 generated by the multiplying circuit 32 are input to the frequency selection circuit 38, and the clock signals CLK26 to CLK30 are further input to the switching circuit 34. The switching circuit 34 includes a clock signal CLK1 output from the frequency dividing circuit 30 and the multiplying circuit 32.
This circuit selects 0 to CLK18 and CLK26 to CLK30 one by one according to a predetermined order, and outputs this as a clock signal CLK32. The switching circuit 34 sends a timing signal indicating a switching timing to the frequency detection circuit 26 and the frequency selection circuit 36.

The switching circuit 34 is connected to the frequency detection circuit 26. The frequency detection circuit 26 is a frequency detection circuit shown in FIG.
Each time the clock signal CLK32 is input, the frequency is compared with a preset reference frequency fST. When the frequency is higher than the reference frequency fST, the frequency becomes H,
When it is low, a detection signal C20 which becomes L is generated. For example, when the clock signal CLK24 output from the multiplication circuit 32 is input to the frequency detection circuit 26 via the switching circuit 34,
The frequency detection circuit 26 sets the detection signal C20 to H when the frequency (2 * f10) is higher than the reference frequency fST, and sets the detection signal C20 to L when the frequency (2 * f10) is lower than the reference frequency fST.

FIG. 9 shows the frequency of the input clock signal CLK10.
Detection signal output from the frequency detection circuit 26 for f10
Changes in C20-10 to C20-18 and C20-24 to C20-28 are shown. In addition,
C20-10 to C20-18 supply the clock signal CLK1 to the frequency detection circuit 26.
0 to CLK18 indicate the detection signal C20 when input, and C2
0-24 to C20-28 output the clock signal CLK24 to the frequency detection circuit 26.
7 shows the detection signal C20 when .about.CLK28 is input. FIG.
In, for example, the frequency f10 of the clock signal CLK10
Is higher than 16 * fST, the detection signals C20-18 to C20-10, C2
0-24 to C20-28 all become H, and when the frequency f10 of the clock signal CLK10 is higher than 8 * fST and lower than 16 * fST,
When only the detection signal C20-18 becomes L and the frequency f10 of the clock signal CLK10 is higher than 4 * fST and lower than 8 * fST,
The detection signals C20-18 and C20-16 become L.

Therefore, in the frequency selection circuit 36, the first
In the same manner as in the embodiment, the detection signals C20-18 to C20-1
0, the range in which the frequency f10 of the clock signal CLK10 exists is determined based on the pattern of the levels of C20-24 to C20-28, and the clock signals CLK10 to CLK18, CLK24 output from the frequency divider 30 and the multiplier 32 are determined. To CLK30, a clock signal having a frequency close to the reference frequency fST can be selected. For example, detection signals C20-18 to C20-10, C20-
When all of C24-C20-28 are H, the clock signal CLK10
Is higher than 16 * fST, so in this embodiment,
The frequency close to the reference frequency fST is determined as f10 / 16, and the clock signal CLK18 frequency-divided by 1/16 by the frequency divider 30 is selected.

Further, for example, detection signals C20-18 to C20-12
Is L and C20-10 and C20-24 to C20-28 are H;
The frequency f10 of the clock signal CLK10 is higher than fST2 * fS
Since it is lower than T, in the present embodiment, a frequency close to the reference frequency fST is determined as f10, and the clock signal CLK10 output from the frequency dividing circuit 30 is selected. Also, for example, the detection signal
When C20-18 to C20-10 and C20-24 to C20-28 are all L, the frequency f10 of the clock signal CLK10 is lower than fST / 8.
* F10 is determined, and the clock signal CLK30 multiplied by 16 by the multiplication circuit 32 is selected.

Returning to FIG. 8, a frequency selection circuit 36 is connected to the frequency detection circuit 26. The frequency selection circuit 36 is shown in FIG.
In the same manner as the frequency selection circuit 28 in the above, the detection signal C20 (C20-18 to C20-10, C20-24 to C2) from the frequency detection circuit 26
0-28), the clock signals CLK10 to CLK18, CLK24 to CLK30 output from the frequency dividing circuit 30 and the multiplying circuit 32
From among the clock signals having a frequency close to the reference frequency fST, a clock signal having a frequency close to the reference frequency
Output as CLK22. In the frequency selection circuit 36,
The detection signal C20 is the detection signal C20-18 to C20-10, C20-24 to C20-
28 is determined based on a timing signal provided from the switching circuit 34.

Next, the operation of the clock signal generation circuit configured as described above will be described. The clock signal CLK10 input from the outside is input to the frequency dividing circuit 30 and the multiplying circuit 32. The frequency dividing circuit 30 divides the frequency of the clock signal CLK10 to generate clock signals CLK12 to CLK18 having frequencies of f10 / 2 to f10 / 16.
Generate The clock signals CLK10 to CLK18 are switched by the switching circuit 36.
And the frequency selection circuit 38. On the other hand, a multiplication circuit
At 32, the clock signal CLK10 is multiplied and the frequency is 2 * f1
Generate clock signals CLK24 to CLK30 of 0 to 16 * f10.
The clock signals CLK24 to CLK28 are input to the switching circuit 34 and the frequency selection circuit 36, and the clock signal CLK30 is input to the frequency selection circuit 36.

In the switching circuit 34, the input clock signal
CLK10 to CLK18 and CLK24 to CLK28 are selected one clock signal at a time in a predetermined order and output to the frequency detection circuit 26 as a clock signal CLK32. In the frequency detection circuit 26,
Each time the clock signal CLK32 is input, its frequency is compared with the reference frequency fST. If the frequency is higher than the reference frequency fST, the detection signal C20 is set to H, and if it is lower, it is set to L. The detection signal C20 generated by the frequency detection circuit 26 is input to the frequency selection circuit 36. In the frequency selection circuit 36, based on the detection signals C20 (C20-10 to C20-18, C20-24 to C20-28), the clock signals CLK10 to CLK18, CLK24 to Select a clock signal with a frequency close to the reference frequency fST from CLK30,
This is output as a clock signal CLK22.

As described above, according to the third embodiment, the multiplying circuit 32 for multiplying the input clock signal CLK10 is added to the second embodiment.
And a plurality of clock signals having a higher frequency than the clock signal CLK10 are generated, so that a clock signal having a desired frequency can be obtained even when the frequency of the input clock signal is lower than the desired frequency. .

[0045]

As described above, according to the clock signal generating circuit of the present invention, the frequency of the reference clock signal having a stable frequency is divided by the frequency dividing means to generate a plurality of clock signals, and the frequency detecting means Since the frequency of each clock signal is compared with the reference frequency and a clock signal close to the reference frequency is selected, a clock signal having a desired frequency with stable frequency can be obtained.

In this case, by providing switching means for selecting a plurality of clock signals generated by the frequency dividing means one by one, the frequency detecting means can be reduced and the circuit scale can be reduced. Furthermore, by providing a multiplying means for generating a plurality of clock signals from the reference clock signal, a clock signal having a frequency higher than the frequency of the reference clock signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a clock signal generation circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a frequency dividing circuit in the clock signal generating circuit shown in FIG.

FIG. 3 is a diagram showing a schematic waveform in each section of the frequency dividing circuit shown in FIG. 2;

FIG. 4 is a block diagram showing an example of a frequency detection circuit in the clock signal generation circuit shown in FIG.

5A and 5B are diagrams showing schematic waveforms at various parts of the frequency detection circuit shown in FIG. 4, wherein FIG. 5A is a schematic waveform when the frequency of the input clock signal is higher than a reference frequency, and FIG. 5 is a schematic waveform when the frequency is lower than a reference frequency.

FIG. 6 is a diagram showing changes in detection signals output from each frequency detection circuit in the clock signal generation circuit shown in FIG.

FIG. 7 is a block diagram showing a second embodiment of the clock signal generation circuit according to the present invention.

FIG. 8 is a block diagram showing a third embodiment of the clock signal generation circuit according to the present invention.

9 is a diagram showing a change in a detection signal output from a frequency detection circuit in the clock signal generation circuit shown in FIG.

[Explanation of symbols]

 10, 30 divider circuit 12 to 20, 26 Frequency detection circuit 22, 28, 36 Frequency selection circuit 24, 34 Switching circuit 32 Multiplier circuit

Claims (4)

[Claims] A frequency dividing means for dividing a frequency of an input clock signal to generate a plurality of clock signals; and a clock signal for dividing a frequency of the plurality of clock signals generated by the frequency dividing means and a preset reference frequency. A plurality of frequency detecting means for comparing each time, and a frequency selecting means for selecting a clock signal having a frequency close to the reference frequency from the plurality of clock signals in accordance with a comparison result obtained by the plurality of frequency detecting means. A clock signal generation circuit characterized by including: 2. Dividing means for dividing an input clock signal to generate a plurality of clock signals, switching means for sequentially selecting a plurality of clock signals generated by the dividing means in a predetermined order, Frequency detecting means for comparing a frequency of the clock signal selected by the switching means with a preset reference frequency; and a frequency close to the reference frequency from among the plurality of clock signals according to a comparison result obtained by the frequency detecting means. Frequency selection means for selecting a clock signal having a frequency. 3. Multiplying means for multiplying an input clock signal to generate a plurality of clock signals; switching means for sequentially selecting a plurality of clock signals generated by the multiplying means in a predetermined order; Frequency detecting means for comparing the frequency of the selected clock signal with a preset reference frequency; and having a frequency close to the reference frequency from the plurality of clock signals according to the comparison result obtained by the frequency detecting means. A clock selection circuit for selecting a clock signal. 4. A frequency dividing means for dividing an input clock signal to generate a plurality of clock signals; a frequency multiplying means for multiplying the input clock signal to generate a plurality of clock signals; Switching means for sequentially selecting a plurality of clock signals generated by the means in accordance with a predetermined order; frequency detecting means for comparing a frequency of the clock signal selected by the switching means with a preset reference frequency; Frequency selecting means for selecting a clock signal having a frequency close to the reference frequency from a plurality of clock signals generated by the frequency dividing means and the multiplying means according to the comparison result obtained by the detecting means. Clock signal generation circuit.