JP2713004B2 - Clock supply method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply system for network synchronization in a digital network.

[0002]

2. Description of the Related Art Conventionally, this type of clock supply system includes a network synchronous clock supply device 21 having a built-in oscillator 22 synchronized with a network synchronous clock as shown in FIG. 3, and clock receiving units 23 and 24 in a transmission device. And a clock distribution unit 2 incorporating selectors 29 and 30 and phase control oscillators 31 and 32
5, and a selector 33 for selecting one of the clocks from the clock distribution units 25 and 26 and supplying the selected clock to the interface board 34.

[0003] Thus, the network synchronization clock supply device 21
The clock oscillated from the oscillator 22 is divided into two and inputted to the clock receiving units 23 and 24, further divided into two and interlaced, and inputted to the clock distribution units 25 and 26. One of the two clocks input to the clock distribution units 25 and 26 is selected by the selectors 29 and 30 and input to the phase control oscillators 31 and 32. Various clocks required in the transmission device are generated by the phase control oscillators 31 and 32, and supplied to the interface board 34 via the selector 33.

Normally, the clock receiving section 23 is operated as a working system, and when a failure or the like occurs in the working clock receiving section 23, the selector 29 is switched to change the clock input from the standby system clock receiving section 24. Select
The data is supplied to the interface panel 34. In this case, if there is a path length difference between the two systems of clocks supplied from the network synchronous clock supply device 21, FIG.
As shown in (B), a phase difference occurs between the clock signals input to the input terminals 100 and 101 of the clock distribution units 25 and 26.

Therefore, the phase of the clock input to the phase-controlled oscillator 31 after the switching of the selector 29 changes, so that the change in the clock phase is gradually synchronized with the clock after the switching by the phase-controlled oscillator 31 having a time constant. Further, the phase fluctuation is absorbed by the elastic memory 35 of the interface board 34.

[0006]

In the above-described conventional clock supply system, two clocks from the network synchronization clock supply device 21 are used.
If there is a path length difference between the system clocks, switching from the working system clock to the backup system clock changes the phase of the clock supplied to the transmission device, so the time slot for reading data input to the transmission device Changes. As a result, in the conventional clock supply method, a large-capacity elastic memory 35 corresponding to the phase difference of the clock must be provided for each data to be independently processed. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and eliminates the occurrence of a phase difference between clock signals at the time of switching from a working system clock to a protection system clock. It is an object of the present invention to provide a clock supply method capable of reducing the capacity and thereby reducing the cost of a product.

[0008]

In order to achieve the above object, the present invention provides a network synchronization clock supply means for supplying a clock by branching the clock into two, and a working clock for receiving one of the two branch clocks and outputting it as a working clock. Clock receiving means, standby clock receiving means for receiving the other of the two branch clocks and outputting the same as a standby clock, inputting the working and standby clocks, selecting one of the clocks, and selecting the selected clock generates various clocks based on, in the clock supply method and a plurality of clock distribution means for supplying to the interface board having the elastic memory, it of said plurality of clock distribution means
A delay means for delaying one input of the working clock or the protection clock to eliminate a phase difference between the two clocks is provided, and the various clocks respectively supplied from the plurality of clock distribution means are provided. while select a is a structure in which a selection means for supplying to said interface board.

[0009]

The clocks supplied from the network synchronization clock supply means in two branches are received by the working and protection clock means, respectively, and output as the working clock and the protection clock. When the working clock or the spare clock is input to the clock distribution means, the phase difference is eliminated by the delay means, so that both clocks are input to the clock distribution means with the same phase. In the clock distribution means, one of the working clock and the spare clock is selected, and various clocks are supplied to the interface board based on the selected clock.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a clock supply method according to this embodiment. Reference numeral 1 denotes a network synchronization clock supply device, and two branches of clocks a and b are transmitted from an oscillator 2 incorporated in the network synchronization clock supply device 1 and synchronized with the network synchronization clock.

Reference numerals 3 and 4 denote clock receiving units incorporated in the transmission apparatus. The clock a is received by the clock receiving unit 3, and the working clocks a and a that are branched into two are output. The clock b is received, and the two divided backup clocks b and b are output.

Reference numerals 5 and 6 denote clock distribution units which input and distribute the working and protection clocks from the clock receiving units 3 and 4. The clock distribution unit 5 has input terminals 100, 1
01, a selector 9 for selecting one of the working and protection clocks a and b respectively input from the phase shifter 01, and a phase control oscillator for generating various clocks c required in the transmission device based on the clock selected by the selector 9. 11 is provided,
Further, a delay element 7 is provided between the input terminal 101 and the selector 9.

The delay element 7 is an element that gives a delay to the backup clock b from the clock receiving unit 4 so as to have the same phase as the working clock a from the clock receiving unit 3. The clock distribution unit 6 also includes a delay element 8 having the same function and a selector 10.
And a phase-controlled oscillator 12. Reference numeral 13 denotes a selector for selecting one of the clocks c and c from the clock distribution units 5 and 6 and supplying the selected clock to the interface board 14 having the built-in elastic memory 15.

Next, the operation of this embodiment will be described.
Normally, the selector a is set so that the working clock a from the network synchronous clock supply device 1 is supplied to the phase control oscillator 11 of the clock distribution unit 5 and the various clocks c from the clock distribution unit 5 are supplied to the interface board 14. , 13 operate. When the clock receiving unit 3 fails, the selectors 9 and 10 of the clock distribution units 5 and 6 are switched to input the backup clock b to the phase control oscillators 11 and 12.

At this time, if there is a path length difference between the working and protection clocks a and b input to the clock distribution unit 5 (6), as shown in FIGS. A phase difference occurs between the input signal of the input terminal 100 and the input signal of the input terminal 101. However, the backup clock b, which is an input signal of the input terminal 101, is delayed by the delay element 7 (8), and is corrected to the same phase as the current clock a, as shown in FIG.

Therefore, even when switching with the selector 9 (10), the backup clock b having the same phase as the working clock a is output from the selector 9 (10) to the phase control oscillator 11 (12), Selector 9
The instantaneous interruption of the clock signal due to the switching of (10) does not occur.

Further, since various clocks c generated based on the backup clock b having the same phase as the current clock a are supplied to the interface board 14, the capacity of the elastic memory 15 can be small.

[0018]

As described above, according to the present invention, even when the phase of the backup clock input to the clock distribution means is different from the phase of the working clock, the phase difference is eliminated by the delay means. Therefore, it is not necessary to increase the capacity of the elastic memory of the interface board in accordance with the phase difference, thereby reducing the capacity of the elastic memory and reducing the cost of the product. Has an excellent effect.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a clock supply method according to an embodiment of the present invention.

2A and 2B are time charts showing a clock input to a clock distribution unit in the present embodiment. FIG. 2A is a time chart of a working clock input to an input terminal 100, and FIG. FIG. 2C is a time chart of the backup clock input to the input terminal 102 after being delayed and input to the input terminal 102.

FIG. 3 is a block diagram showing a conventional clock supply method.

4A and 4B are time charts showing a clock input to a clock distribution unit in a conventional example, FIG. 4A is a time chart of a working clock, and FIG. 4B is a time chart of a backup clock; .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Network synchronous clock supply device 3,4 ... Clock receiving part 5,6 ... Clock distribution part 7,8 ... Delay element 9,10,13 ... Selector 14 ... Interface board 15 ... Elastic memory

Claims (1)

(57) [Claims] 1. A network synchronization clock supply means for supplying a clock by branching the clock into two, a clock receiving means for receiving one of the two-branch clocks and outputting it as a working clock, and receiving the other of the two-branch clocks A standby clock receiving means for outputting a clock as a standby clock, inputting the working clock and the standby clock, selecting one of the clocks, generating various clocks based on the selected clock, and generating an elastic memory. In a clock supply system having a plurality of clock distribution means for supplying to an interface board provided with: A delay of one input of the working clock or the spare clock to each of the plurality of clock distribution means,
Delay means for eliminating the phase difference between these two clocks; and selection means for selecting one of the various clocks supplied from each of the plurality of clock distribution means and supplying the selected clock to the interface board. A clock supply method.