JPH05244132A - Clock supply system - Google Patents

Abstract

PURPOSE:To reduce the cost of a product by reducing the capacity of an elastic memory of an interface panel. CONSTITUTION:This system is provided with a network synchronizing clock supply means 1 for supplying a clock by allowing it to branch into two, an existing clock receiving means 3 for receiving one (a) of two branch clocks (a), (b) and outputting it as an existing clock (a), a stand-by clock receiving means 4 for receiving the other (b) of the two branch clocks (a), (b) and outputting it as a stand-by clock (b), and clock distributing means 5, 6 for inputting the existing and the stand-by clocks (a), (b) and selecting one clock of them, generating various clocks (c), based on the selected clock, and supplying them to an interface panel 14 provided with an elastic memory 15. In the system, delaying means 7, 8 for delaying an input of one of the existing clock (a) or the stand-by clock (b), and eliminating a phase difference of both these clocks (a), (b) are provided in the clock distributing means 5, 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network synchronization clock supply system in a digital network.

[0002]

2. Description of the Related Art Conventionally, in this type of clock supply system, as shown in FIG. 3, a network synchronization clock supply device 21 having an oscillator 22 which is synchronized with the network synchronization clock, and clock reception units 23 and 24 in the transmission device. And a clock distribution unit 2 including the selectors 29 and 30 and the phase control oscillators 31 and 32.
5 and 26, and a selector 33 that selects one of the clocks from the clock distribution units 25 and 26 and supplies it to the interface board 34.

As a result, the network synchronization clock supply device 21
The clock oscillated from the oscillator 22 is input into the clock receiving units 23 and 24 after being branched into two, and further branched into two to be entangled and input into the clock distribution units 25 and 26. One of the two systems of clocks input to the clock distribution units 25 and 26 is selected by the selectors 29 and 30 and input to the phase control oscillators 31 and 32. Then, various clocks required in the transmission device are generated by the phase control oscillators 31 and 32, and are supplied to the interface board 34 via the selector 33.

Normally, the clock receiving section 23 is operated as an active system, and when a failure or the like occurs in the active clock receiving section 23, the selector 29 is switched to change the clock input from the standby system clock receiving section 24. Select
The interface board 34 is supplied. In this case, if there is a path length difference between the two systems of clocks supplied from the network synchronization clock supply device 21, FIG.
And as shown in (B), there is a phase difference between the clock signals input to the input terminals 100 and 101 of the clock distribution units 25 and 26.

Therefore, since the phase of the clock input to the phase control oscillator 31 changes after switching the selector 29, the phase control oscillator 31 having a time constant gradually synchronizes this change in clock phase with the clock after switching. Further, the elastic memory 35 of the interface board 34 absorbs the phase fluctuation.

[0006]

In the above-mentioned conventional clock supply system, the two clocks from the network synchronous clock supply device 21 are used.
If there is a path length difference between the system clocks, switching the current system clock to the standby system clock changes the phase of the clock supplied to the transmission device, so the time slot for reading the data input to the transmission device. Changes. As a result, the conventional clock supply system has a drawback that a large capacity elastic memory 35 corresponding to the phase difference of the clocks must be provided for each data to be processed independently, and the cost of the product becomes high. It was

The present invention has been made in order to solve the above-mentioned problems, and eliminates the occurrence of a phase difference between clock signals which occurs at the time of switching from the current system clock to the standby system clock, so that the elastic memory of the interface board can be improved. It is an object of the present invention to provide a clock supply system capable of reducing the capacity and thereby reducing the cost of the product.

[0008]

To achieve the above object, the present invention provides a network synchronization clock supply means for supplying a clock in two branches, and an active clock for receiving one of the two branch clocks and outputting it as a working clock. A clock receiving means, a spare clock receiving means for receiving the other of the two-branched clocks and outputting it as a spare clock, and the above-mentioned working and spare clocks as inputs, selecting one of the clocks, and selecting the selected clock. In the clock supply system having a clock distribution means for generating various clocks based on the above, and supplying the clock to an interface board equipped with an elastic memory, the clock distribution means receives one of the working clock and the standby clock. Is provided so that the phase difference between these two clocks is eliminated. If necessary, a plurality of the clock distribution means are provided, and a selection means for selecting one of the various clocks supplied from each of the plurality of clock distribution means and supplying it to the interface board is provided. You can also

[0009]

The clocks supplied in two branches from the network synchronization clock supply means are respectively received by the working and protection clock means and output as the working clock and the protection clock. When the working clock or the spare clock is input to the clock distribution means, the delay means eliminates the phase difference, so that both clocks are input to the clock distribution means in the same phase. The clock distribution means selects one of the working clock and the spare clock, and supplies various clocks to the interface board based on the selected clock.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the clock supply system of this embodiment. Reference numeral 1 denotes a network synchronization clock supply device, and an oscillator 2 built in the network synchronization clock supply device 1 and synchronized with the network synchronization clock outputs clocks a and b of two branches.

Clock receivers 3 and 4 are built in the transmission device. The clock a is received by the clock receiver 3 and the two-divided working clocks a and a are output to the clock receiver 4. The clock b is received, and the bifurcated standby clocks b and b are output.

Clock distribution units 5 and 6 receive and distribute the working and protection clocks from the clock reception units 3 and 4, respectively. The clock distributor 5 has input terminals 100, 1
A selector 9 for selecting one of the working and standby clocks a and b respectively input from 01, and a phase control oscillator for generating various clocks c necessary in the transmission device based on the clock selected by the selector 9. 11 and are provided,
Further, the delay element 7 is arranged between the input terminal 101 and the selector 9.

The delay element 7 is an element that delays the backup clock b from the clock receiving section 4 so as to have the same phase as the working clock a from the clock receiving section 3. The clock distribution unit 6 also includes a delay element 8 having the same function and a selector 10
And a phase-controlled oscillator 12. A selector 13 selects one of the clocks c and c from the clock distribution units 5 and 6 and supplies it to the interface board 14 having the elastic memory 15 built therein.

Next, the operation of this embodiment will be described.
Normally, the selector a operates so that the active clock a from the network synchronization clock supply device 1 is supplied to the phase control oscillator 11 of the clock distribution unit 5 and various clocks c from the clock distribution unit 5 are supplied to the interface board 14. , 13 operates. When the clock receiving unit 3 fails, the selectors 9 and 10 of the clock distributing units 5 and 6 are switched to input the standby clock b to the phase control oscillators 11 and 12.

At this time, if there is a path length difference between the current and standby clocks a and b input to the clock distribution unit 5 (6), as shown in FIGS. A phase difference occurs between the input signal of 100 and the input signal of the input terminal 101. However, the spare clock b, which is the input signal of the input terminal 101, is delayed by the delay element 7 (8) and corrected to the same phase as the current clock a as shown in FIG.

Therefore, even when switching to the selector 9 (10), the spare clock b having the same phase as the working clock a is output from the selector 9 (10) to the phase control oscillator 11 (12). Selector 9
No instantaneous interruption of the clock signal occurs due to the switching of (10).

Further, since various clocks c generated based on the standby clock b having the same phase as the working clock a are supplied to the interface board 14, the capacity of the elastic memory 15 can be small.

[0018]

As described above, according to the present invention, even when the phase of the spare clock input to the clock distribution means is different from the phase of the working clock, the phase difference is eliminated by the delay means. Therefore, it is not necessary to increase the capacity of the elastic memory of the interface board in response to the phase difference, and this enables the elastic memory to have a smaller capacity and achieve the cost reduction of the product. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock supply system according to an embodiment of the present invention.

2A and 2B are time charts showing a clock input to a clock distribution unit in the present embodiment, FIG. 2A is a time chart of a working clock input to an input terminal 100, and FIG. 2B is an input terminal. 2C is a time chart diagram of the spare clock input to the input terminal 101, and FIG. 2C is a time chart diagram of the standby clock input to the input terminal 102 after being delayed.

FIG. 3 is a block diagram showing a conventional clock supply system.

FIG. 4 is a time chart diagram showing a clock input to a clock distribution unit in a conventional example, FIG. 4 (A) is a time chart diagram of a working clock, and FIG. 4 (B) is a time chart diagram of a standby clock. ..

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Network synchronization clock supply device 3, 4 ... Clock receiving part 5, 6 ... Clock distribution part 7, 8 ... Delay element 9, 10, 13 ... Selector 14 ... Interface board 15 ... Elastic memory

Claims (2)

[Claims] 1. A network synchronization clock supply means for supplying a two-branched clock, a working clock receiving means for receiving one of the two-branching clocks and outputting it as a working clock, and another for receiving the other of the two-branching clocks. And a spare clock receiving means for outputting as a spare clock and selecting one of the clocks, and generating various clocks based on the selected clock to generate an elastic memory. In a clock supply system having a clock distribution means for supplying to an interface board provided with a delay for delaying the clock distribution means by inputting one of the working clock and the spare clock to eliminate the phase difference between the two clocks. A clock supply system characterized by comprising means. 2. A plurality of clock distribution means are provided, and a selection means is provided for selecting one of the various clocks supplied from each of the plurality of clock distribution means and supplying the selected clock to the interface board. The clock supply system according to claim 1.