JP2000278261A - Isdn connection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disturbance in an output clock at the switching of an input clock of a PLL to generate a multiplex clock in a clock changeover control circuit of an ISDN connection device. SOLUTION: The ISDN connection device comprising a plurality of ISDN interface circuits (ISDN i/f0-n) 4-0-4-n, a channel data transmission reception section that controls transmission reception of data multiplexed on a channel, a PLL (1-2) to take synchronization of a clock and a clock changeover control circuit 1, multiplexing data of a plurality of the ISDN interface circuits (ISDN i/f0-n) 4-0-4-n by using a high speed clock synchronously with an ISDN and giving the result to the channel data transmission reception section 3 that applies transmission reception processing to the data in a lot is configured such that two frequency dividers (frequency divider A) for a system A and (frequency divider B) for a system B of a PLL are provided to the clock changeover control circuit, and a circuit selecting sequentially a clock for phase matching for an active/standby system is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ISDN for transmitting and receiving data of a plurality of ISDN interface circuits in a single channel data transmitting / receiving section.
Regarding the connection device, in particular, the clock switching control circuit is provided with a frequency divider and a phase adjustment circuit for the backup input clock, and the ISDN interface circuit used as the working input clock stops and switches to the input clock of another ISDN interface circuit. ISDN suitable for preventing data error even in case of
Related to the connection device.

[0002]

2. Description of the Related Art In a conventional clock switching control circuit of an ISDN connection device, for example, a clock switching control circuit shown in FIG. 2, a plurality of ISDN interfaces are provided as shown in FIG.
Clock (R) of the input circuit (ISDN i / f0-n)
CLK0 / RCLK1) is synchronized in frequency as an ISDN network, but is not necessarily synchronized in phase. Therefore, the current input clock (RCLK
0) and the ISDN interface circuit (ISDN
i / f0) stops and the input clock (RCLK) of another ISDN interface circuit (ISDN i / f1)
In the case of switching to 1), the phase is largely shifted and the output (PD-OUT) is increased by the phase comparator, and it is not possible to prevent the clock from being out of synchronization or shifting the phase of the PLL output clock. Was.

As a prior art related to such a clock switching control circuit, there is one disclosed in Japanese Patent Application Laid-Open No. H10-65536.

[0004]

For this purpose, a plurality of I
In the case where transmission / reception data transmission / reception of the SDN interface circuit is collectively transmitted / received by one channel data transmission / reception unit, a data error occurs in another ISDN interface circuit by stopping one ISDN interface circuit. That could not be prevented. For this reason, multiple ISDN
The transmission / reception of the transmission / reception data of the interface circuit can be collectively performed by one channel data transmission / reception unit, but cannot be easily realized.

[0005] The same applies to the clock switching circuit described in Japanese Patent Application Laid-Open No. 10-65536. In the clock switching circuit described in JP-A-10-65536,
Even if the clock can be maintained when the clock is cut off, the phase is not significantly shifted after switching.

First, in a conventional clock switching control circuit, a plurality of ISDN interface circuits (ISD
N i / f0-n) input clocks (RCLK0-n)
Is synchronized in frequency as an ISDN network, but the phase is not necessarily synchronized, and the input clock of another ISDN interface circuit is stopped by stopping the ISDN interface circuit which is the working input clock. In the case of switching to, it is required to prevent the clock from being disturbed such that the phase is largely shifted and the PLL is out of synchronization or the phase of the PLL output clock is shifted.

Second, when the ISDN interface circuits are all stopped, the two systems A (frequency divider A) and B (frequency divider B) are kept in phase with each other. I
When the SDN interface circuit is restored and the clock returns to the normal state, it is necessary to stop the phase adjustment and supply it to the phase comparator to shorten the PLL pull-in time.

[0008] It is an object of the present invention to stop another ISDN interface circuit which is being used as an input clock.
When switching to the input clock of the N interface circuit, the phase shifts greatly, causing loss of PLL synchronization,
It is an object of the present invention to provide an ISDN connection device capable of preventing clock disturbance such as shifting of the phase of an LL output clock.

Another object of the present invention is to provide a system in which both the system A (frequency divider A) and the system B (frequency divider B) are in phase with each other when the ISDN interface circuit is stopped. When the ISDN interface circuit is restored and the clock returns to normal, the phase adjustment is stopped and supplied to the phase comparator, so that the ISDN connection that can reduce the PLL synchronization pull-in time can be achieved. It is to provide a device.

[0010]

The above object is achieved by a plurality of ISs.
DN interface circuit (ISDN i / f0-n),
Channel data transmission / reception unit for controlling transmission / reception of data multiplexed on a channel, PLL for clock synchronization
And a clock switching control circuit, which multiplexes data of a plurality of ISDN interface circuits (ISDNi / f0 to n) with a high-speed clock synchronized with the ISDN network, passes the data to a channel data transmission / reception unit, and collectively performs transmission / reception processing.
In the N connection device, a clock switching control circuit uses two PLL frequency dividers of A system (frequency divider A) / B system (frequency divider B), and sequentially switches clocks for matching phases between active and standby. This is achieved by configuring with the circuitry used.

Further, when all the ISDN interface circuits are stopped in the clock switching control circuit of the ISDN connection device, A system (frequency divider A) / B system (frequency divider B)
In both cases, a phase matching state is provided, and when the ISDN interface circuit is restored and a normal clock is returned, a circuit for stopping the phase matching and supplying the circuit to the phase comparator is provided.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an ISDN connection apparatus according to an embodiment of the present invention. Multiple ISDN interface circuits (ISD
N i / f 0 to n), a channel data transmission / reception unit for controlling transmission / reception of data (Data) multiplexed in a channel, a PLL for clock synchronization, and a clock switching control circuit, and a high-speed synchronized with an ISDN network. ISD for multiplexing data of a plurality of ISDN interface circuits (ISDN i / f0 to n) with a clock (MCLK) and passing the data to a channel data transmitting / receiving unit for collective transmission / reception processing
Construct an N-connection device.

FIG. 3 shows a clock switching control circuit and a PLL of the ISDN connection device according to the embodiment. The clock switching control circuit is an ISDN interface circuit (ISDN i / f
0 to n) clock signals (RCLK0 to RCLK)
CLK-ST0-n) Therefore, which clock (RC
LK0-n) is supplied to the frequency divider A / frequency divider B, or the standby frequency divider is reset at the rising edge of the selected clock (RCLK0-n) and supplied to the phase comparator of the PLL. Switch the clock.

FIG. 5 is a time chart during normal operation (before switching) of the clock switching control circuit and the PLL of the ISDN connection device of the embodiment. The switching control unit controls the clock (RCL) of the ISDN interface circuit (ISDN i / f0).
K0) and the input clock (PLL-
IN / M). Further, the other input clock (PLL-IN / S) of the phase comparator selects the output clock (CCLK-A) having the period A. The division period A of the working system is determined by an ISDN interface circuit (ISDN
i / f0), the reset of the rising edge of the clock (RCLK0) is suspended, but the phase matching operation of the PLL causes the ISDN interface circuit (ISDN i) to reset.
/ F0) clock (RCLK0) and the output clock (CCLK-A) of the divisional period A have the same phase (the phases are synchronized). When the phases are synchronized, the output (PD-OUT) of the phase comparator is stable.

On the other hand, the division period B of the preliminary type is based on the clock (R) of the ISDN interface circuit (ISDN i / f1).
The rising edge of CLK1) is reset, and the phase of the output clock (CCLK-B) of the frequency divider B is adjusted to match the phase of the clock (RCLK1).

FIG. 6 is a time chart during normal operation (at the time of switching) of the clock switching control circuit and the PLL of the ISDN connection device of the embodiment. The clock switching control circuit operating as shown in FIG. 5 is an ISDN interface circuit (ISD
N / f1) detects that the state signal (RCLK-ST0) of the clock (RCLK1) is turned off, and supplies the clocks (PLL-IN / M and PLL) to be supplied to the phase comparator.
-IN / S).

A clock supplied to the phase comparator (PLL-
IN / M) is an ISDN interface circuit (ISDN)
The clock (PLL-IN / S) for supplying the clock (RCLK1) of (i / f1) to the phase comparator selects the output clock (CCLK-B) of the divided cycle B. At this time, FIG.
As shown by, two clocks (RCLK1
And the phase of CCLK-B), the output (PD-OUT) of the phase comparator can be switched while remaining stable.

Further, since the frequency divider B becomes a working system and can synchronize the phase with the input clock (RCLK1) by the operation of the PLL, it is necessary to reset the rising edge of the input clock (RCLK1) and adjust the phase. Abort.

On the other hand, the divisional period A becomes a standby system, and prepares for the next normal input clock (RCLK
The operation of adjusting the phase by resetting the rising edge in 2) is started. (At this time, the PLL stops input and enters a free-run state.) Further, all input clocks (R
CLK0-n) are stopped (RCLK-ST0-n are all off), both the frequency divider A / frequency divider B are standby systems, and the default input clock (RCLK0 / RCLK-ST0-n)
The operation of resetting the rising edge of 1) and adjusting the phase is continued. When any one of the input clocks becomes normal, the input clock is reset at the rising edge of the frequency divider A to perform the operation of adjusting the phase, and then the clock is switched. Accordingly, the PLL supplies clocks (PLL-IN / M and PLL-IN / M) supplied to the phase comparator.
Since the pull-in operation can be started from the state where the phase of (/ S) is close, the amount of phase variation can be small, and the PLL pull-in time can be shortened.

[0021]

According to the present invention, the ISDN interface circuit used as the current input clock stops and another ISDN
When the input clock is switched to the input clock of the DN interface circuit, it is possible to prevent the clock from being out of phase and causing the PLL to lose synchronization or to shift the phase of the PLL output clock.

Further, in the clock switching control circuit of the ISDN connection device, when all the ISDN interface circuits are stopped, both the A system (frequency divider A) / B system (frequency divider B) With the
When the DN interface circuit is restored and the clock returns to the normal state, a circuit for stopping the phase adjustment and supplying the phase to the phase comparator is provided, so that the initial PLL pull-in time can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an ISDN connection device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a clock switching control circuit of the ISDN connection device of the embodiment.

FIG. 3 is a circuit diagram of an example of a conventional clock switching control circuit.

FIG. 4 is a time chart of an example of a conventional clock switching control circuit.

FIG. 5 is a time chart (during normal operation) of a circuit diagram of a clock switching control circuit of the ISDN connection device according to one embodiment of the present invention;

FIG. 6 is a time chart (operating at the time of switching) of a circuit diagram of a clock switching control circuit of the ISDN connection device according to one embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Clock switching control circuit, 1-2 ... PLL, 3 ... Channel data transmission / reception part, 4-0-n-0 ... ISDN interface circuit,

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04Q 11/04 304 H04L 7/02 B 5K101 9A001 (72) Inventor Hideharu Kameno 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture F-term in the Server Development Division, Hitachi, Ltd. (Reference) HA07 5K101 LL03 MM04 VV05 9A001 BB04 CC04 LL02

Claims (3)

[Claims] A plurality of ISDN interface circuits, a channel data transmission / reception unit for controlling transmission / reception of data multiplexed on a channel, and a PLL for clock synchronization.
And a clock switching control circuit for multiplexing data of a plurality of ISDN interface circuits with a high-speed clock synchronized with an ISDN network, passing the data to a channel data transmitting / receiving unit, and performing collective transmission / reception processing. The clock switching control circuit includes a plurality of PLL frequency dividers,
The frequency divider is controlled to generate a clock close to the phase of the received clock output of the corresponding ISDN interface circuit, and the ISDN interface circuit currently used as the input clock for generating the multiplexed clock is stopped. When switching the input clock, simultaneously with the switching of the PLL input clock, the frequency divider is also switched to make the comparison clock of the phase comparator a clock close to the phase of the input clock. Stop and fix the divider, frequency-synchronize with the input clock before switching, and use as the comparison clock whose phase almost matches the input clock after switching, and use it as the input clock with the phase in the PLL phase comparator. / An ISDN connection device that continuously supplies a comparison clock. 2. The system according to claim 1, wherein said frequency divider comprises two systems, an A system (frequency divider A) and a B system (frequency divider B). By switching and using the frequency divider (frequency divider A / frequency divider B), the clock switching control circuit allows a plurality of ISDN interface circuits (I
2. The ISDN connection device according to claim 1, wherein a plurality of frequency dividers are prepared in accordance with the SDN i / f0 to SDn. 3. In the clock switching control circuit of the ISDN connection device, when all the ISDN interface circuits are stopped, the A system (frequency divider A) / B system (frequency divider B) Keep the two in phase, and
When the N interface circuit is restored and the clock returns to normal, the phase adjustment is stopped and supplied to the phase comparator.
3. The ISD according to claim 2, wherein the synchronization pull-in time of the LL is reduced.
N connection device.