JP2004320393A - Clock feeding system and communication data processing apparatus used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a clock feeding system which enables the non-interruption of data and phase matching in switching clock sources while the reliability of multiplexing is achieved. <P>SOLUTION: A scale of clock processing circuit for non-interruption switching is reduced by mounting distributed clock sources to each interface processing unit, mutually transmitting and reducing a frame pulse obtained by dividing the output of the clock source and a clock between interface processing units, matching phases for the frame pulse which are selected for transmitting the frame pulse to the other processing unit, and controlling clock jitter by a PLL circuit located in the interface processing unit. Moreover, a high precision clock source is preferentially selected by mounting a high precision clock source conforming to the SDH standard to the SDH system interface processing unit mounting a low precision clock source not conforming to this standard to the Ethernet (R) system interface processing unit. If high precision clock sources become defective completely, the lower precision clock sources are selected. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock supply system and a communication data processing device used for the same, and more particularly, to communication such as a cross-connect device for distributing data between different types of data such as an SDH (Synchronous Digital Hierarchy) system or an Ethernet (R) system or between data of the same type. The present invention relates to a clock supply method suitable for application to a data processing device.
[0002]
[Prior art]
A configuration of a clock supply system in a conventional device of this type has a configuration as shown in FIG. Referring to FIG. 7, the high-precision clock sources a-32 and b-32 are mounted on clock processing units a and b different from the interface processing units 1 to n, and the clock processing units a and b form a duplex. are doing. In this duplex configuration, a low-frequency reference frame pulse is transmitted from the master (a) to the slave (b) to adjust the frequency and the frame pulse phase, and the reference frame pulse is sent to each of the interface processing units 1 to n. By generating PLL (Phase Locked Loop) circuits a-31 and b-31 necessary to generate a high-frequency clock to be transmitted and to suppress jitter, data instantaneous interruption during clock source switching is realized. It is supposed to.
[0003]
Then, a clock and a frame pulse are transmitted from the duplicated clock processing units a and b to each of the interface processing units 1 to n. In each of the interface processing units 1 to n, the clock processing unit selection circuits 1-33 to n-33 are transmitted. To select the working clock processing unit. Further, the PLL circuits 1-34 to n-34 and the frequency divider circuits 1-35 to n-35 use the selected clocks to perform various processes used for their own SDH or Ethernet (R) interface processing and distributed cross-connect processing. A clock having a frequency is generated, and a clock having a required frequency is distributed to each of the interface processing units 1-36 to n-36 and the distributed cross-connect processing units 1-37 to n-37.
[0004]
In the above conventional example, the clock source is duplicated, but a multiplexed configuration is disclosed in Patent Document 1. With reference to this patent document, in each of a plurality of communication cards, a clock extracted from a transmission path is supplied to a bus-like clock signal line common to the communication cards, and a desired one is extracted from the bus-like clock. The clock is selected and used by each communication card. Here, if the selected clock is interrupted due to a failure or the like, the clock is switched to another clock of the bus-like clocks, that is, a clock from another communication card.
[0005]
[Patent Document 1]
JP-A-6-284119, pages 4 and 5, FIG.
[0006]
[Problems to be solved by the invention]
A first problem in the configuration shown in FIG. 7 is that when a clock source and a clock processing circuit used in the apparatus have a redundant configuration, an attempt to increase the number of redundant configurations requires a new clock processing unit. Must be increased by that few minutes.
[0007]
The reason is that in order to adjust the phase of the reference frame pulse mutually transmitted and received in the dual clock processing unit, to generate a high-frequency clock to be transmitted to each interface processing unit from this reference frame pulse, and to suppress jitter. This is because the required PLL circuit is mounted, the circuit scale becomes large, and a clock processing unit must be provided separately from the interface processing unit.
[0008]
A second problem in the configuration shown in FIG. 7 is that if both of the dual high-precision clock sources a-32 and b-32 mounted in the device fail, the entire system will be down. In this case, it is not only impossible for the system to use a high-precision clock source to perform circuit switching between SDH-based interfaces that require data conduction, but also to use a low-precision clock source. Circuit switching between Ethernet (R) -based interfaces that allow data conduction is also impossible.
[0009]
The reason is that the data processing of the SDH type interface processing unit which may be accommodated may be performed because the clock source is physically independent regardless of the type and the number of interface processing units accommodated in the device. For this purpose, a high-precision clock source must be provided, and an increase in the number of mounted clock sources leads to an increase in the number of accommodated units, which becomes difficult.
[0010]
Although the technology described in Patent Document 1 has an advantage that the number of redundancy depends on the number of communication cards, no instantaneous interruption of data at the time of clock switching or phase matching is taken into consideration at all. There is a problem in system stability at the time of clock switching. Further, in this technique, an SDH interface that requires data conduction using a high-precision clock source, and an Ethernet (R) interface that permits data conduction using a low-precision clock source are described. Is not considered at all, and therefore, the second problem described above also exists.
[0011]
An object of the present invention is to provide a clock supply system that enables instantaneous interruption of data and phase alignment when switching clock sources while ensuring reliability by multiplexing, and a data communication processing device used therefor.
[0012]
Another object of the present invention is to provide a communication system that can operate with a low-precision clock source even if a failure occurs in a high-precision clock source, even in a heterogeneous communication system in which the accuracy of a clock source is different. An object of the present invention is to provide a clock supply system operable effectively and a data communication processing device used for the clock supply system.
[0013]
[Means for Solving the Problems]
A clock supply system according to the present invention is a clock supply system in a communication device having a plurality of communication data processing units, wherein each of the plurality of communication data processing units has a clock source and a clock obtained from an output of the clock source. And distribution means for distributing the frame pulse to another communication data processing unit, a selection means for selecting a clock and a frame pulse to be used in the own communication data processing unit according to an external selection signal, Phase adjusting means for adjusting the phase of the frame pulse obtained by its own clock source to the frame pulse and outputting the frame pulse to the distributing means. Selection control means for generating the external selection signal in accordance with a given priority. It is.
[0014]
A communication data processing device according to the present invention is a communication data processing device that constitutes a communication system, and distributes a clock source and a clock and a frame pulse obtained from an output of the clock source to another communication data processing unit. Means, a selection means for selecting a clock and a frame pulse to be used in the own communication data processing unit according to an external selection signal, and a frame pulse obtained by the clock source with respect to the frame pulse selected by the selection means. Phase adjusting means for performing phase adjustment and outputting the frame pulse to the distributing means is provided.
[0015]
The operation of the present invention will be described. In a cross-connect device for distributing data between different types of data such as SDH system and Ethernet (R) system or the same type of data, a clock source is distributed and mounted in an interface processing unit of various data, and a clock used in the interface processing is used. And the frame pulse are frequency-divided from the clock source and distributed among the respective interface processing units. When the number of interface processing units is n, the reliability of the selected clock source is ensured by making the selected clock source n-fold.
[0016]
Also, there is interface processing that requires data processing with a high-precision clock source to comply with the high-precision clock jitter standard, and interface processing that allows data processing with a low-precision clock source in comparison with this. When the clock sources are mixed, prioritize the selection of the clock source, select the high-precision clock source with high priority, and select the low-precision clock source with low priority. In this case, the entire system can be prevented from being down by effectively conducting a data signal by cross-connect between interfaces that allow data conduction using a low-precision clock source.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, a clock supply system according to the present invention includes interface processing units (hereinafter, “units” are referred to as “slots”) 1 to n for processing SDH-based signals or Ethernet (R) -based signals; Contains.
[0018]
These interface processing slots 1 to n include clock sources 1-1 to n-1 for operating the entire apparatus and clocks i-101 to i-101 for dividing the output of these clock sources and transmitting the divided signals to other slots. Frequency divider circuits 1-2 to n-2 for generating 10n (i is an integer of 1 to n) and frame pulses i-201 to i-20n, and a frame pulse to be transmitted to another slot is selected by a selection circuit And phase adjusting circuits 1-3 to n-3 for adjusting the phase of the frame pulse.
[0019]
The interface processing slots 1 to n include a clock source selection circuit 1 for selecting a clock source according to a selected clock source instruction from the clocks 1-101 to n-101 and the frame pulses 1-201 to n-20n received from other slots. -4 to n-4 and 1-6 to n-6, clock disconnection detection circuits 1-5 to n-5 for detecting disconnection of received clocks 1-101 to n-101, and received frame pulses Frame pulse disconnection detection circuits 1-7 to n-7 for detecting disconnections of 1-201 to n-201.
[0020]
Further, the interface processing slots 1 to n are provided with a PLL circuit 1 to generate various high-frequency clocks necessary for performing interface processing in the slots from the clocks selected by the clock source selection circuits 1-4 to n-4. 9 to n-9, frequency dividing circuits 1-10 to n-10, interface processing circuits 1-11 to n-11 for performing SDH interface processing or Ethernet (R) interface processing for each slot type, and each interface It has distributed cross-connect processing circuits 1-12 to n-12 for distributing them in the processing slots and performing a cross-connect function.
[0021]
When a high-precision clock source and a low-precision clock source are mixed, the device control unit 7 includes a priority setting circuit 13 for setting the priority of selection, and priority setting information in the device control unit 7. And a clock source selection control circuit 8 for determining a selected clock source based on the clock disconnection detection information and the frame pulse disconnection detection information.
[0022]
In FIG. 1, there are interface processing slots 1 to n for processing an SDH system signal or an Ethernet (R) system signal, and these are cross-connect devices for performing circuit switching between the SDH system signal and the Ethernet (R) system signal. Yes, clock sources 1-1 to n-1 are distributed and mounted in interface processing slots 1 to n, respectively.
[0023]
Conventionally, in such an apparatus, the clock source must be mounted in a different slot from the interface processing slot, and the number of additional slots must be increased in order to perform switching by making the clock source redundant. Therefore, the redundancy of the clock source has been limited up to the duplication. In switching of clock sources by duplication, data instantaneous interruption is generally realized at the time of switching.To do so, the phases of frame pulses generated from both clock sources that make up the duplication are matched, and from both clock sources, It is necessary to suppress the jitter of the frequency clock used in the generating apparatus (a slight shift of the same frequency clock generated in both slots).
[0024]
In the conventional configuration, a low-frequency reference frame pulse is transmitted from a master slot constituting a dual clock source to a slave slot to adjust a frame pulse phase, and further transmitted from the reference frame pulse to each interface processing slot. By installing a PLL circuit necessary to generate high-frequency clocks and suppress jitter, instantaneous interruption of data when switching clock sources is realized. However, the mounting of this PLL circuit increases the circuit scale. The clock processing circuit had to be mounted in another slot.
[0025]
Therefore, in the present invention, low-frequency frame pulses i to 201 to i-20n obtained by dividing the outputs of the clock sources 1-1 to n-1 mounted in a distributed manner by the frequency dividing circuits 1-2 to n-2, and High frequency clocks i-101 to i-10n are mutually transmitted and received between the interface processing slots. At this time, when transmitting the frame pulse to another slot, the phase matching circuits 1-3 to n-3 determine the phase of the frame pulse selected by the clock source selection circuits 1-6 to n-6. Send after adjusting.
[0026]
For clock jitter, PLL circuits 1-9 to n-9 originally provided in interface processing slots are used to generate various high-frequency clocks used in interface processing and distributed cross-connect processing. Suppress.
[0027]
With such a configuration, without a PLL circuit for generating a high-frequency clock and suppressing jitter, which is conventionally required for the clock processing slot, the data can be instantaneously interrupted when the clock source is switched. The clock processing circuit can be mounted in the interface processing slot while reducing the circuit scale.
[0028]
The selection switching of the clock source is determined by the clock source selection control circuit 8 in the device control unit 7 that receives the results of the clock disconnection detection circuits 1-5 to n-5 and the frame pulse disconnection detection circuits 1-7 to n-7. Then, a clock source in which no clock interruption or frame pulse interruption has occurred is switched and selected by the clock source selection circuits 1-4 to n-4 and 1-6 to n-6.
[0029]
With such a configuration, the clock source selection always selects the same clock source as the device. From the selected clock, PLL circuits 1-9 to n-9 and frequency dividers 1-10 to n-10 generate various high-frequency clocks required for processing in the slot, and perform interface processing together with the selected frame pulse. Used in circuits 1-11 to n-11 and distributed cross-connect processing circuits 1-12 to n-12. By adopting such a configuration, in the present invention, when the number of installed interface processing slots is n, reliability is ensured by making the selected clock source n-fold.
[0030]
Also, this cross-connect device is used for circuit switching for multiplexing and mapping Ethernet (R) signals onto SDH signals, circuit switching between SDH signals, and circuit switching between Ethernet (R) signals. Is performed. At this time, the SDH interface processing slot and the Ethernet (R) interface processing slot are not limited in terms of the mounting of the slots 1 to n and can be interchanged. There may be accommodation of processing slots only. Therefore, in the present invention, a high-precision clock source that complies with the SDH standard is mounted in the SDH interface processing slot, and a low-precision and low-cost interface that does not satisfy the standard is installed in the Ethernet interface processing slot. Equipped with a clock source. When the SDH system and the Ethernet (R) system interface processing slot coexist, the priority is set by the priority setting circuit 13 in the device control unit 7, and a high-precision clock source is preferentially selected, and all of them have failed. If so, choose a low-precision, low-cost clock source.
[0031]
As a result, when all of the high-precision clock sources fail, the circuit switching function for multiplexing and mapping Ethernet (R) signals to SDH signals and the circuit switching function between SDH signals are invalid. However, the present invention realizes effective conduction of data signals by circuit switching between Ethernet (R) -based interfaces that allow data conduction using a low-precision clock source.
[0032]
Here, the phase matching circuits 1-3 to n-3 will be described in detail with reference to FIG. The phase matching circuit selects the clock source of its own slot from the selected clock source number (slot) information specified by the clock source selection control circuit 8 and the insertion slot number information indicating its own slot position. A matching judgment circuit 21 for judging whether or not the clock pulse of the own slot is selected, a phase matching control circuit 22 for controlling not to perform the phase adjustment of the frame pulse, and selecting the divided frame pulse. A phase matching circuit 23 for adjusting the phase of the frame pulse to generate a transmission frame pulse.
[0033]
Next, the operation of the block diagram of FIG. 1 will be described with reference to the drawings. In FIG. 1, clock sources 1-1 to n-1 are dispersedly mounted in interface processing slots 1 to n for processing an SDH system signal or an Ethernet (R) system signal. The frequency is divided by the frequency dividing circuits 1-2 to n-2, and the frame pulses i-201 to i20n of low frequency and the clocks i-101 to i-10n of high frequency are mutually transmitted and received between the interface processing slots.
[0034]
At this time, for the framer, the phase is adjusted to the frame pulse selected by the clock source selection circuits 1-6 to n-6 by the phase adjustment circuits 1-3 to n-3, and then transmitted. At this time, if the clock source of the own slot is selected, there is no need to adjust the frame pulse phase. Therefore, as shown in FIG. 2, the match determination circuit 21 determines the information of the selected clock source (selected slot number) specified by the clock source selection control circuit 8 and the insertion slot number indicating the position of the own slot. A match determination is made. If the information matches, and the clock source of the own slot is selected, the phase matching control circuit 22 controls the phase matching circuit 23 so as not to operate.
[0035]
The clocks transmitted from the other slots and the respective interface processing slots that have received the frame pulse are received by the clock loss detection circuits 1-5 to n-5 and the frame pulse loss detection circuits 1-7 to n-7. And the detection of the interruption of the frame pulse, and transmits the result to the clock source selection control circuit 8 in the device control section 7. The clock source selection circuit 8 selects a clock source of an interface processing slot in which no clock disconnection or frame pulse disconnection has occurred based on the clock and frame pulse disconnection information, transmits an instruction to each interface processing slot, and Source and selector circuits 1-4 to n-4 and 1-6 to n-6 select and switch clocks and frame pulses.
[0036]
With this operation, the clock source selection always selects the same clock source as the device. The selected clock is subjected to jitter suppression by PLL circuits 1-9 to n-9 and frequency divider circuits 1-10 to n-10, SDH or Ethernet (R) interface processing in its own slot, and distributed cross-connect. Clocks of various frequencies used for processing are generated, and clocks of necessary frequencies are distributed to the interface processing units 1-12 to n-12 and the distributed cross-connect processing units 1-13 to n-13.
[0037]
By such an operation, instantaneous data interruption conduction at the time of clock source selection switching is realized without mounting a PLL circuit for generating a high-frequency clock transmitted to each interface processing slot, thereby reducing the circuit scale. A clock processing circuit can be mounted on the interface processing slot. According to the present invention, when the number of mounted interface processing units is n, the reliability is ensured by n-folding of the selected clock source.
[0038]
In addition, as shown in FIGS. 3, 4, and 5, the present cross-connect device includes distributed cross-connect processing circuits 1-12 to n-12 as SDH interface processing slots and Ethernet (R) interface processing slots. Circuit switching for multiplexing and mapping Ethernet (R) signals onto SDH signals, circuit switching between SDH signals, and circuit switching between Ethernet (R) signals Three types are performed.
[0039]
At this time, the SDH interface processing slot and the Ethernet (R) interface processing slot are not limited in terms of the mounting of the slots 1 to n and can be interchanged. There may be a mixture, accommodation of only SDH interface processing slots as shown in FIG. 4, and accommodation of only Ethernet® interface processing slots as shown in FIG.
[0040]
As shown in FIGS. 3 and 4, the SDH-system interface processing slots are equipped with high-precision clock sources 1-1 to n-1 which need to comply with the SDH standard of ± 20 ppm or less. 3. As shown in FIG. 5, low-precision, low-cost clock sources 3-1 to n-1 that do not satisfy this standard are mounted in the Ethernet (R) interface processing slot. Thus, by mounting a low-cost clock source in the Ethernet (R) interface processing slot, the cost can be reduced as compared with mounting a high-precision clock source in all interface processing slots. .
[0041]
When the SDH system and Ethernet (R) system interface processing slots coexist as shown in FIG. 4, the priority setting circuit 13 in the device control unit 7 shown in FIG. 1 preferentially selects a high-accuracy clock source. The priority is set, and the clock source selection control circuit 8 controls so as to select a high-accuracy clock source mounted in the SDH interface processing slots 1 and 2.
[0042]
Here, when the clock loss detection circuit or the frame pulse loss detection circuit detects the failure of all the high-precision clock sources due to the detection of the clock or the frame pulse loss, the Ethernet (R) interface slots 3 to n are connected. Select an on-board low-precision clock source. Here, when only a small number of high-precision clock sources are mounted on the device as in the conventional case, and when all the high-precision clock sources fail, the Ethernet (R) signal is multiplexed into the SDH signal. Not only the signal conduction due to the circuit switching for the mapping and the signal conduction due to the circuit switching between the SDH signals, but also the signal conduction due to the circuit switching between the Ethernet (R) interfaces becomes invalid.
[0043]
On the other hand, in the operation according to the present invention, when all of the high-precision clock sources fail, signal conduction by circuit switching for multiplexing and mapping the Ethernet (R) system signal to the SDH system signal and the SDH system signal Although signal conduction due to circuit switching between them becomes invalid, data signals due to circuit switching between Ethernet (R) -based interfaces that allow data conduction using a low-precision clock source are effectively conducted. Realize that.
[0044]
Since the low-precision clock source is installed in the Ethernet (R) interface processing slot, the number of Ethernet (R) interface processing slots increases, and the amount of data conduction due to circuit switching between Ethernet (R) interfaces is large. As the number of low-accuracy, low-cost clock sources increases, the number of data sources can be gradually increased.
[0045]
Next, another embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 6, the present embodiment is different from the embodiment shown in FIGS. 1 and 2 in that a working spare information setting circuit 14 is newly provided in the device control unit 7. If the interface processing slot has a redundant configuration of redundancy and the working / standby exists in the interface processing slot, the information is set in the working / standby information setting circuit 14 and transmitted to the clock source selection control circuit 8, and the clock is selected. The source selection control circuit 8 controls so as not to select the clock source mounted on the standby interface processing slot.
[0046]
The reason is that there is a possibility that the interface processing slot of the standby system will be removed, and at that time, control is performed to prevent data from being interrupted by selecting the clock source of the slot. Therefore, this control has a new effect that the clock supply system of the present invention can cope with a redundant redundant configuration of interface processing slots.
[0047]
In the embodiment described above, a case where the present invention is applied to a cross-connect device that performs data distribution between different types of data of the SDH system or the Ethernet (R) system or data of the same type is described, but the present invention is not limited to this. The present invention is applicable to a clock supply system of a communication system having a communication data processing unit that handles various communication data.
[0048]
【The invention's effect】
The first effect of the present invention is that when a clock source and a clock processing circuit used in the device have a redundant configuration, the number of interface processing slots can be increased without increasing the number of new clock processing slots. That is, reliability can be ensured by n-folding of the selected clock source.
[0049]
The reason is that a clock source is distributed and mounted in each interface processing slot, a frame pulse obtained by dividing the output of the clock source and a clock are mutually transmitted and received between the interface processing slots, and the frame pulse is transmitted to another slot. By adjusting the phase to the frame pulse selected at the time and using a PLL circuit provided in the interface processing slot to suppress clock jitter, the clock processing circuit scale for instantaneous interruption switching can be reduced. This is because the clock processing circuit is reduced and the clock processing circuit is mounted in the interface processing slot.
[0050]
A second effect of the present invention is that when all of the high-precision clock sources mounted in the device fail, data communication between Ethernet (R) -based interfaces using a low-precision clock source is allowed. The purpose is to effectively conduct data signals by circuit switching.
[0051]
The reason is that the SDH interface processing slot is equipped with a high-precision clock source that complies with the SDH standard, and the Ethernet (R) interface processing slot is equipped with a low-precision, low-cost clock source that does not meet this standard. Then, prioritize the selection of the clock source and select the high-precision clock source preferentially.If all the high-precision clock sources fail, control is performed to select the low-precision clock source. Because he did.
[Brief description of the drawings]
FIG. 1 is a block diagram of one embodiment of the present invention.
FIG. 2 is a diagram illustrating details of a phase matching circuit in FIG. 1;
FIG. 3 is a diagram illustrating an embodiment of the present invention in a system equipped with interfaces of SDH system and Ethernet (R) system having different clock accuracies.
FIG. 4 is a diagram illustrating an embodiment of the present invention in a system equipped with an SDH-only interface.
FIG. 5 is a diagram illustrating an embodiment of the present invention in a system equipped with only an Ethernet (R) interface.
FIG. 6 is a block diagram of another embodiment of the present invention.
FIG. 7 is a diagram for explaining a conventional technique.
[Explanation of symbols]
1 to n interface
7 Device control unit
8 Clock source selection control circuit
13 Priority setting circuit
14 Working spare information setting circuit
21 Match judgment circuit
22 Phase adjustment control circuit
23 Phase matching circuit
1-1 to n-1 clock source
1-2 divider circuit
1-3 to n-3 phase matching circuit
1-4 to n-4, 1-6 to n-6 clock source selection circuits
1-5 to n-5 clock disconnection detection circuit
1-7 to n-7 frame pulse disconnection detection circuit
1-9 to n-9 PLL circuit
1-10 to n-10 frequency divider circuit
1-1-1 to n-11 interface processing circuit
1-12 to n-12 Distributed Cross Connect Processing Circuit

Claims (7)

A clock supply system in a communication device having a plurality of communication data processing units,
In each of the plurality of communication data processing units,
A clock source, a distributing means for distributing a clock and a frame pulse obtained from the output of the clock source to another communication data processing unit, and a clock and a frame pulse used in the own communication data processing unit in response to an external selection signal. Selecting means for selecting a frame pulse selected by the selecting means, and a phase matching means for performing phase matching of the frame pulse obtained by the own clock source and outputting the frame pulse to the distributing means,
Common to the plurality of communication data processing units,
A clock supply system comprising selection control means for generating the external selection signal according to a predetermined priority. 2. The clock supply system according to claim 1, wherein each of the plurality of communication data processing units further includes a unit that removes jitter of a clock selected by the selection unit. Each of the plurality of communication data processing units, further provided with the clock and frame pulse disconnection detection means,
The clock supply system according to claim 1, wherein the selection control unit generates the external selection control signal according to a detection output of the disconnection detection unit. 4. The clock supply system according to claim 1, wherein the selection control unit generates the external selection control signal according to active spare information of the plurality of data communication processing units. 5. The plurality of communication data processing units are grouped into heterogeneous data processing units that process heterogeneous communication data, and the priority is determined by setting a clock source in a communication data processing unit of a group that requires higher speed. The clock supply system according to claim 1, wherein the clock supply system has a high priority. A communication data processing device constituting a communication system,
A clock source,
Distributing means for distributing a clock and a frame pulse obtained by the output of the clock source to another communication data processing unit;
Selecting means for selecting a clock and a frame pulse to be used in the own communication data processing unit according to an external selection signal;
Communication data provided with phase adjustment of a frame pulse obtained by the clock source with respect to the frame pulse selected by the selection means and outputting the frame pulse to the distribution means. Processing equipment. 7. The communication data processing apparatus according to claim 6, further comprising: means for removing jitter of a clock selected by said selecting means.

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