KR0164110B1 - Apparatus for distributing system clock - Google Patents

Abstract

The present invention relates to a system clock distribution apparatus, comprising: clock receiving means (11) for receiving and outputting two pairs of system clocks and system timings; Fault monitoring and clock automatic selection means (12) for receiving a pair of system clocks and system timings and a system clock selection signal and detecting a failure of the received signal and outputting a selection signal for selecting a clock in which no failure occurs; First multiplexing means (13) which receives two pairs of system clocks and system timings from the clock receiving means (11) and selects and outputs them by a selection signal of the fault monitoring and automatic clock selection means (12); First dividing means (14) which receives the output of the first multiplexing means (13) and divides it with the same clock duty as the input clock; Internal oscillator means 15 for supplying an internal clock; Second dividing means (16) for receiving an internal clock of the internal oscillator means (15), dividing the same, and outputting it; An output of the first multiplexing means 13 and outputs of the first and second distributing means 14 and 16 to be selected and output by the fault monitoring and selection signals of the automatic clock selection means 12; Two multiplexing means 17; And clock driver means (18) for receiving the output of the second multiplexing means (17) to generate and output a system distribution clock and system distribution timing to an STM-N signal processor, a low speed switch unit, and a low speed signal multiplexer. It receives two pairs of system clocks and system timings input from the circuit distribution system (BDCS), and monitors their faults to provide stable 77.760 MHz system distribution clock and 8KHz / 2KHz system distribution timing. There is an effect that can be supplied to the processing unit, the low speed switch unit, and the low speed signal multiple unit.

Description

System clock distribution unit

1 is a block diagram of an embodiment of a system clock distribution apparatus according to the present invention.

2 is an output signal waveform diagram according to the present invention.

3 is a temporary configuration diagram of a failure device and a clock automatic selection unit according to the present invention.

4 is a logic table of a failure device and a clock automatic selection unit according to the present invention.

* Explanation of symbols for the main parts of the drawings

11: clock receiving unit 12: fault and clock automatic selection unit

13: first multiplexer 14: first divider

15: internal oscillator 16: second divider

17: second multiplexer 18: clock driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system clock distribution device, and more particularly, to an STM using a system clock (77.760 MHz) and a system timing (8 KHz) provided by a system clock generator of a broadband circuit board system (BDCS). A system clock distribution device for generating and outputting a system distribution clock of 77.760 MHz used in a -N signal processor, a low speed switch unit, and a low speed signal multiplexer and an 8 KHz / 2 KHz system distribution timing as a reference for a frame start position.

It accepts synchronous transfer mode level N (STM-N) signals from synchronous transmission (SDH: Synchronous Digital Hierarchy) technology and performs circuit switching in AU / TU (Administration Unit / Tributary Unit) signal units. In addition, broadband circuit distribution system (BDCS) with STM-N signal transmission function can easily configure the national transmission network by mutual distribution / branch combining function. Not only does it provide fast transmission link recovery, it can also perform trial access on any signal.

In order to realize the functions of the broadband circuit distribution system, a synchronized system distribution clock and system distribution timing used in the STM-N signal processing unit, the low speed switch unit, and the low speed signal multiplexer should be provided. To do this, monitor the failure of two stacked system clocks and system timings sent by the system clock generator to select a non-failed clock, or select an internal oscillator for backup in case of any system clock and system timing failures. Must be created.

Accordingly, the present invention receives two pairs of system clocks and system timings, and inputs the system distribution clocks of 77.760 MHz and the system distribution timings of 8KHz / 2KHz through the fault monitoring of the STM-N signals of the broadband circuit distribution system. It is an object of the present invention to provide a system clock distribution device for supplying a processor, a low speed switch unit, and a low speed signal multiple unit.

The present invention for achieving the above object is a clock receiving means for receiving and outputting two pairs of system clock and system timing; Fault monitoring and clock automatic selection means for receiving a pair of system clocks and system timings and a system clock selection signal and detecting a failure of the received signal and outputting a selection signal for selecting a clock in which no failure occurs; First multiplexing means for receiving two pairs of system clocks and system timings from a clock receiving means and selecting and outputting the signals by selecting signals of the fault monitoring and automatic clock selection means; First dividing means for receiving the output of the first multiplexing means and dividing the same into four clocks having the same clock duty as the input clock; Internal oscillator means for supplying an internal clock; Second dividing means for receiving and dividing and outputting an internal clock of the internal oscillator means; Second multiplexing means for receiving the output of the first multiplexing means and the outputs of the first and second frequency dividing means and selecting and outputting the selected signals by means of a selection signal of the fault monitoring and clock automatic selection means; And a clock driver means for receiving the output of the second multiplexing means and generating and outputting a system distribution clock and a system distribution timing to an STM-N signal processor, a low speed switch unit, and a low speed signal multiplexer.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an embodiment of a system clock distribution apparatus according to the present invention, in which 11 is a clock receiver, 12 is a fault monitoring and clock automatic selection unit, 13 is a first multiplexer, and 14 is a first divider. 15 denotes an internal oscillator, 16: second divider, 17: second multiplexer, and 18: clock driver.

Here, the first multiplexer 13 receives two system clocks from the clock receiver 11 and selects and outputs two system clocks by selecting signals from the fault monitoring and automatic clock selector 12. ) And a second 2: 1 MUX 132 that receives two system timings from the clock receiver 11 and selects and outputs the signals by the fault detection and the clock automatic selection unit 12.

In addition, the second multiplexer 17 receives the system clock of the multiplexer 13 and the system clock of the second divider 16 and selects the selected signal from the fault monitoring and automatic clock selector 12. The fault detection and clock automatic selection unit 12 by receiving the first 2: 1 MUX 171 and the system timing of the first multiplexer 13 and the system timing of the second divider 16. The fault monitoring and clock selection are automatically performed by receiving the second 2: 1 MUX 172 and the system timing of the first divider 14 and the system timing of the second divider 16 which are selected and output by the selection signal. A third 2: 1 MUX 173 selects and outputs the signal by the selection signal of the unit 12.

Referring to Figure 2, the operation of the present invention, the clock receiver 11 is the system clock 1 (77.760MH) input from an external system clock generator using the MC10H101 chip

z), the system timing 1 (8KHz), the system clock 2 (77.760MHz) and the system timing 2 (8KHz) are received to remove noise, and amplify and output the signal.

The failure monitoring and clock automatic selection unit 12 receives the system clock 1, the system timing 1, the system clock 2, and the system timing 2 to detect a failure of each clock, and also selects a system clock input from an external system clock generator. Selection for outputting a selection signal 1 for selecting a normal clock using the signal to the first multiplexer 13, and for selecting an internal clock of the second divider 16 when a clock signal received from the outside fails. The signal 2 is output to the second multiplexer 17.

The first multiplexer 13 selects the two received system clocks and system timings according to the selection signal 1 provided to the fault monitoring and clock automatic selection unit 12 so that the system timing is equal to the second multiplexer 17 and The clock is output to the first divider 143 and the system clock is output to the second multiplexer 17.

If the selection signal is '0', the system clock 1 and the system timing 1 are selected. If the selection signal is '1', the system clock 2 and the system timing 2 are selected. The first multiplexer 13 is implemented using the MC10H158 chip.

The first divider 14 divides the system timing 8KHz output from the first multiplexer 13 into 4 parts to generate the 2KHz timing required for the low speed switch unit and the low speed signal multiplexer. Output Here, the output of the first divider 14 has a phase and duty equal to 8 KHz.

The internal oscillator 15 generates an internal clock of 155.52 MHz and outputs it to the second divider 16 in case all system clocks and timings provided by the system clock generator are in an error state. The internal oscillator 15 uses SNP3031A, which is a temperature compensation oscillator from NDK of Japan.

The second divider 16 generates 77.760 MHz, 8 KHz, and 2 KHz by sequentially dividing the internal clock 2, 9720, and 4 by the internal oscillator 15, and outputs the 77.760 MHz, 8 KHz, and 2 KHz to the second multiplexer 17.

The second multiplexer 17 receives the system clock and system timing inputted from the first multiplexer 13 and the divided internal clock inputted from the second divider 16 to select the fault monitoring and clock automatically. The signal is selected by the selection signal 2 of the unit 12 and output to the clock driver 18.

If the selection signal 2 is '0', the clock input from the first multiplexer 13 is selected. If the selection signal 2 is '1', the divided internal clock input from the second divider 16 is selected. The second multiplexer 17 is implemented using a general MC10H158.

The clock driver 18 receives a system clock of 77.760 MHz and a system timing of 8KHz / 2KHz output from the second multiplexer 17, and as shown in FIG. And outputs the system distribution timing 2 to the STM-N signal processing section, the low speed switch section, and the low speed signal multiplexing section. The clock driver 18 used here is implemented using Motorola's MC10E111, a low skew clock driver.

3 is a temporary configuration diagram of the failure device and the clock automatic selection unit 12 according to the present invention. The failure device and the clock automatic selection unit 12 receive two system clocks and two system timings. A clock supervisor circuit 21 for monitoring a clock and outputting a clock fault signal, a negative logic sum gate 22 for receiving a clock fault signal from the clock supervisor circuit 21 and performing a negative OR to output a selection signal 2 and the clock supervisor And a clock automatic selection circuit 23 for outputting a clock failure signal of the circuit 21 and an external system clock signal 1.

Referring to the operation of the failure device and the clock automatic selection unit 12 configured as described above, the clock monitoring circuit 21 monitors the system clock 1 / system timing 1 and the system clock 2 / system timing 2 input from the system clock generator, respectively. The clock failure signal 1 and the clock failure signal 2 are output to the negative AND gate 22 and the clock automatic circuit 23. In this case, if the clock failure signal is '0', the system clock / system timing indicates a failure state. The clock monitoring circuit 21 is composed of a 74LS123 and a logic gate.

The negative OR gate 22 outputs the selection signal 2 using the clock failure signal 1 and the clock failure signal 2 output from the clock monitoring circuit 21 and outputs the selection signal 2 to the second multiplexer 17. Here, when the fault signals are all '0', the selection signal 2 is output as '1'.

The clock automatic selection circuit 23 receives a clock failure signal of the clock monitoring circuit 21 and a system clock selection signal from a system clock generator and outputs a selection signal 1 for selecting a clock in a steady state. Normally, clock selection is selected by the system clock selection signal ('0': system clock 1 selection, '1': system clock 2 selection), but if a failure (cable failure, etc.) occurs during transmission, Because it can be selected, it is selected after checking the clock status by detecting the clock failure. The selection method is selected by a system clock selection signal if there is no clock failure, and if a clock indicated by the system clock signal is in a failure state, another clock that is normal can be selected. The clock automatic selection circuit 23 is composed of logic gates based on the logic table shown in FIG.

The present invention configured and operated as described above has two system clocks and system timing inputs applied to a broadband circuit distribution system (BDCS) to receive a stable 77.760 MHz system distribution clock and 8KHz / 2KHz through their fault monitoring. The system distribution timing can be supplied to the STM-N signal processing unit, the low speed switch unit, and the low speed signal multiple unit of the wideband circuit distribution system.

Claims (4)

Clock receiving means (11) for receiving and outputting two pairs of system clocks and system timings; Fault monitoring and clock automatic selection means (12) for receiving a pair of system clocks and system timings and a system clock selection signal and detecting a failure of the received signal and outputting a selection signal for selecting a clock in which no failure occurs; First multiplexing means (13) which receives two pairs of system clocks and system timings from the clock receiving means (11) and selects and outputs them by a selection signal of the fault monitoring and automatic clock selection means (12); First dividing means (14) for receiving an output of the first multiplexing means (13) and dividing the same into four clocks having the same clock duty as the input clock; Internal oscillator means 15 for supplying an internal clock; Second dividing means (16) for receiving an internal clock of the internal oscillator means (15), dividing the same, and outputting it; An output of the first multiplexing means 13 and outputs of the first and second distributing means 14 and 16, which are selected and output by the fault monitoring and selection signals of the automatic clock selection means 12; Two multiplexing means 17; And a clock driver means 18 which receives the output of the second multiplexing means 17 and generates and outputs a system distribution clock and system distribution timing to an STM-N signal processor, a low speed switch unit, and a low speed signal multiplexer. System clock distribution device. The method of claim 1, wherein the first multiplexing means (13) receives two system clocks from the clock receiving means (11) and selects them by a selection signal of the fault monitoring and automatic clock selection means (12). Outputting a first 2: 1 MUX 131; And a second 2: 1 MUX 132 which receives two system timings from the clock receiving means 11 and selects and outputs them by a selection signal of the fault monitoring and automatic clock selection means 12. System clock distribution device. 2. The system of claim 1, wherein the second multiplexing means (17) receives the system clock of the first multiplexing means (13) and the system clock of the second frequency dividing means (16). A first 2: 1 MUX 171 that selects and outputs the selected signal at (12); A second 2: receiving the system timing of the first multiplexing means 13 and the system timing of the second frequency dividing means 16 and selecting and outputting the signal by the fault monitoring and selection signal of the automatic clock selection means 12; 1 MUX 172; And a third 2 that receives the system timing of the first distributing means 14 and the system timing of the second distributing means 16 and selects and outputs the signals by the fault detection and automatic selection means of the clock selection means 12. A system clock distribution device comprising: 1 MUX 173. The clock monitoring means (21) according to claim 1, wherein the fault monitoring and clock automatic selection means (12) receives two system clocks and two system timings and monitors the input clocks and outputs a clock failure signal. ; Negative logic gate means (22) for receiving a clock failure signal of the clock monitoring means (21) and performing a negative logic sum to output a selection signal (2); And a clock automatic selection means 23 for receiving a clock failure signal of the clock monitoring means 21 and an external system clock selection signal and outputting a selection signal 1 for selecting a normal clock. Device.