KR970056146A - System clock distribution unit - Google Patents

Abstract

The present invention relates to a system clock distribution apparatus, comprising: clock receiving means (11) for receiving and outputting two pairs of system clocks and system timings; Fault monitoring and clock automatic selection means (12) for receiving a pair of system clocks and system timings and a system clock selection signal and detecting a failure of the received signal and outputting a selection signal for selecting a clock in which no failure occurs; First multiplexing means (13) which receives two pairs of system clocks and system timings from the clock receiving means (11) and selects and outputs them by a selection signal of the fault monitoring and automatic clock selection means (12); First dividing means (14) which receives the output of the first multiplexing means (13) and divides it with the same clock duty as the input clock; Internal oscillator means 15 for supplying an internal clock; Second dividing means (16) for receiving an internal clock of the internal oscillator means (15), dividing the same, and outputting it; An output of the first multiplexing means 13 and outputs of the first and second distributing means 14 and 16 to be selected and output by the fault monitoring and selection signals of the automatic clock selection means 12; Two multiplexing means 17; And clock driver means (18) for receiving the output of the second multiplexing means (17) to generate and output a system distribution clock and system distribution timing to an STM-N signal processor, a low speed switch unit, and a low speed signal multiplexer. It receives two pairs of system clocks and system timings input from the circuit distribution system (BDCS), and monitors their faults to provide stable 77.760 MHz system distribution clock and 8KHz / 2KHz system distribution timing. There is an effect that can be supplied to the processing unit, the low speed switch unit, and the low speed signal multiple unit.

Description

System clock distribution unit

Since this is an open matter, no full text was included.

1 is a block diagram of an embodiment of a system clock distribution apparatus according to the present invention.

2 is an output signal waveform diagram according to the present invention.

Claims (4)

Clock receiving means (11) for receiving and outputting two pairs of system clocks and system timings; Fault monitoring and clock automatic selection means (12) for receiving a pair of system clocks and system timings and a system clock selection signal and detecting a failure of the received signal and outputting a selection signal for selecting a clock in which no failure occurs; First multiplexing means (13) which receives two pairs of system clocks and system timings from the clock receiving means (11) and selects and outputs them by a selection signal of the fault monitoring and automatic clock selection means (12); First dividing means (14) for receiving an output of the first multiplexing means (13) and dividing the same into four clocks having the same clock duty as the input clock; Internal oscillator means 15 for supplying an internal clock; Second dividing means (16) for receiving an internal clock of the internal oscillator means (15), dividing the same, and outputting it; An output of the first multiplexing means 13 and outputs of the first and second distributing means 14 and 16, which are selected and output by the fault monitoring and selection signals of the automatic clock selection means 12; Two multiplexing means 17; And a clock driver means 18 which receives the output of the second multiplexing means 17 and generates and outputs a system distribution clock and system distribution timing to an STM-N signal processor, a low speed switch unit, and a low speed signal multiplexer. System clock distribution device. The method of claim 1, wherein the first multiplexing means (13) receives two system clocks from the clock receiving means (11) and selects them by a selection signal of the fault monitoring and automatic clock selection means (12). Outputting a first 2: 1 MUX 131; And a second 2: 1 MUX 132 which receives two system timings from the clock receiving means 11 and selects and outputs them by a selection signal of the fault monitoring and automatic clock selection means 12. System clock distribution device. 2. The system of claim 1, wherein the second multiplexing means (17) receives the system clock of the first multiplexing means (13) and the system clock of the second frequency dividing means (16). A first 2: 1 MUX 171 that selects and outputs the selected signal at (12); A second 2: receiving the system timing of the first multiplexing means 13 and the system timing of the second frequency dividing means 16 and selecting and outputting the signal by the fault monitoring and selection signal of the automatic clock selection means 12; 1 MUX 172; And a third 2 that receives the system timing of the first distributing means 14 and the system timing of the second distributing means 16 and selects and outputs the signals by the fault detection and automatic selection means of the clock selection means 12. A system clock distribution device comprising: 1 MUX 173. The clock monitoring means (21) according to claim 1, wherein the fault monitoring and clock automatic selection means (12) receives two system clocks and two system timings and monitors the input clocks and outputs a clock failure signal. ; Negative logic gate means (22) for receiving a clock failure signal of the clock monitoring means (21) and performing a negative logic sum to output a selection signal (2); And a clock automatic selection means 23 for receiving a clock failure signal of the clock monitoring means 21 and an external system clock selection signal and outputting a selection signal 1 for selecting a normal clock. Device. ※ Note: The disclosure is based on the initial application.