JP2626487B2 - Transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to SONET (Synch).
(ronous Optical Network) or S
DH (Synchronous Digital Hi)
The present invention relates to a device used in a synchronous network such as an erarchy network, and more particularly to inputting a plurality of time-division multiplexed transmission paths, performing signal selection between time-division multiplexed signals on the input transmission path, and The present invention relates to a transmission device that outputs to a transmission path.

[0002]

2. Description of the Related Art Conventionally, in a device that performs time division switching of a time division multiplexed signal in a SONET / SDH network, an OH (Overhead) signal added to a signal on an input transmission line is terminated, and all signals are replaced by pointer replacement. The signal from the input transmission line is subjected to timing conversion to the common internal clock, and the time division switch is performed in a state where all the signals are synchronized with the common timing, and the time division switched signal is output to the output transmission line. A signal to be transmitted is selected, and an OH signal is added and transmitted.

As shown in FIG. 4, a conventional transmission device used for a SONET network receives an input signal from an input transmission line # 1 and terminates an OH, and an OH termination unit 71 for transmitting a signal terminated with the OH to the transmission line. A pointer processing unit 81 that converts a timing into a timing in the apparatus, an OH terminating unit 72 that receives a signal from the input transmission line # 2 and terminates an OH, A pointer processing unit 82 for converting the timing into a timing, a frame synchronization signal generating unit 91 for supplying internal timing to the pointer processing units 81 and 82, and time-division switches 101 and 103 for time-divisionally switching signals from the pointer processing unit 81.
Time-division switches 102 and 104 for time-divisionally switching signals from the pointer processing unit 82; a selector 111 for selecting a signal to be transmitted to the output transmission line # 1 from the signals of the time-division switches 101 and 102; 10
A selector 112 for selecting a signal to be transmitted to the output transmission line # 2 from the signals of the signal lines 3 and 104;
Selector selector 92 for instructing signal 2 to be selected;
OH is inserted into the signal from the selector 111 and the output transmission line #
1 and an OH insertion unit 122 that inserts OH into the signal from the selector 112 and sends it out to the output transmission line # 2.

Next, the operation will be described. In the conventional apparatus shown in FIG. 4, the signal of the input transmission line # 1 time-division multiplexed according to the SONET format and the signal of the input transmission line # 2 similarly time-division multiplexed are used as the output transmission line # 1. A signal to be transmitted to the output transmission line # 2 is selected and transmitted to the output transmission line # 1 or the output transmission line # 2. For example, when transmitting to the output transmission line # 1, if the time slot of the desired signal on the input transmission line # 1 matches the time slot of the desired signal on the input transmission line # 2, the time division switch 101 Is used to exchange the time slots of the signal from the input transmission line # 1 to eliminate the coincidence of the time slots.

Since the time-division switches 101 to 104 perform the time-division switch operation by writing and reading data to and from the memory, there is a characteristic that a certain delay time is added to a signal passing through the time-division switch. . The selector, for selecting the signals to the appropriate frame phase of the output signal, it is necessary to frame phase between your Keru signal to the selector input match. For this purpose,
In the conventional example, all signals are passed through a time-division switch to match the frame phases of the signals.

[0006]

In this conventional transmission device, a time-division switch is used for signals from all input transmission lines in order to match the phases at the selector inputs. Therefore, the ratio of the time-division switch to the components constituting the transmission device is large, and the conventional configuration that requires many time-division switches has a problem that the device scale becomes large. Further, since a delay time for passing through the time-division switch is added to all transmission paths, there is a problem that the delay time in the case of multiple connections is increased. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to reduce the size of a device to about half that of a conventional device and obtain a transmission device having a path without delay time by a time division switch.

[0007]

The transmission device of the present invention comprises:
One or more transmission line termination units, one or more transmission line transmission units,
A frame synchronization signal generator for generating a frame synchronization signal in the apparatus, a delay circuit for delaying the frame synchronization signal from the frame synchronization signal generator for a predetermined time, and an output signal of the transmission path terminator to a frame phase in the apparatus. A pointer processing unit to be converted, a time division switch for exchanging a time slot of an output signal of the pointer processing unit, and a signal to be transmitted to a transmission path transmission unit from a signal from the pointer processing unit and a signal from the time division switch are selected. A selector that supplies a frame synchronization signal from the frame synchronization signal generation unit to at least one pointer processing unit, and supplies a frame synchronization signal that has passed through the delay circuit to the other pointer processing units. the output signal of the pointer processing unit that operates by a signal from the frame synchronization signal generation unit passes the time-division switch, upper The output signal of the pointer processing unit that operates in a frame synchronization signal which has passed through the delay circuit is obtained by so as not to pass through the time division switch. Also, the first
And the second transmission path terminating sections (11, 12),
A second transmission path sending section (61, 62), and a frame in the apparatus.
Frame synchronization signal generating section (31) for generating a system synchronization signal
And the frame synchronization signal from the frame synchronization signal generation unit.
A delay circuit (32) for delaying a fixed time, a first transmission path end
The output signal at the end is synchronized with the frame passing through this delay circuit.
A first point for converting to a frame phase in the device by a signal
Data processing unit (21) and the output signal of the second transmission line termination unit.
By the frame synchronization signal from the frame synchronization signal generator
Second pointer processing unit for converting to an internal frame phase
(22) and the output signal of the second pointer processing unit.
The first and the second to replace the time slot
A second time division switch (41, 42) and a first point
Signal from the data processing unit and the signal from the first time division switch.
A signal for selecting a signal to be sent to the first transmission path sending unit from the signal
1 selector (51) and a signal from the first pointer processing unit.
A second transfer from the signal and the signal from the second time-division switch.
A second selector (5) for selecting a signal to be sent to the transmission path sending unit
2). In addition, the first, second and
3 transmission line terminators (11, 12, 13) and the first and second
And a third transmission path transmission section (61, 62, 63).
A frame synchronization signal generator that generates a frame synchronization signal in the unit
(31) and a frame from the frame synchronization signal generation unit.
A delay circuit (32) for delaying the system synchronization signal by a predetermined time;
The output signal of the transmission line terminal section 1 has passed through this delay circuit.
Convert to frame phase in device by frame synchronization signal
A first pointer processing unit (21) and a second transmission line termination unit
Output signal from the frame synchronization signal passed through the delay circuit.
Pointer processing unit for converting to a frame phase in the apparatus
(22) and the output signal of the third transmission path termination unit is
A frame synchronization signal from the synchronization signal generation unit
A third pointer processing unit (23) for converting to a frame phase
And the output signal of the third pointer processing unit, respectively.
And the first and second
Time division switches (41, 42) and first pointer processing
Inputs the output signal of the unit and swaps its time slot
A third time-division switch (43);
Input the output signal of the
A fourth time-division switch (44) and a first pointer
The signal from the processing unit and the signal from the first time division switch
A first cell for selecting a signal to be transmitted from the
And a signal from the second pointer processing unit.
From the signal from the second time division switch,
A second selector (52) for selecting a signal to be sent to the output unit;
The signal from the third time division switch and the fourth time division switch
And the signal to be sent to the third transmission path sending unit from the signal from the
And a third selector (53).

[0008]

According to the present invention, the pointer processing unit for processing the signal passing through the time division switch receives the frame synchronization signal from the frame synchronization signal generation unit and processes the signal not passing through the time division switch. Receives the frame synchronization signal from the delay circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a transmission device according to the present invention. The transmission device shown in FIG. 1 includes an OH termination unit (transmission line termination unit) 11 that receives a signal from an input transmission line and terminates OH, a transmission line transmission unit (OH insertion unit 61),
A frame synchronization signal generator 31 for generating a frame synchronization signal in the apparatus, a delay circuit 32 for delaying the frame synchronization signal from the frame synchronization signal generator 31 for a predetermined time,
Pointer processing units 21 and 22 for converting output signals of the transmission path terminating unit 11 into internal frame phases, a time division switch 41 for exchanging time slots of output signals of the pointer processing unit 22, and a pointer processing unit 21. A selector 51 for selecting a signal to be sent to the transmission path sending unit from the signal and the signal from the time division switch 41, supplying a frame synchronization signal from the frame synchronization signal generation unit 31 to at least one pointer processing unit; The frame synchronization signal that has passed through the delay circuit 32 is supplied to the pointer processing unit, and the output signal of the pointer processing unit that operates based on the signal from the frame synchronization signal generation unit 31 passes through the time division switch and passes through the delay circuit 32. The output signal of the pointer processing unit operating with the frame synchronization signal is configured not to pass through the time division switch. .

Reference numeral 33 denotes a selector control unit for instructing the selector 51 to select a signal to be selected. Reference numeral 61 denotes an OH insertion unit for inserting an OH into the signal from the selector 51 and transmitting the OH to an output transmission line. It constitutes a sending section. Here, the pointer processing units 21 and 22 have a function of converting the OH-terminated signal from the transmission line timing to the device timing, and the frame synchronization signal generation unit 31 supplies the in-device timing to the pointer processing unit 22. The delay circuit 32 has a function of delaying the frame signal from the frame synchronization signal generation unit 31 and supplying the frame signal to the pointer processing unit 21. The time-division switch 41 has a function of time-divisionally switching a signal from the pointer processing unit 22, and the selector 51 has a function of selecting a signal from the pointer processing unit 21 and a signal from the time-division switch 41. I have.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, some of the signals time-division multiplexed on the input transmission line are subjected to time division switching, and the other signals are transmitted to the output transmission line without performing time division switching. And O
The output of the H terminator 11 is branched into two, and the pointer processors 21 and 22 convert the timing into an in-device frame synchronization signal. In the pointer processing unit 21, the delay circuit 32 performs timing conversion to a frame synchronization signal to which a delay time equal to the delay time of the time division switch 41 is given. The output signal of the pointer processing unit 22 is a time division switch 4
1 and the desired time-division switch operation is performed.

Next, the input signal of the selector 51 is divided into a signal synchronized with the timing given the same delay time as the time division switch 41 by the delay circuit 32 and the time division switch 4.
1 is a signal to which a delay time has been added, so that its frame phases are equal. Therefore, the selector 51 can select a desired signal at an appropriate signal phase of the output signal. According to the configuration described above, a signal that requires time slot replacement must pass through the time division switch, and a signal that does not require time slot replacement must be transmitted through a path without delay time added by the time division switch. Can be.

FIG. 2 is a block diagram showing another embodiment of the present invention. The transmission device shown in FIG.
An OH termination unit 11 that receives a signal from the
Pointer processing unit 21 for converting a signal terminated with OH from transmission line timing to device timing, and OH termination unit 12 for receiving a signal from input transmission line # 2 and terminating OH
A pointer processing unit 22 for converting a signal terminated with an OH from a transmission line timing to a device timing; a frame synchronization signal generation unit 31 for supplying internal device timing to the pointer processing unit 22; 31
The frame processing from the pointer processing unit 21
, And time-division switches 41 and 4 for time-divisionally switching signals from the pointer processing unit 22
2, a selector 51 for selecting a signal from the pointer processing unit 21 and a signal from the time division switch 41, a selector 52 for selecting a signal from the pointer processing unit 21 and a signal from the time division switch 42, and a selector 51 And 52
A OH insertion unit 61 that inserts OH into the signal from the selector 51 and sends it to the output transmission line # 1, and inserts an OH into the signal from the selector 52 and outputs the signal. OH insertion unit 62 to be sent to path # 2
Consists of

Next, the operation of the embodiment shown in FIG. 2 will be described. First, the signal from the input transmission line # 1 and the input transmission line #
When a desired signal is selected from the signals from the second transmission line and transmitted to the output transmission line # 1, the time slot of the desired signal on the input transmission line # 1 and the time of the desired signal on the input transmission line # 2 When the slots match, the time slot of the signal from the input transmission line # 2 is exchanged using the time division switch 41. At the same time, when a desired signal is selected from the signal from the input transmission line # 1 and the signal from the input transmission line # 2 and transmitted to the output transmission line # 2, the desired signal of the input transmission line # 1 is When the time slot matches the time slot of the desired signal on the input transmission line # 2, the time slot of the signal from the input transmission line # 2 is exchanged using the time division switch. Since the signal from the input transmission line # 1 is input to the selectors 51 and 52 without passing through the time division switch, the time division switches 41 and 42 from the input transmission line # 2 are input.
When the timing is converted by the pointer processing unit 21 in order to match the phase with the signal that has passed through, the delay circuit 32 adjusts the timing to a timing in which a delay equal to the delay time of the time-division switch is given in advance.

Next, the selector 51 is connected to the selector controller 3.
According to the control from 3, the desired signal is selected from the signal from the pointer processing unit 21 and the signal from the time division switch 41 whose frame phases match. The selected signal is added to the transmission OH by the OH insertion unit 61 and transmitted to the output transmission line # 1. The selector 52 selects a desired signal from the signal from the pointer processing unit 21 and the signal from the time-division switch 42 having the same frame phase according to the control from the selector control unit 33. The selected signal is O
The transmission OH is added by the H insertion unit 62 and transmitted to the output transmission line # 2. The input signals to the selectors 51 and 52 are a signal synchronized with the timing given the same delay time as the time division switch by the delay circuit 32 and a signal to which the delay time is added in the time division switch. equal. Therefore, the selectors 51 and 52 can select a signal to an appropriate signal phase of the output signal. If the time slot of the desired signal on the input transmission line # 1 matches the time slot of the desired signal on the input transmission line # 2, the time division switches 41 and 4
2, the time slot of the signal from the input transmission line # 2 is exchanged, so that a different time slot can be selected. With the above-described configuration, the signals to be transmitted to the output transmission lines # 1 and # 2 can select signals in arbitrary time slots of the input transmission lines # 1 and # 2.

FIG. 3 is a block diagram showing still another embodiment of the present invention. The transmission device shown in FIG. 3 receives a signal from an input transmission line # 1, and an OH termination unit 11 for terminating OH and a pointer processing unit for converting a signal terminated with OH from transmission line timing to device timing. 21; an OH terminator 12 that receives a signal from the input transmission line # 2 and terminates OH; and a pointer processing unit 22 that converts a signal terminated with OH from transmission line timing to device timing.
The signal from the input transmission line # 3 is input, and O
H termination unit 13 and pointer processing unit 23 for converting a signal terminated with OH from the timing of the transmission line to the timing of the device
A frame synchronization signal generating unit 31 for supplying the timing in the apparatus to the pointer processing unit 23; a delay circuit 32 for delaying the frame signal from the frame synchronization signal generating unit 31 and supplying the frame signal to the pointer processing units 21 and 22; A time-division switch 43 for time-divisionally switching the signal from the pointer processing unit 21, a time-division switch 44 for time-divisionally switching the signal from the pointer processing unit 22, and a time-division switch for the signal from the pointer processing unit 23. Split switch 4
1 and 42, a selector 51 for selecting a signal from the pointer processing unit 21 and a signal from the time division switch 41,
A selector 52 for selecting a signal from the pointer processing unit 22 and a signal from the time division switch 42;
3, a selector 53 for selecting a signal from the time division switch 44, a selector control unit 33 for instructing the selectors 51, 52, and 53 to select a signal to be selected, and a selector 5
An OH insertion unit 61 that inserts OH into the signal from No. 1 and sends it to the output transmission line # 2, an OH insertion unit 62 that inserts OH into the signal from the selector 52 and sends it to the output transmission line # 1, and a selector 53 And an OH insertion unit 63 that inserts OH into the output signal and sends it out to the output transmission line # 3.

Next, the operation of the embodiment shown in FIG. 3 will be described. First, the input / output transmission line # 1 and the input / output transmission line # 2 are used as main transmission lines, a desired signal is extracted from the main transmission line to the output transmission line # 3, and the signal from the input transmission line # 3 is used as the main transmission line. As an add / drop device to be inserted into a desired time slot. Then, the signal from the input transmission line # 1 is timing-converted in the pointer processing unit 21 by the delay circuit 32 so as to be synchronized with the delayed frame phase. Similarly, the signal from the input transmission line # 2 is timing-converted in the pointer processing unit 22 so as to be synchronized with the frame phase delayed by the delay circuit 32. Further, the signal from the input transmission line # 3 is timing-converted in the pointer processing unit 23 so as to be synchronized with the frame phase given from the frame synchronization signal generation unit 31.

Next, the signal to be transmitted to the output transmission line # 3 is selected by the selector 53 when the signal from the input transmission line # 1 is transmitted, and the signal from the time division switch 43 is selected. When transmitting the signal from the time division switch 44, the signal from the time division switch 44 is selected. The signal to be transmitted to the output transmission line # 2 is selected by the selector 51 when the signal from the input transmission line # 1 is transmitted, and the signal from the pointer processing unit 21 is selected. When selecting, the signal from the time division switch 41 is selected. The signal to be sent to the output transmission line # 1 is
In the case of transmitting the signal from the input transmission line # 2, the signal from the pointer processing unit 22 is selected, and when the signal from the input transmission line # 3 is selected, the time division switch 42 is used.
Select the signal from.

Next, the signal phase at the input of the selector 53 becomes equal because the same delay time is added in the time division switches 43 and 44. Also, input transmission line # 1
When the time slot of the desired signal of the input transmission line # 2 matches the time slot of the desired signal of the input transmission line # 2, the time slot of the signal from the input transmission line # 1 is switched using the time division switch 43, By using the division switch 44 to exchange the time slot of the signal from the input transmission line # 2, a signal can be selected from a different time slot. The input signal of the selector 51 is
Since the signal synchronized with the timing given the same delay time as the time division switch by the delay circuit 32 and the signal added with the delay time in the time division switch, their frame phases are equal. Therefore, the selector 51 can select a signal to an appropriate signal phase of the output signal. If the time slot of the desired signal on the input transmission line # 1 matches the time slot of the desired signal on the input transmission line # 3, the time division switch 41 is used to input the time slot of the input transmission line # 3.
By swapping the time slots of the signals from
Signals can be selected from different time slots.

The input signal of the selector 52 is a signal synchronized with the timing given the same delay time as the time division switch by the delay circuit 32 and a signal to which the delay time is added in the time division switch. Are equal. Therefore, the selector 52 can select a signal to an appropriate signal phase of the output signal. When the time slot of the desired signal on the input transmission line # 2 matches the time slot of the desired signal on the input transmission line # 3, the time division switch 42 is used to transmit the signal from the input transmission line # 3. By exchanging time slots, signals can be selected from different time slots. According to the configuration described above, a signal to be transmitted to the output transmission line # 1 can be selected from signals in arbitrary time slots of the input transmission line # 2 and the input transmission line # 3. Can select a signal in an arbitrary time slot of the input transmission line # 1 and the input transmission line # 3.
Can be selected from signals in any time slot of the input transmission line # 1 and the input transmission line # 2.

[0021]

As described above, the present invention has a frame synchronization signal generator for generating a frame signal in the apparatus and a delay circuit for adding the same delay time as the delay time in the time division switch to the frame synchronization signal. The frame synchronization signal from the frame synchronization signal generation unit is input to the pointer processing unit that processes the signal passing through both time division switches, and the pointer processing unit that processes the signal not passing through the time division switch is input from the delay circuit. Since the frame synchronization signal is input, the size of the time division switch in the transmission device is
Compared to the conventional device, the transmission line is 50% when there are two transmission lines, and about 60% when the transmission line is three lines.
Percent has the effect that can be reduced. In addition, the reduction of the time-division switch scale can greatly reduce the device cost, and can provide an inexpensive device.

In the case of a single transmission path, the delay time of a signal that does not need to pass through the time division switch can be reduced by the delay time when the signal passes through the time division switch. One object of the SONET network or the SDH network is to reduce the delay time in the network as much as possible, and the reduction of the delay time according to the present invention has a great effect on this purpose. Further, even when there are two or more transmission paths, a transmission path that does not pass through the time division switch does not add a delay time due to the time division switch. In particular, even if the transmission devices are connected in multiple stages, the delay time does not increase. Therefore, even when a large-scale network is constructed, it is possible to provide a service with a small delay time, and there is an effect that user convenience is remarkably improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a transmission device according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing still another embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a conventional transmission device.

[Explanation of symbols]

 11 to 13 OH termination unit 21 to 23 pointer processing unit 31 frame synchronization signal generation unit 32 delay circuit 33 selector control unit 41 to 44 time division switch 51 to 53 selector 61 to 63 OH insertion unit

Claims (1)

(57) [Claims] 1. One or more transmission line termination units, one or more transmission line transmission units, a frame synchronization signal generation unit for generating a frame synchronization signal in the device, and a frame from the frame synchronization signal generation unit A delay circuit for delaying a synchronization signal for a predetermined time, a pointer processing unit for converting an output signal of the transmission path termination unit into a frame phase in the apparatus based on a frame synchronization signal, and replacing a time slot of an output signal of the pointer processing unit. A time division switch, and a selector for selecting a signal to be sent to the transmission path transmission unit from a signal from the pointer processing unit and a signal from the time division switch, wherein at least one pointer processing unit has the frame synchronization signal. A frame synchronization signal from the generation unit is supplied, and a frame synchronization signal passed through the delay circuit is supplied to another pointer processing unit. The output signal of the pointer processing unit operated by the signal from the frame synchronization signal generation unit is passed through the time division switch, and the output signal of the pointer processing unit operated by the frame synchronization signal passed through the delay circuit is not passed through the time division switch. A transmission device characterized in that: