JP2543138B2 - Network synchronization device and network synchronization method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network synchronizer used for a digital communication network or the like.

2. Description of the Related Art FIG. 6 is a diagram showing a configuration of a conventional network synchronizer. In FIG. 6, reference numeral 1 is a clock supply device, and its output clock 2 is input to a phase lock loop (hereinafter referred to as PLL) 3 of the network synchronizer 9. The output of the PLL3 is input to the clock generation unit 4, and the outputs of the clock generation unit 4 are the clock 5 used in the network and the network synchronization clock 7. The network synchronization clock 7 is input to the PLL8, and from the PLL8. , The clock 6 used in the network is output. The clock 5 and the clock 6 are used as a redundant configuration.

Since each PLL outputs a clock synchronized with the input clock, the redundant clocks 5 and 6 are synchronized with the clock 2 output from the clock supply device 1.

FIG. 7 is a diagram showing a configuration when two conventional network synchronizers are used, in which two clock paths from the clock supply device 1 are used.
This shows a configuration in which a book is used to increase redundancy.

Here, 41 and 42 are network synchronizers, and the clock 2 from the clock supply device is input to the switches 11 and 12, respectively, and the outputs thereof are input to the PLLs 3 and 8. Also switch 11,12
Has an input priority, and (1) has a higher priority than (2). That is, if (1) has a clock input, the switches 11 and 12 are connected to (1),
If there is no clock input in (1), it shall be connected to (2). If both clocks 2 from the clock supply device 1 are normal, both switches 11 and 12 are connected to (1). Now, assuming that the clock 2 on the right side is cut off, the switch 11 is switched to (2) and synchronized with the clock 2 on the left side. As a result, both the clocks 5 and 6 can be synchronized with the clock 2 of the clock supply device 1.

However, in the conventional network synchronizer described above, in the case of the example of FIG. 6, there is only one clock path from the clock supply device, and if this path is disconnected, network synchronization cannot be realized. there were.

Further, in the example of FIG. 7, when the clock supply device 1 does not exist or when two clock paths are both disconnected,
Since the PLLs 3 and 8 operate independently, the clocks 5 and 6 are asynchronous.

The present invention is to solve the drawbacks of the above conventional examples,
An object of the present invention is to provide an excellent network synchronizer capable of outputting two systems of redundant clocks that are synchronized with each other even when the clock supply device is disconnected or when both clock paths are disconnected.

Means for Solving the Problems The present invention, in order to achieve the above object, a clock generator that generates a network synchronization clock by a PLL output, and a means for outputting “disconnection” of the highest priority clock input, Means is provided for inputting the output of the input disconnection of another network synchronizer, and means for changing the switching priority of the switch by the disconnection of the plurality of network synchronization unit highest priority clocks. The synchronizing clock output is input to the clock input terminal of another network synchronizer which is not the highest priority.

Action The present invention has the following actions due to the above-mentioned configuration. That is, even if there is no clock supply device, the output clock of one network synchronization device is synchronized with another network synchronization device, and all clocks can be synchronized.

EXAMPLE FIG. 1 is a diagram showing a schematic configuration of an example of the present invention, FIG.
FIG. 3 is a block diagram showing the main part of FIG. 1 in more detail, and FIG. 3 is a schematic block diagram of another embodiment of the present invention.

In FIG. 1, 41 and 42 are network synchronizers, and 1 is a clock supply device, which outputs a plurality of synchronized clocks 2. 11,1
2 is a switch, which is a priority input terminal (1),
Switch (2) to output. The outputs of switches 11 and 12 are PLL
The clocks 5 and 6 used in the network and the clocks input to the clock generators 21 and 22 are input to the PLLs 3 and 8, respectively, and the outputs of the PLLs 3 and 8 are the clocks to be used in the network. The clock generators 21 and 22 generate network synchronization clocks, and their outputs are input to the low priority input terminals (2) of the switches 12 and 11, respectively.

In FIG. 2, the same numbers as those in FIG. 1 indicate the same contents (the same applies hereinafter), and the explanation thereof is omitted.

In FIG. 2, reference numerals 31 and 32 are detection circuits for detecting that the highest priority clock input is “off”, and the outputs thereof are output to the outside and simultaneously input to the NAND gates 33 and 34. . The other inputs of the NAND gates 33 and 34 are input from the outside. The outputs of NAND gates 33 and 34 are AND
The low-priority clock is input to the other inputs of the AND gates 35 and 36. Further, the outputs of the AND gates 35 and 36 are connected to the terminals (2) of the switches 11 and 12.

As shown in FIG. 2, the outputs of the clock generators 21 and 22 are input to the low-priority clock input terminals of different network synchronizers, and the output of the detection circuit 32 of the network synchronizer 42 changes to the network synchronizer 41. NAND gate 33 is connected to be input.

Next, the operation of the above embodiment will be described. In the above embodiment, since the clock 2 is normally input from the clock supply device 1 to the network synchronizers 41 and 42, the switches 11 and 12 are
Are connected to the side of (1). As a result, the PLLs 3 and 8 operate in synchronization with the clock 2, and the output clocks 5 and 6 to the network operate in synchronization with the clock 2.

Next, the operation when the clock 2 of one system is disconnected will be described. For example, when the clock 2 supplied to the network synchronizer 42 is cut off, the changeover switch 12 is connected to the side (2). At this time, the NAND gate 34 outputs “1” because there is no input from the outside, and the AND gate 36 passes the clock from the network synchronizer 41. Therefore, the clock is input to the clock generator 21 to the PLL 8. To be done. For this reason, PLL8
Since it is synchronized with L3, it is eventually synchronized with the clock supply device 1. This operation is exactly the same when the clock 2 to the network synchronizer 41 is cut off.

Next, the operation when both clocks 2 are disconnected will be described. When the clock 2 is cut off, the switches 11 and 12 are connected to the side (2). Further, the clock detection circuit 31,3
2 detects the number of clock inputs and outputs "1". By this operation, the outputs of the NAND gates 33 and 34 become "0" and "1", respectively, and the output of the AND gate 35 is prohibited. This makes PLL3
However, since the AND gate 36 allows the clock of the clock generator 21 to pass through, the PLL8 is slave-synchronized with the PLL3.

Thus, according to the above embodiment, the clock supply device 1
Even if both of the clocks 2 from 1 are disconnected, there is an advantage that one network synchronizer can be used as a master to synchronize the two network synchronizers and a hunting phenomenon does not occur.

FIG. 3 shows a main part of another embodiment. In this embodiment, a failure detecting section 50 for detecting a failure of the PLL 3 or 8 is shown.
And an AND gate 51 for prohibiting the network synchronization clock output from the clock generator by the detection output. In this embodiment, since the network synchronization clock output is prohibited due to the PLL failure, there is an advantage that the failure of the device is not propagated to other devices.

FIG. 4 is a conceptual diagram of another embodiment. In this embodiment, by adding network synchronizers 61 and 62, the network synchronization becomes more redundant (in the case of FIG. 4, 4). Has been realized. Furthermore, by increasing the number of clock paths from the clock supply device 1, it is possible to realize a large-scale synchronous network composed of a plurality of sub-networks as shown in FIG.

EFFECTS OF THE INVENTION The present invention has the following advantages, as is apparent from the above-described embodiments.

(1) Since the outputs of a plurality of network synchronizers are fed back to each other, network synchronization can be ensured against the interruption of the clock from the clock supply device.

(2) When all the clocks from the clock supply device are disconnected, one of the network synchronization devices operates as a master, so that a network synchronization system without hunting can be realized.

(3) In the case of a PLL failure, the output of the network synchronization clock is prohibited, so that the failure is not propagated to other systems.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 is a configuration diagram showing the main part of FIG. 1 in more detail, and FIG. 3 is a schematic configuration of another embodiment of the present invention. FIG. 4 is a conceptual diagram of another embodiment of the present invention, FIG. 5 is a conceptual diagram when the present invention is implemented in a large-scale network, and FIGS. 6 and 7 are conventional network synchronizers. It is a block diagram of. 1 …… Clock supply device, 2,5,6 …… Clock, 3,8 ……
PLL, 7 ... Network synchronization clock, 11, 12 ... Switch, 4,
21,22 …… Clock generator, 31,32 …… Clock detector,
33,34 …… NAND gate, 35,36,51 …… AND gate, 9,41,4
2, 61, 62 …… Network synchronizer, 50 …… Failure detection unit.

Claims (2)

(57) [Claims] 1. A phase lock for generating a clock to a network by operating in synchronization with a clock output from the switching means, a plurality of external clock input terminals, a switching means for switching the plurality of input terminals. Loop (PL
L), clock generation means for generating and outputting a clock having the same signal format as the external input clock in synchronization with the output of the PLL, and clock detection means for detecting the presence or absence of a clock input at the external clock input terminal. Controlling means for switching the switching means in a predetermined priority order according to the detection result of the detecting means, and means for switching the internal state so that the PLL is self-propelled when there is no input clock of all external clock input terminals. And a means for detecting a failure of the PLL, and a means for inhibiting output from a clock generation means connected to the PLL in which the failure is detected. 2. A clock supplied from a single clock supply source is input to the highest priority external clock input terminals of a plurality of network synchronizers, and the network synchronization clock output of each network synchronizer is supplied to another network. An external clock input terminal having a low priority of the synchronizer is input, a clock is supplied to the network by a clock output of each of the network synchronizers, and an input clock detection result regarding the highest priority input terminals of the plurality of network synchronizers is input. When inputting to a certain network synchronizer and all the detection results including this network synchronizer are judged to be input disconnection, the PLL of the certain network synchronizer is automatically detected based on the input clock detection result for the input terminal with the highest priority. Network synchronization method to run.