JP2679504B2 - Clock switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock switching, and more particularly to a clock switching control method.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional clock switching circuit includes a 0-system (active) clock unit 1 and a 1-system (standby) clock unit.
It was composed of a clock unit 2 and a control unit 8. The 0-system external clock input a is monitored by the input monitoring circuit 3, and the monitoring information is sent to the judgment control circuit 7 in the control unit 8. The 1-system clock unit is similarly sent to the judgment control circuit 7 in the control unit 8.
The judgment control circuit 7 judges the presence or absence of a clock based on the monitoring information of these two systems and controls the two selection circuits 6 of the 0 system and the 1 system, respectively.

In other words, only when the external input clocks a and b have disappeared in both systems, the decision circuit 7 controls the selection circuit 6 by switching it from the external clock selection mode to the internal clock oscillator 5 mode.

[0004]

In this conventional clock switching circuit, a control unit 8 is required in addition to the 0-system and 1-system clock units, so that the number of units is large and the number of inter-unit controls is large and the structure is complicated. There was a problem that was. That is, in the control unit 8, first, the 0 system,
The input status of the external clock of each 1-system clock unit
Each input monitoring circuit 3 monitors. One external clock
If, for example, only the 0-system external clock is input
The 0-system external clock is output from output c
Controlled, and in the opposite case, the clock is output from the output d of system 1
Need to be controlled. In addition, both external
When no lock is input, the 0-system or 1-system clock is
Send the internal clock oscillator in the lock unit
Clock output from either output c or d
In addition, it is necessary to control by assuming all states.
Had a problem that the process was complicated.

[0005]

The clock switching circuit of the present invention
The path is external to the first external clock and the second clock.
0-system and 1-system clock units to which each is input
And a first external clock and a second external clock
First and second information indicating the input state by monitoring each input
First and second input monitoring circuits that respectively output information,
The first internal clock and the second internal clock are internally generated.
First and second internal clock oscillators generated respectively
, The first information and the second information are input, and the first external clock is input.
If the clock is input, select the first external clock.
Select the first external clock and the second external clock.
Select the first internal clock if
The first selection circuit, the first information and the second information are input,
2nd external clock when 2 external clocks are input
Select a clock to select the first external clock and the second external clock.
Second internal clock if both locks are lost
And a second selection circuit for selecting
doing. The clock switching circuit of the present invention has a selection circuit for switching between an external clock selection mode and an internal clock oscillator mode, and the selection circuit is provided from an external clock input monitoring circuit of its own system and an external input monitoring circuit of an external clock of another system. It has a circuit for inputting information and judging and controlling from the information of the input state of 2.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a switching circuit according to an embodiment of the present invention.

This embodiment comprises a 0-system clock unit 1 and a 1-system clock unit 2, the input monitoring circuit 3 monitors the input state of the 0-system external clock input a, and the judgment information is judged by the judgment control circuit 4. Further, the information from the input monitoring circuit 3 of the external clock input b of the other system is also input to the determination control circuit 4. This allows the external input a,
b 0-system and 1-system selection circuit 6 only when both systems are lost
Performs control to switch to the mode of the internal clock oscillator 5.

In other words, when only the external clock input a disappears, the judgment control circuit 6 does not operate because the external clock input b exists, and the 0-system and 1-system select the external clock mode selection circuit. Therefore, the output c is a non-signal output,
The output d outputs the external clock b. If the external clock b also disappears from this stage, the judgment control circuit 4 of the 0-system 1-system judges that there is no external clock of both systems, and the selection circuit 6
To the internal clock oscillator 5 mode. That is,
The outputs c and d output the internal clock oscillator 5, respectively.

[0010]

As described above, according to the present invention, since the external clock input monitoring information of the 0-system 1-system is mutually passed and the judgment control circuit is also provided with the clock of the 0-system 1-system, the external clock 0 When both the system 1 and the system 1 are lost, the control unit becomes unnecessary, and the number of connections between the units is as small as two, which is advantageous in that the configuration is simple.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 0 system clock unit 2 1 system clock unit 3 Input monitoring circuit 4, 7 Judgment control circuit 5 Internal clock oscillator 6 Selection circuit 8 Control unit a, b External clock input c, d Output

Claims (1)

(57) [Claims] 1. A first external clock is input from the outside.
0-system clock unit and 1-system clock to which a second external clock is input from the outside
The unit and the input of the first external clock to monitor the input state.
A first input monitoring circuit for outputting the first information shown, and monitoring the input of the second external clock to check the input state.
A second input monitoring circuit for outputting the second information shown, and a first internal clock for internally generating the first internal clock.
Clock oscillator and a second internal clock that internally generates a second internal clock.
Clock oscillator, the first information and the second information are input, and the first
If the external clock of the
Local clock, the first external clock and the second external clock are
If both disappear, the first internal clock is selected.
A first selection circuit for selecting, the first information and the second information are input, and the second
If the external clock of the
Local clock, the first external clock and the second external clock are
If both disappear, select the second internal clock
And a second selection circuit for selecting the clock switching circuit.