JPH05297976A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To obtain the clock switching circuit whose circuit scale is small, and also, which can be switched to the own system clock without outputting a component of a high frequency immediately at the time when the other system is abnormal. CONSTITUTION:The circuit is provided with a synchronizing circuit 1 for outputting a synchronization control signal at a variation point of a level of the other system clock, and a clock generating circuit 2 for outputting the own system clock subjected to phase lock with the other system clock on the operation by the synchronization control signal, running freely without depending on the synchronization control signal, when a switching signal is inputted and outputting the own system clock of the same frequency. Also, this circuit is constituted by providing a selector 3 for inputting the other system clock and the own system clock, selecting and outputting the other system clock at a normal time, and selecting and outputting the own system clock, when the switching signal is inputted, and a switching control circuit 4 for sending the switching signal to the clock generating circuit 2 and the selector 3, when the other system abnormality signal is inputted, and outputting the own system clock from the selector 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a clock switching circuit having a digital system active device and a standby device and used for a system for switching to the standby device when the active device is abnormal.

In a system having an active device and a backup device of a digital system, when the active device is abnormal, the clock is also switched to the clock of the backup device so that the backup device operates. There is a demand for providing a clock switching circuit which can prevent a (hazard) from occurring and cause a malfunction, and has a small circuit scale that can instantaneously switch clocks.

[0003]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional clock switching circuit, and FIG. 5 is a time chart of each part of FIG.

In FIG. 4, when the other system clock (clock of the active device) as shown in FIG. 5A is inputted, this clock is inputted to the synchronizing circuit 1, the selector 3 and the phase monitoring circuit 21.

In the synchronizing circuit 1, the synchronizing control signal is input to the clock generating circuit 20 at the rising edge of the clock of the other system, and in the clock generating circuit 20, the synchronizing control signal is used as a trigger to slightly delay the phase as shown in FIG. 5 (B). The own system clock is output and input to the selector 3 and the phase monitoring circuit 21.

In the phase monitor circuit 21, when the levels of the other system clock shown in FIG. 5A and the own system clock shown in FIG. 5B are both L level or H level, as shown in FIG. 5C. An H level switching permission signal is sent to the switching control circuit 22.

In the switching control circuit 22, if the other system abnormal signal is input when the switching permission signal is not input as shown in FIG. 5D, the switching control circuit 22 waits until the switching permission signal is input.
When a switching signal as shown in C of (E) is output and a switching permission signal is input as shown in (D) of FIG. A switching signal as shown is output.

This switching signal is input to the clock generation circuit 20 and the selector 3, and the clock generation circuit 20 self-runs without depending on the synchronization control signal and outputs a clock having the same frequency as that of the other system clock. As shown in FIG. 5F, the other system clock that has been selected and output is switched to the own system clock selection output and used as the internal clock.

The reason why the switching permission signal is output is as follows. When the other system clock is switched to the own system clock when the switching permission signal shown in FIG. 5C is L level which is not switching permission, a high frequency component (hazard) as shown in FIG. 5G is generated and the device malfunctions. May occur,
The switching is performed when the switching permission signal is at the switching permission H level.

[0010]

However, in the conventional clock switching circuit, the phase monitoring circuit for giving the switching permission is required, the circuit scale becomes large, and when there is an abnormality in another system, there is a slight delay when switching to the own system clock. There is a problem that something that must be switched occurs.

It is an object of the present invention to provide a clock switching circuit having a small circuit scale and capable of switching to a self-system clock immediately without outputting a high frequency component when another system malfunctions.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, a synchronization circuit 1 that outputs a synchronization control signal at a change point of the level of the other system clock, and an own system clock that is phase-synchronized with the other system clock in operation by the synchronization control signal, When a switching signal is input, the clock generation circuit 2 that outputs a self-system clock of the same frequency by running independently of the synchronization control signal, and the other system clock and the self system clock are input, and when normal, the other When the selector 3 which selectively outputs the system clock and the switching signal is input, and the selector 3 which selectively outputs the own system clock and the other system abnormality signal
A switching control circuit 4 is provided which sends a switching signal to the clock generation circuit 2 and the selector 3 and causes the selector 3 to output the own system clock.

[0013]

According to the present invention, the clock generation circuit 2 operates in response to the synchronization control signal generated at the change point of the level of the other system clock from the synchronizing circuit 1 to operate its own clock which is phase-synchronized with the other system clock. Since a high frequency component is not output no matter which time the other system clock is switched to the own system clock, the switching control circuit 4 immediately outputs the switching signal to the clock generation circuit 2 and the other system abnormal signal. The clock generation circuit 2 is sent to the selector 3, and the clock generation circuit 2 is made to be free-running. In the selector 3, the other system clock that has been selectively output is immediately switched to the own system clock selection output.

That is, since the phase monitoring circuit of the conventional clock switching circuit is not required, the circuit scale is small and it is possible to switch to the own system clock without outputting a high frequency component immediately when another system malfunctions. ..

[0015]

2 is a block diagram of a clock switching circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of each part of FIG.

In FIG. 2, when another system clock having a frequency of 1 MHz as shown in FIG.
Is inverted and becomes a clock as shown in FIG.
As the clock, the frequency shown in FIG. 3 (C) is 10 MHz.
flip-flops 12 and 1 to which the z clock is input
3 and a differentiating circuit 16 composed of an AND circuit 14 and the selector 3.

The differentiating circuit 16 outputs a pulse as shown in FIG. 3D obtained by differentiating the rising edge of the inverted clock shown in FIG. The selector 15 normally selects and outputs the output side of the differentiating circuit 16, and FIG.
The pulse shown in (D) is input to the synchronous load terminal of the decimal counter 2-1 to which the 10 MHz clock is input.

The output of Qc of the decimal counter is L level between 0 and 3, H level between 4 and 7, and L level between 8 and 9.
Since it becomes the level, a clock as shown in FIG. 3 (E) is output from the output Qc of the decimal counter 2-1 and is inverted by the knot circuit 2-2, and the inverted other system clock shown in FIG. 3 (B). Figure 3 is a phase advance of 1/2 cycle of 10MHz
A clock as shown in (F) is output.

That is, in operation, a clock that is phase-synchronized with the other system clock is output. When another system abnormal signal as shown in FIG. 3 (H) is input to the flip-flop 4 as a clock, the output of the flip-flop 4 becomes an H-level switching signal as shown in FIG. Then, the selector 15 selects the ground side and
It is given to the synchronous load terminal of the decimal counter 2-1 so that the decimal counter 2-1 self-runs.
The one in which the inverted other system clock shown in (B) is selected,
The output of the decimal counter 2-1 is switched so as to select the own system clock, and a clock obtained by switching the other system clock to the own system clock is output from the output as the internal clock.

That is, since the own system clock is phase-synchronized with the other system clock in operation, the phase monitoring circuit is unnecessary and the circuit scale becomes small, and the high frequency component is output immediately when the other system abnormality occurs. Instead, you can switch to your own system clock.

[0021]

As described in detail above, according to the present invention, the clock can be switched to the own system clock with a small circuit scale and immediately when another system is abnormal without outputting a high frequency component. There is an effect that a circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of a clock switching circuit according to an embodiment of the present invention,

FIG. 3 is a time chart of each part of FIG.

FIG. 4 is a block diagram of a conventional clock switching circuit,

FIG. 5 is a time chart of each part of FIG.

[Explanation of symbols]

 1 is a synchronous circuit, 2 is a clock generation circuit, 2 is a decimal counter, 2 is a notation counter, 2 is a 11 is a knot circuit, 3 is a selector, 4 is a flip-flop, a switching control circuit, and 12 is a flip-flop. 14 is an AND circuit, 16 is a differentiating circuit, 21 is a phase monitoring circuit, and 22 is a switching control circuit.

Claims (1)

[Claims] 1. A synchronizing circuit (1) which outputs a synchronization control signal at a change point of the level of the other system clock, and an own system clock which is phase-synchronized with the other system clock by the synchronization control signal. When a switching signal is input, a clock generation circuit (2) that self-runs independently of the synchronization control signal and outputs the own system clock of the same frequency, and the other system clock and the own system clock Is a selector (3) that selectively outputs the other system clock and selectively outputs the own system clock when a switching signal is input, and a clock generation circuit (2) and the selector (3) when another system abnormality signal is input. And a switching control circuit (4) for sending a switching signal to the selector (3) to output the own system clock.