JPH11355259A - Clock confounding/distributing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock hardware scale distributing device which is inexpensive and small and is capable of shortening the processing halt time at the time of clock switching by providing a synchronized transmission means with n-fold phase for outputting the result obtained by multiplying the frequency of a selected clock by (n), and supplying the result obtained by further multiplying by (n) to a processing unit and a system control means or the like for operating the active/standby switching of an information processor. SOLUTION: At a processor #0, for example, the clock frequency is increased by a PLL 8 after an active/standby clock selector circuit, and plural PLL 10-12, after the outputted clock further increase the clock frequency and supplied to the processing unit. A system control circuit 20 sends a control signal to a system control circuit 120 and performs the selection of active/standby clock of the processor #0, reset, start/stop and the active/standby switching operation of the processor corresponding to information from the system control circuit 120. Besides, all the phase-matched signals of PLL 10-12 on the final step are detected and reported to the system control circuit 120.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock confounding distribution device and a clock confounding distribution method suitable for use in a duplex information processing system.

[0002]

2. Description of the Related Art Conventionally, as a technique for confounding and distributing a clock signal to an information processing system in which an information processing apparatus is duplicated,
For example, Japanese Patent Application Laid-Open Nos. 7-177525 and 6-2
These are disclosed in, for example, JP-A-66464 and JP-A-5-130093. JP-A-7-177025
The technology disclosed in Japanese Patent Application Publication No. JP-A-2005-26095 discloses a selection unit that selects one of an input reference clock and a clock transmitted from another system, a switching control unit that controls selection switching thereof, and a clock synchronized with the selected clock. The clock device having the phase synchronizing means and the frequency dividing circuit is constructed in a duplex configuration, and is provided with output means for selecting and outputting one of the output clocks of the two.

On the other hand, the technique disclosed in Japanese Patent Application Laid-Open No. 6-266644 discloses a length equalizing means for equalizing a signal transmission delay so as to receive a clock input signal and simultaneously reach a plurality of functional units, and a clock drive. Buffer means. Japanese Patent Application Laid-Open No. Hei 5-130093 discloses a system clock generator, a controller for synchronizing the system clocks of both systems, a selector for selecting one of the system clocks, and an externally provided system clock. Clock distribution system in a plurality of two-system internal devices each including a two-system synchronizer each having a distribution output unit for outputting to the system and a selector for selecting a system clock transmitted from each of the two synchronizers Based on the status of the system clocks of both systems, the selectors in the synchronizers of both systems select the system clock. The configuration has a function of controlling the selector in consideration of the state of the system clock.

[0004]

Incidentally, the above-mentioned Japanese Patent Application Laid-Open No. Hei 7-177525 and Japanese Patent Application Laid-Open No.
According to the technology disclosed in Japanese Patent Publication No. 3 (1994), the confounding of clocks between information processing systems is performed at the same clock (frequency) as the clock distributed to each unit in the information processing system, while the duplicated information is used. Since the own system (0 system or 1 system, self or mate) and the other system (1 system or 0 system, mate or self) of the processing system are physically separated, a fast clock (high frequency) signal is entangled. In such a case, it is necessary to use a special wiring, resulting in a problem of high cost.

In order to solve this problem, it is conceivable to use a plurality of clocks whose phases are shifted from each other of a slow clock (low frequency) signal.
In this case, a new problem arises in that the hardware scale is increased.

Further, in an information processing apparatus using a large number of units, the configuration scale becomes large.
In the techniques disclosed in Japanese Patent No. 464 and Japanese Patent Application Laid-Open No. Hei 5-130093, a length equalizing means, an area buffer and a distribution output unit are provided, but a clock distributed in such a configuration is used in each unit. Since the clock signal is the same as that of the above, many expensive parts and circuits that operate at high speed must be used, which causes a problem of increasing the product cost.

Further, there has been proposed a mode in which two or more phase-locked oscillators (stages) are connected in cascade to the clock distribution circuit. In this case, when the input clock of the phase-locked oscillator is switched, the mode is generally changed. It takes several milliseconds to several tens of milliseconds until the output clock stabilizes, that is, until the phases match (LOCK). When two stages are cascaded, when the input clock of the first PLL is switched (phase is shifted), it takes (2) × (several tens of milliseconds) at the worst value until the phase of the last stage PLL matches. Therefore, during this time, the operation of the information processing system (information processing device) is no longer guaranteed, and there is a problem that the information processing system (information processing device) stops processing for a long time when the clock is switched.

The present invention solves each of the above-mentioned problems, and is an inexpensive and small-scale hardware, and furthermore, a clock confounding distribution apparatus and a clock confounding distribution apparatus which realize an information processing system in which processing stop time is reduced when switching clocks. It is intended to provide a way.

[0009]

In order to achieve the above object, according to the first aspect of the present invention, a low frequency is used as a confounding clock between information processing devices that use a duplexed clock in a confounding manner, and thereafter, After the clock distribution is performed by increasing the clock frequency, the clock frequency is further increased and supplied to each processing unit included in the information processing apparatus to optimize the processing stop time of the information processing apparatus.

According to a second aspect of the present invention, there is provided a dual information processing system comprising an own information processing apparatus and another information processing apparatus which uses a duplex clock composed of first and second clocks in a confounding manner. An n-multiplied phase synchronizing transmission means provided at a stage subsequent to the selecting means for selecting one of the first and second clocks and multiplying and outputting the frequency of the selected clock by n; A plurality of stages of n-multiplied phase synchronization transmitting means provided on the output side and further multiplying the frequency of the n-multiplied clock by n, and supplying the multiplied clock to the processing unit; A system control means for selecting, resetting, starting and stopping the current / protective clock of the device, and switching between the current / protective state of the information processing device; Notification means for detecting all the coincidence signals with respect to the final-stage phase coincidence signal in the n-multiplied phase synchronization transmission means and reporting the same to the system control means on the other system side; Optimizing the processing stop time of the information processing apparatus by using the output of the n-multiplied phase synchronizing transmission means and supplying it to each processing unit using the outputs of the plurality of stages of n-multiplied phase synchronizing transmission means for clock distribution. Features.

According to the present invention, a low frequency is used as a confounding clock between information processing devices that use a duplicated clock in a confounding manner, and thereafter the clock frequency is increased to distribute the clock, and then the clock frequency is further increased. An information processing system is supplied to each processing unit constituting the information processing apparatus to optimize the processing stop time of the information processing apparatus, so that it is inexpensive, has a small hardware scale, and reduces the processing stop time when switching clocks. Can be embodied.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a duplex information processing system using a clock confounding and distributing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1 is a block diagram illustrating a configuration of a redundant information processing system including a processing device # 0 and a processing device # 1. Hereinafter, when the processing device # 0 is referred to as “self system” or “self”,
Processing device # 1 is called another system or mate, and processing device #
1 is referred to as “self system” or “self”.
Becomes another system or mate.

Now, the processing device # 0 (or the processing device #
In 1), reference numeral 1 101 denotes a clock generator for generating a rectangular wave (pulse) having a frequency f0. An output signal of the clock generator 1 is supplied to a first input of an AND circuit 4 and a first input of an AND circuit 104 of another system via a signal line 2. The output signal of the clock oscillator 101 is
Is supplied to the first input of the AND circuit 106 and the first input of the AND circuit 6 of the other system. Outputs of the AND circuits 4 and 6 are connected to first and second inputs of an OR circuit 7, respectively. The output of the OR circuit 7 is connected to an n-multiplied phase-locked oscillation circuit (PLL) 8. Thereafter, the n-multiplied phase-locked oscillation circuit (PL
L) is called nPLL.

An nPLL 8 that outputs a clock signal twice as large as the input clock signal is connected via a signal line 9 to each nPL of its own system.
It is connected to PLLs 10, 11, and 12, and performs clock distribution. In addition, you may use an amplifying element as needed.
Each of the nPLLs 10, 11, and 12 outputs a clock signal that is twice the input clock signal. The output clock of the nPLL 10 is connected to the system control circuit 20. nPL
The output clocks of L11 and L12 are output from the respective units 21 and 22.
Is connected to The phase matching (LOCK) signals of the nPLLs 10, 11, and 12 are connected to the system control circuit 20 via signal lines 14, 16, and 18, respectively.

The unit 21 is an MPU (microprocessor unit). The unit 22 is an MM (main memory). The system control circuit 20 is connected to the second input of the AND circuit 4 and the inversion element 5 via the clock selection signal line 3. The output of the inversion element 5 is the second input of the AND circuit 6. Hereinafter, the inversion element 5, the AND circuits 4 and 6, and the OR circuit 7 are referred to as a working / standby clock selection circuit or a clock switching circuit.

The system control circuit 20 includes an RST signal for resetting the processing device, an STA signal for starting operation of the processing device from a specific address, an STP signal for stopping the processing device, and an active / standby signal for indicating the operation state of the processing device ( AC
T / SBY) signal. The system control circuit 20 and the units 21 and 22 are connected via a bus 30.

The configuration of the processing device # 1 is a configuration in which 100 is added to the number of the processing device # 0. That is, the system control circuit 20 sends the signal from the processor bus 30 and the coincidence signal of the phase coincidence (LOCK) signal lines 14, 16, and 18 (an AND signal) via the signal line 40 to the system of the mate processing device. It is connected to the control circuit 120. In addition, the system control circuit 120 transmits a signal from the processor bus 130 to the phase matching (LOCK) signal line 11.
4, 116, 118 coincidence signal (AND signal)
Is connected to the system control circuit 120 of the mate processing device via a signal line 140.

Next, the operation of the embodiment having the above configuration will be described. In FIG. 1, it is assumed that the processing device # 0 is active, the processing device # 1 is standby, and the clock generator 1 is in use. That is, the clock selection signal line 3 is instructed by the system control circuit 20 to be “1”, the active / standby signal line is instructed to be active, and the system control circuit 120 is not instructed by the clock selection signal line 103 to be “0”. , A state where the protection of the working / protection signal line is instructed.

The processing device # 0 supplies the output clock of the clock generator 1 to the nPLL 8 through the AND circuit 4. The nPLL 8 doubles the frequency of the received clock and distributes it to the nPLLs 10, 11, and 12 for each unit. In the nPLLs 10, 11, and 12, the frequency is further doubled and supplied to each unit. Processing device # 1
The output clock of the clock generator 1 is supplied to the AND circuit 104.
To the nPLL 108 through nPLL108
Makes the receiving clock twice the frequency and distributes it to the nPLLs 110, 111, 112 for each unit. nP
In the LLs 110, 111, and 112, the frequency is further doubled and supplied to each unit. Therefore, if the output clock of the clock generator 1 is f0, each unit has 4
The clock of f0 is supplied.

Next, the operation of switching the clock of the redundant information processing system from system 0 to system 1 in the present embodiment will be described. First, the clock of the processing device # 1 is changed from 0 system to 1 system.
The operation of changing to the system will be described. Working processor # 0
Instructs the system control circuit 120 to stop via the system control circuit 20. System control circuit 120
Stops the processing device # 1 on the STP signal line. Next, a reset instruction is issued to the system control circuit 120. The system control circuit 120 uses the RST signal line to
Reset 1 Further, it instructs the system control circuit 120 to switch the clock.

The system control circuit 120 instructs the clock switching circuit “1” to switch the clock via the clock selection signal line 103. The condition of the AND circuit 104 is not satisfied, and the condition of the AND circuit 106 is satisfied.
The output clock of the clock generator 101 is nPL10
8 is supplied. The output clock of the nPLL 108 becomes unstable. That is, a situation occurs in which the phases do not match (LOCK). Similarly, the output clocks of the nPLLs 110, 111, and 112 become unstable. That is, a situation occurs in which the phases do not match (LOCK). System control circuit 12
0 indicates that the phase match (LOCK) signal does not match the signal line 1
The other system control circuit 20 is notified via 40. The system control circuit 20 notifies the MPU 21 via the processor bus 30. The MPU 21 controls the R of the system control circuit 120 via the system control circuit 20.
The output signal of the nPLL 108 is stabilized while the ST signal is continuously output. Then, nPLL110,1
The output clocks of 11, 112 are also stabilized. That is, the phases match (LOCK).

The system control circuit 120 includes the nPLL 11
The system control circuit 2 of the other system checks whether the phase matching (LOCK) signals of 0, 111, and 112 match via the signal line 140.
Inform 0. The system control circuit 20 notifies the MPU 21 via the processor bus 30. MPU21
Stops the RST signal of the system control circuit 120 via the system control circuit 20.

Next, the MPU 21 controls the system control circuit 2
For 0, the working / spare signal line is set to the spare, and the working / spare signal line is made active to the system control circuit 120 via the system control circuit 20. Then, the MPU 21 transmits the signal to the system control circuit 120 via the system control circuit 20.
At the STA signal line to start the operation of the processing device # 1. Also, the MPU 21 instructs the system control circuit 20 to stop using the STP signal line, and the processing device # 0 stops the operation in response to the instruction.

Next, the operation of changing the clock of the processing device # 0 from the 0 system to the 1 system will be described. Working processor #
When 1 issues a stop instruction to the system control circuit 20 via the system control circuit 120, the system control circuit 20 stops the processing device # 0 via the STP signal line. In this operation example, it has already stopped. Next, when a reset instruction is given to the system control circuit 20, the system control circuit 20
Resets the processing device # 0 through the RST signal line.
Further, it instructs the system control circuit 20 to switch the clock (from “1” to “0”).

The system control circuit 20 gives an instruction “0” to the clock switching circuit via the clock selection signal line 3. The condition of the AND circuit 4 is not satisfied, and the AND circuit 6
Is satisfied. The output clock of the clock generator 101 is supplied to the nPLL 8 through the AND circuit 6, and as a result, the output clock of the nPLL 8 becomes unstable. That is, a situation occurs in which the phases do not match (LOCK). Similarly,
The output clocks of the nPLLs 10, 11, and 12 also become unstable, resulting in a situation where the phases do not match (LOCK).

Then, the system control circuit 20 notifies the other system control circuit 120 of the mismatch of the phase match (LOCK) signal via the signal line 40. The system control circuit 120 notifies the MPU 121 via the processor bus 130. The MPU 121 controls the R of the system control circuit 20 via the system control circuit 120.
The output signal of the nPLL 8 stabilizes during the output of the ST signal. Accordingly, the nPLLs 10, 11, 1
The output clock 2 also stably matches (LOCK).

The system control circuit 20 includes the nPLL 10,
The coincidence of the phase coincidence (LOCK) signals of 11 and 12 is notified to the other system control circuit 120 via the signal line 40. Then, the system control circuit 120 notifies the MPU 121 via the processor bus 130. MPU
121 stops the RST signal of the system control circuit 20 via the system control circuit 120. MPU121
Instructs the system control circuit 20 to start via the STA signal line via the system control circuit 120. The processing device # 0 starts operation. Thus, the operation of switching the clock of the redundant information processing system from the 0 system to the 1 system ends. As described above, an operation of changing the clock of the information processing system from the 1 system to the 0 system is also possible.

In this embodiment, an example is shown in which a two-stage phase-locked oscillation circuit is connected in cascade between the clock switching circuit and the processing unit. However, the present invention is not limited to this, and the operable clock frequency of the processing unit is higher. In this case, the doubling phase-locked oscillator and the quadrupled phase-locked oscillator can be realized by cascade connection in two stages, or of course, the doubling phase-locked oscillator can be realized by cascade connection in four stages. It is.

As described above, according to the present invention, in a duplex information processing system using a duplex clock in a confounding manner, an n-multiplied phase-locked oscillation circuit (PLL) is installed after a working / standby clock selection circuit. A clock frequency is increased, and an n-multiplier PLL of one or more stages is installed after the output clock of the PLL, and the clock frequency is further increased and supplied to the processing unit. Sends a control signal to the control circuit, selects, resets, starts and stops the current / standby clock of the own information processing device based on information from the other system control circuit, and uses the current / standby information processing device (ACT / SBY).
A system control circuit for performing a switching operation is provided, and the own system control circuit includes a phase match (L
A means for detecting all coincidence signals of the OCK signal and informing the other system control circuit is provided, so that the confounding clock between the information processing devices is performed at a low frequency, and then the clock frequency is increased to distribute the clock. Then, the clock frequency is further increased and supplied to the processing unit to optimize the processing stop time of the information processing apparatus.

[0030] For this reason, confounding can be performed with a clock having a lower frequency than that supplied to the unit, and an inexpensive information processing system with a small hardware scale can be provided. Further, the method of distributing clocks by cascading nPLLs in a plurality of stages can lower the distribution clock frequency in the information processing apparatus, is technically easy, does not use many expensive components and circuits, and is economical. It is possible to provide a simple information processing system. Further, the own-system processing unit can smoothly execute the necessary processing at the time of clock switching by knowing the phase matching of all the last-stage nPLLs of the cascaded nPLLs in the other system, and optimizes the clock switching time. An information processing system according to the present invention can be provided.

[0031]

According to the present invention, a low frequency is used as a confounding clock between information processing apparatuses that use a convoluted clock in a convoluted manner. Since the frequency is increased and supplied to each processing unit configuring the information processing apparatus, and the processing stop time of the information processing apparatus is optimized, the cost and the hardware scale are small, and the processing stop time at the time of clock switching is reduced. An information processing system can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a duplex information processing system using a clock confounding distribution device according to an embodiment of the present invention.

[Explanation of symbols]

1,101 Clock oscillator 4,6,104,106 AND circuit 5,105 Inverting element (inverter) 7,107 OR circuit 8,108,10,110 n-multiplied phase-locked oscillator 11,111,12,112 n-multiplied Phase synchronization oscillation circuit 20, 120 System control circuit 21, 121 MPU (microprocessor unit)

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[Procedure amendment]

[Submission date] July 2, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Clock confounding distribution device

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

BACKGROUND OF THE INVENTION The present invention is related to a preferred clock interlacing distribution device using the duplexed information processing system
I do .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

Further, there has been proposed a mode in which two or more phase-locked oscillators (stages) are connected in cascade to the clock distribution circuit. In this case, when the input clock of the phase-locked oscillator is switched, the mode is generally changed. It takes several milliseconds to several tens of milliseconds until the output clock stabilizes, that is, until the phases match (LOCK). When two stages are cascaded, when the input clock of the first PLL is switched (phase is shifted), it takes (2) × (several tens of milliseconds) at the worst value until the phase of the last stage PLL matches. That is, the maximum value of several tens of milliseconds x 2 (stages)
This will take minutes. Therefore, during this time, the operation of the information processing system (information processing device) is no longer guaranteed, and there is a problem that the information processing system (information processing device) stops processing for a long time when the clock is switched.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

The present invention solves the above-mentioned problems, and provides a clock confounding and distributing apparatus which realizes an information processing system which is inexpensive, has a small hardware scale, and shortens the processing stop time at the time of clock switching. It is intended to be.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

[0009]

Means for Solving the Problems To achieve the above object,
According to the first aspect of the present invention, in the dual information processing system including the self-system information processing device and the other-system information processing device using the duplicated clock including the first and second clocks in a confounding manner, Provided at the subsequent stage of the selecting means for selecting one of the first and second clocks,
N-multiplied phase-locked transmitting means for multiplying the frequency of the selected clock by n and outputting the same, and an output side of the n-multiplied phase-locked transmitting means for further multiplying the frequency of the n-multiplied clock by n Plural stages of n-multiplied phase synchronous transmission means to be supplied to the processing unit, selection, reset, start and stop of current / standby clocks of the own information processing apparatus based on information from the other information processing apparatus, and current use of the information processing apparatus / System control means for performing a switching operation for backup /
Not include and informing means for informing to detect all of the coincidence signal for a phase coincidence signal of the last stage to the system control unit of the other system side in the n multiplication phase synchronization transmitting means of said plurality of stages
You.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

In the case where the clock of the redundant information processing system is switched between the first clock and the second clock, the clock of the other information processing apparatus on the standby side is changed.
The switching is performed according to the following procedure. The active side information processing device on the active side
The other system on the standby side through the route and the system control circuit of the other system
Stop and reset the information processing device, and
The clock switching means is instructed to switch clocks. The clock supplied to the n-multiplied phase synchronous transmission means of the other system is
Switch between a first clock and a second clock
The output of the multi-stage n-multiplied phase-synchronized transmitting means of the other system.
When the phases match, the system control circuit of the other system
Inform the stem control circuit of the phase match. The self-system information processing device includes the self-system control circuit and other
The operation of the other system information processing device via the system control circuit of the system
Start the work. Clock of the local information processing device on the standby side
The switching is performed according to the following procedure. The other-side information processing device on the active side is used to control the other system.
The standby side's own system via the
Stop and reset the information processing device, and
The clock switching means is instructed to switch clocks. The clock supplied to the self-system n-multiplied phase synchronization transmitting means is
Switch between a first clock and a second clock
The output of the multi-stage n-multiplied phase-synchronized transmitting means of the own system.
When the phase matches, the system control circuit of the own system
Inform the stem control circuit of the phase match. The other-system information processing device includes the other-system control circuit and the
The operation of the information processing device of the own system through the system control circuit of the
Start the work.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

As described above, according to the present invention, in a duplex information processing system using a duplex clock in a confounding manner, an n-multiplied phase-locked oscillation circuit (PLL) is installed after a working / standby clock selection circuit. A clock frequency is increased, and an n-multiplier PLL of one or more stages is installed after the output clock of the PLL, and the clock frequency is further increased and supplied to the processing unit. Sends a control signal to the control circuit, selects, resets, starts and stops the current / standby clock of the own information processing device based on information from the other system control circuit, and uses the current / standby information processing device (ACT / SBY).
A system control circuit for performing a switching operation is provided, and the own system control circuit includes a phase match (L
A means for detecting all coincidence signals of the OCK signal and informing the other system control circuit is provided, so that the confounding clock between the information processing devices is performed at a low frequency, and then the clock frequency is increased to distribute the clock. Then, the clock frequency is increased and supplied to the processing unit, so that the processing stop time of the information processing apparatus can be shortened .

Claims (2)

[Claims] 1. A low-frequency clock is used as a confounding clock between information processing devices that uses a duplexed clock in a confounding manner. After that, the clock frequency is increased to distribute the clock, and then the clock frequency is further raised to increase the information. A clock confounding / distribution method, wherein the clock entanglement distribution method is supplied to each processing unit included in a processing device to optimize a processing stop time of the information processing device. 2. A dual information processing system comprising an own information processing apparatus and another information processing apparatus using a duplicated clock composed of first and second clocks in a confounding manner, wherein the first clock and the second clock are used. An n-multiplied phase-synchronized transmitting means provided at a stage subsequent to the selecting means for selecting any one of the following, and multiplying the frequency of the selected clock by n for output; Plural stages of n-multiplied phase synchronous transmission means for further multiplying the frequency of the n-multiplied clock by n and supplying the same to the processing unit, and a working / spare clock of the own-system information processing device based on information from the other-system information processing device System control means for selecting, resetting, starting, stopping, and switching operation of the information processing apparatus between active and standby; Notifying means for detecting all the coincidence signals with respect to the phase coincidence signal of the last stage in the stage and informing the system control means on the other system side, wherein the confounding clock between the information processing devices is the n-times multiplied phase synchronous transmission means Clock convolution distribution, wherein the outputs of the plurality of stages of n-multiplied phase synchronous transmission means are used for clock distribution and supplied to each processing unit to optimize the processing stop time of the information processing apparatus. apparatus.