KR100352125B1 - Device for Multiplexing Asynchronous Clock Signal - Google Patents

Abstract

The present invention relates to an asynchronous clock signal multiplexing apparatus, wherein when the first clock selection signal changes, the first clock protection signal is changed, and the second clock selection signal is changed by detecting a change in the safety_flag signal value. A flag generator that is a finite state machine; A first asynchronous / synchronous signal generator synchronized with the second clock to sense a change in the first clock protection signal and to change a second clock protection signal when the second clock is in operation; A safety flag generator for detecting a change in the second clock protection signal to change a first safety flag flag; A second asynchronous / synchronous signal generator which senses a change in the first safety flag signal to change a second safety_flag signal and inputs it to the flag generator to cause the flag generator to change a second clock selection signal; Synchronized by the first clock, and generates the same signal as the first clock in the normal state, and when the change of the first clock protection signal and the second safety_flag signal is detected, the high level until the return to the normal state A first clock signal regenerator for generating a signal of the first clock signal generator; And a second signal synchronized with the second clock, and generating a signal identical to the second clock in a normal state, and generating a high level signal until returning to a normal state when detecting the change of the second clock protection signal. And a clock signal regenerator.

According to the device according to the present invention, it is possible to convert the clock without generating a glitch, and to provide a stable clock by providing a safe mode so that it can be replaced by another clock even if one clock does not work. There is an advantage.

Description

Device for Multiplexing Asynchronous Clock Signal

The present invention relates to an asynchronous clock signal multiplexing device, and more particularly, to accept a different clock as an input to change the clock signal without glitch, and if any one clock stops, irrespective of the clock select signal The present invention relates to a clock signal multiplexing device having a safe mode using a clock that is currently operating so as to be suitable for maintaining clock continuity.

1 shows a configuration of an apparatus for converting an asynchronous signal into a synchronous signal in accordance with a conventional base clock.

As shown in FIG. 1, the apparatus for converting a conventional asynchronous signal includes a latch 10, a multiplexer 11, and an AND operator 12.

In FIG. 1, the latch 10 inputs a latching signal to the multiplexer 11 when the system reset signal and the base clock signal provided from the outside are at a high level in response to the first reset signal provided from the outside.

The multiplexer 11 multiplexes the asynchronous signal and the output signal from the latch 10 in response to the base clock signal and inputs the signal to the logical product operator 11. The output signal from the multiplexer is a signal in which the asynchronous signal and the output signal from the latch 10 are synchronized in response to a base clock.

The AND product 12 receives the output signal of the multiplexer 11 and the system reset signal as inputs, and outputs a synchronization signal obtained by the AND operation to the base clock in synchronization with the base clock.

FIG. 2 shows waveforms in the apparatus for converting the asynchronous signal shown in FIG. 1 into a synchronous signal.

As shown in FIG. 2, it can be seen that the input asynchronous signal is synchronized at the rising edge of the base clock.

3 shows a configuration of a conventional asynchronous clock signal multiplexing device.

As shown in FIG. 3, the conventional asynchronous clock signal multiplexing apparatus includes a first asynchronous / synchronous signal generator 30, a flag generator 31, a second asynchronous / synchronous signal generator 32, and a third asynchronous / synchronous signal. The generator 33 includes a first clock signal regenerator 34, a second clock signal regenerator 35, and a multiplexer 36.

The first asynchronous / synchronous signal generator 30 supplies a clock selection signal to the flag generator 31 in synchronization with the first clock signal when the asynchronous selection signal is input.

The flag generator 31 receives a first clock reprotect signal and a first clock signal fed back from the clock select signal and the third asynchronous / synchronous signal generator 33 to generate a first clock protect signal and a clock select regenerator. A signal is generated, the generated first clock protection signal is provided to the second asynchronous / synchronous signal generator 32, and the generated clock selection regeneration signal is provided to the multiplexer 36, respectively.

The second asynchronous / synchronous signal generator 32 receives the first clock protection signal and the second clock signal and supplies a second clock protection signal to the third asynchronous / synchronous signal generator 33 to prevent the second clock signal. It is provided to the first clock signal regenerator 60, respectively.

The third asynchronous / synchronous signal generator 33 receives the first clock signal and the second clock protection signal and feeds back a first clock re-protection signal to the flag generator 31.

The first clock signal regenerator 34 receives the first clock protection signal and the first clock signal and provides a new first clock regeneration signal to the multiplexer 36.

The second clock signal regenerator 35 receives the second clock protection signal and the second clock signal and provides a second clock regeneration signal to the multiplexer 36.

The multiplexer 36 selectively outputs one of the first clock regeneration signal and the new second clock regeneration signal in response to the provided first and second clock regeneration signals.

4 illustrates a clock conversion timing diagram of the conventional asynchronous clock signal multiplexing apparatus.

As shown in FIG. 4, the output clock signal is an original first clock signal output from the first clock signal regenerator 34 and the second clock signal generator 35 when the clock selection signal is at a low level. And outputting the second clock signal as it is, but when the clock selection signal is input and converted to a high level, the first clock regeneration signal and the new second clock in response to the first clock protection signal and the second clock protection signal, respectively. Output the regeneration signal. Also, when the clock selection regeneration signal output from the flag generator 31 is at the low level, the first clock regeneration signal is output, but when the clock selection regeneration signal is high, the second clock regeneration signal is output through the waveform diagram. Can be.

The conventional asynchronous clock signal multiplexing device as described above is designed to be converted to the second clock signal even when the second clock signal does not operate when the first clock signal is converted to the second clock signal. This conventional asynchronous clock signal multiplexing device has a disadvantage that it can have a fatal effect in the circuit where the continuity of the clock is important.

In the present invention, in order to solve the problems of the prior art as described above, even if any one clock stops operation, even if a clock selection signal to convert the operation stops, until the clock stops operating again The present invention proposes an asynchronous clock signal multiplexing device having a safe mode that maintains a current clock and converts it to a corresponding clock when the stopped clock is operated again.

1 illustrates a configuration of an apparatus for converting an asynchronous signal into a synchronous signal in accordance with a conventional base clock.

FIG. 2 shows waveforms in an apparatus for converting the asynchronous signal shown in FIG. 1 into a synchronous signal, FIG.

3 illustrates a configuration of a conventional asynchronous clock signal multiplexing device,

Figure 4 shows a clock conversion timing diagram of a conventional asynchronous clock signal multiplexing device,

5 illustrates a configuration of an asynchronous clock signal multiplexing device according to a preferred embodiment of the present invention.

6 shows a clock conversion timing diagram when the first clock and the second clock are operating normally;

7 illustrates a clock conversion timing diagram when the first clock operates normally but the second clock stops.

In order to achieve the above object, the asynchronous clock signal multiplexing apparatus according to the present invention changes the first clock protection signal when the first clock selection signal changes, and detects the change of the safety_flag signal value. A flag generator for varying two clock select signals and being a finite state machine; A first asynchronous / synchronous signal generator synchronized with the second clock to sense a change in the first clock protection signal and to change a second clock protection signal when the second clock is in operation; A safety flag generator for detecting a change in the second clock protection signal to change a first safety flag flag; A second asynchronous / synchronous signal generator which senses a change in the first safety flag signal to change a second safety_flag signal and inputs it to the flag generator to cause the flag generator to change a second clock selection signal; Synchronized by the first clock, and generates the same signal as the first clock in the normal state, and when the change of the first clock protection signal and the second safety_flag signal is detected, the high level until the return to the normal state A first clock signal regenerator for generating a signal of the first clock signal generator; And a second signal synchronized with the second clock, and generating a signal identical to the second clock in a normal state, and generating a high level signal until returning to a normal state when detecting the change of the second clock protection signal. And a clock signal regenerator.

The present invention further includes a first latch and a second latch connected to the first asynchronous / synchronous signal generator and the second asynchronous / synchronous signal generator, respectively, to prevent a timing loop.

The state of the flag generator, which is a finite state machine, is that the first clock protection signal changes after detecting a change in the first clock selection signal and a first state having the same state of the first clock selection signal and the second clock selection signal. And a third state which automatically transitions to maintain the protection signal in the second state, and a fourth state that transitions when the operation of the second clock is not detected in the second state. It features.

And the flag generator and the second asynchronous / synchronous signal generator are synchronized by the first clock, and the safety flag generator is synchronized by a second clock.

Hereinafter, exemplary embodiments of an asynchronous clock signal multiplexing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

5 illustrates a configuration of an asynchronous clock signal multiplexing apparatus according to a preferred embodiment of the present invention.

As shown in FIG. 5, the asynchronous clock signal multiplexing apparatus according to the preferred embodiment of the present invention includes a flag generator 50, a first asynchronous / synchronous signal generator 51, a safety flag generator 52, and a second asynchronous / synchronous signal. And a signal generator 53, a first clock signal regenerator 54, a second clock signal regenerator 55, a multiplexer 56, a first latch 57, and a second latch 58.

In FIG. 5, the plug generator 50 is synchronized by a first clock, and according to a preferred embodiment of the present invention as a finite state machine, operates differently according to four states. For convenience of description, the four states will be referred to as '00' state, '01' state, '10' state, and '11' state, respectively. '00' state means a state in which the first clock selection signal and the second clock selection signal are the same. In the '00' state, when the first clock selection signal is different from the second clock selection signal, the first protection signal for the first clock is changed in synchronization with the first clock to a low level. '01' state refers to a state after the first protection signal is changed to a low level. The '10' state automatically transitions from the '01' state in order to maintain the period in which the protection signal is maintained for a predetermined clock. '11' state refers to a state in which the second clock to be converted does not operate when the clock is to be converted from the first clock to the second clock. The flag generator 50 also detects the transition of the second safety_flag signal to the low level in the '10' state and changes the second clock selection signal to the same level as the first clock signal.

The first asynchronous / synchronous signal generator 51 detects that the first protection signal is changed to the low level by the flag generator 50 in the '01' state and changes the second protection signal to the low level. The first asynchronous / synchronous signal generator 51 is synchronized with the second clock, and if the second clock is not operating, the second protection signal cannot be changed to the low level.

The first safety flag generator 52 is synchronized with a second clock, and the first asynchronous / synchronous signal generator 51 senses that the second protection signal is changed to a low level and maintains a high level. It changes the safety_flag signal to low level.

The second asynchronous / synchronous signal generator 53 is synchronized with the first clock, and the first safety flag generator 52 detects that the first safety flag flag has changed to a low level, thereby maintaining a high level. The second safety_flag signal is changed to the low level and input to the flag generator 50.

The first clock signal regenerator 54 is synchronized by the first clock, and generates a signal such as the first clock in a normal state, but continuously high when the first protection signal and the second safety flag signal are kept at a low level. It generates a signal to maintain the level, and when the transition to the '00' state generates the same signal as the first clock again.

The second clock signal regenerator 55 is synchronized with the second clock and generates a signal such as the second clock in the normal state, but continuously maintains the high level in the protection period in which the second protection signal changes to the low level. Generate a signal.

The multiplexer 56 selectively outputs any one of an output signal from the first clock signal regenerator 54 and an output signal from the second clock signal regenerator 55.

The first latch 57 and the second latch 58 are connected to the first asynchronous / synchronous signal generator 51 and the second asynchronous / synchronous signal generator 53, respectively, and the second clock protection signal, which is their output signal, and It serves to prevent the formation of a timing loop for the second safety flag flag.

According to a preferred embodiment of the present invention, the first asynchronous / synchronous signal generator 51 and the second asynchronous / synchronous signal generator 53 are composed of a latch and a combinational logic circuit, and the flag generator 50 and a safety flag. Generator 52 is comprised of flip-flops.

Hereinafter, an operation of an asynchronous clock signal multiplexing apparatus according to a preferred embodiment of the present invention with the above configuration will be described with reference to FIGS. 6 and 7 showing a timing diagram.

6 shows a clock conversion timing diagram when the first clock and the second clock are operating normally. Referring to FIG. 6, the operation of the asynchronous clock signal multiplexing apparatus when both the first clock and the second clock normally operate will be described.

Initially, when the first clock selection signal and the second clock selection signal are kept at the same level at the low level, the plug generator 50, which is a finite state machine, is in a '00' state. When the first clock selection signal changes to a high level, the plug generator detects this and shifts the state to a '01' state in synchronization with a subsequent first clock. In FIG. 6, it can be seen that the state '01' is maintained for one clock and automatically transitions to the state '10' at the next clock. In addition, as shown in FIG. 6, the first clock protection signal is changed to the low level while the state is transitioned to the '01' state.

The changed state and the changed first clock protection signal are input to the first asynchronous / synchronous signal generator 51, and the first asynchronous / synchronous signal generator 51 detects this and synchronizes with a second clock to thereby generate a second clock. The protection signal is changed to the low level and input to the safety flag generator 52 and the second clock signal regenerator 55. As shown in FIG. 6, when the second clock protection signal changes to a low level, the second clock signal regenerator outputs the same signal as the second clock and then changes to output a high level signal. In addition, the safety flag generator 52 detects this and then synchronizes with the next second clock to change the level of the first safety_flag signal from a high level to a low level and input it to the second asynchronous / synchronous signal generator 53. do.

The second asynchronous / synchronous signal generator 53 senses a change in the first safety flag flag level and when the first clock maintains the high level from the high level to the low level from the second safety flag flag level. Change. The change value of the second safety flag flag is input to the flag generator 50 and the first clock signal regenerator 54, and the flag generator 50 has both the first clock protection signal and the second safety flag flag low level. In this case, the second clock selection signal is changed to the high level in synchronization with the first clock, and the state is changed from the '10' state to the '00' state. In addition, the signal from the first clock signal regenerator is continuously maintained at a high level.

When the state of the plug generator 50 transitions to the '00' state, as shown in FIG. 6, the output clock signal at the multiplexer 56 becomes the same signal as the second clock, and is first generated at the first clock without glitch. You can see that it changes to 2 clocks. On the other hand, when the state of the flag generator 50 transitions to the '00' state, the first clock protection signal is changed back to the high level when the first clock is high level, and the second clock protection signal is synchronized to the second clock. The first safety flag flag detects that the second clock protection signal is changed to the high level, and is changed to the high level at the next second clock. The second safety flag flag is changed to the first safety signal. It is sensed that the flag signal is changed to a high level, and is changed to a high level when the first clock is at a high level.

7 illustrates a clock conversion timing diagram when the first clock operates normally but the second clock stops.

As shown in FIG. 7, when the first clock selection signal changes to a high level when the first clock signal operates normally and the second clock signal stops, the flag generator 50 once changes its state to that of FIG. 6. Similarly, the first clock protection signal is switched to the '01' state in synchronization with the first clock, and the first clock protection signal is converted to the low level. However, as shown in FIG. 7, since the second clock is not operating, the second clock protection signal does not change to a low level so that the first safety flag flag and the second safety flag flag do not change. do. In this state, the flag generator 50 switches the state from the '10' state to the '11' state, and does not perform a clock conversion operation to the second clock even when the first clock selection signal changes to a high level. The clock waits for operation.

When the second clock is operated again in the '11' state, the first asynchronous / synchronous signal generator 51 detects this and changes the second clock protection signal to a low level. In addition, the signal changed to the low level is input to the second clock signal regenerator 55, and the second clock regeneration signal is subsequently maintained at the high level. When the second clock protection signal changes to the low level, the safety flag generator 52 changes the first safety_flag signal to the low level in synchronization with the second clock. The second asynchronous / synchronous signal generator detects that the first safety_flag signal changes to a low level and changes the second safety_flag signal to a low level in a period where the first clock is at a high level. 50) and a first clock signal regenerator 54. The plug generator 50 that detects the change of the second safety_flag signal to the low level changes the first clock protection signal to the low level as shown in FIG. 7, and changes the state to '01' from the '11' state. Transition to state. As described above, the state of the finite state machine automatically transitions from the '01' state to the '10' state, and when the second safety_flag signal is detected at the low level in the '10' state, the flag is synchronized with the first clock. The state of the generator 50 transitions to the '00' state, the first clock protection signal changes to a high level, and the second clock selection signal changes to the same high level as the first clock selection signal value. Thereafter, the clock output of the multiplexer is converted to the second clock.

As described above, according to the asynchronous clock signal multiplexing apparatus of the present invention, the clock can be converted without generating a glitch, and has a safe mode to replace the clock with another clock even if one of the clocks does not operate. The advantage is that the clock can be provided reliably. Such a device could be useful for circuit design where clock continuity is important.

Claims (4)

In the asynchronous clock signal multiplexing apparatus for multiplexing different first clock signals and second clock signals, A flag generator which changes the first clock protection signal, detects a change in the safety_flag signal value, and changes the second clock selection signal when the first clock selection signal changes, and is a finite state machine; A first asynchronous / synchronous signal generator synchronized with the second clock to sense a change in the first clock protection signal and to change a second clock protection signal when the second clock is in operation; A safety flag generator for detecting a change in the second clock protection signal to change a first safety flag flag; A second asynchronous / synchronous signal generator which senses a change in the first safety flag signal to change a second safety_flag signal and inputs it to the flag generator to cause the flag generator to change a second clock selection signal; Synchronized by the first clock, and generates the same signal as the first clock in the normal state, and when the change of the first clock protection signal and the second safety_flag signal is detected, the high level until the return to the normal state A first clock signal regenerator for generating a signal of the first clock signal generator; And A second clock synchronized with a second clock and generating a signal equal to the second clock in a normal state, and generating a high level signal until returning to a normal state when detecting the change of the second clock protection signal; An asynchronous clock signal multiplexing device comprising a signal regenerator. The method of claim 1, And a first latch and a second latch coupled to the first asynchronous / synchronous signal generator and the second asynchronous / synchronous signal generator, respectively, to prevent a timing loop. The method of claim 1, The state of the flag generator, which is a finite state machine, is that the first clock protection signal changes after detecting a change in the first clock selection signal and a first state having the same state of the first clock selection signal and the second clock selection signal. And a third state which automatically transitions to maintain the protection signal in the second state, and a fourth state that transitions when the operation of the second clock is not detected in the second state. An asynchronous clock signal multiplexing device. The method of claim 1, And the flag generator and the second asynchronous / synchronous signal generator are synchronized by the first clock, and the safety flag generator is synchronized by a second clock.