KR950022074A - Transient elimination circuit and unnecessary switching prevention circuit during redundant clock switching - Google Patents

Transient elimination circuit and unnecessary switching prevention circuit during redundant clock switching Download PDF

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Publication number
KR950022074A
KR950022074A KR1019930030002A KR930030002A KR950022074A KR 950022074 A KR950022074 A KR 950022074A KR 1019930030002 A KR1019930030002 A KR 1019930030002A KR 930030002 A KR930030002 A KR 930030002A KR 950022074 A KR950022074 A KR 950022074A
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South Korea
Prior art keywords
clock
signal
control signal
transient
switching
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KR1019930030002A
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Korean (ko)
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KR960000128B1 (en
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이찬구
박상조
유강희
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양승택
재단법인 한국전자통신연구소
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

본 발명은 이중화 클럭 절체시 과도현상 제거회로 및 불필요한 절체방지회로에 있어서, 주 표준신호를 입력받아 제1클럭 및 제1PLL언록(UNLOCK)신호를 생성하는 제1클럭 발생기(21)와; 예비 표준신호를 입력받아 제2클럭 및 제2PLL언록신호를 생성하며 상기 제1클럭 발생기(21)와 클럭을 주고 받는 제2클럭 방생기(22)와; 외부클럭을 입력받되, 상기 제1클럭 발생기(21)에서 생성된 제1클럭, 제1PLL언록신호, 프리셀신호를 입력받아 제1제어신호를 생성하는 제1과도 현상 제거부(23)와; 외부클럭을 입력받되, 상기 제2클럭 발생기(22)에서 생성된 제2클럭, 제2PLL언록신호, 프리셀신호를 입력받아 제2제어신호를 생성하는 제2과도 현상 제거부(24)와; 상기 제1클럭발생기(21), 제1과도 현상 제거부(23) 각각에서 생성된 제1클럭, 제1제어신호를 입력받고, 상기 제2클럭발생기(22), 제2과도 현상 제거부(22) 각각에서 생성된 제2클럭, 제2제어신호를 입력받는 동기 복구 검출기(25)와; 상기 동기 복구 검출기(25)의 출력, 제1클럭, 제1제어신호, 제2클럭, 제2제어신호를 입력받아 클럭신호를 생성하는 클럭 절체부(26)를 포함하여 이루어 지는 것을 특징으로 한다.The present invention provides a transient cancellation circuit and unnecessary switching prevention circuit in a redundant clock switching, comprising: a first clock generator (21) for receiving a main standard signal and generating a first clock and a first PLL unlock signal; A second clock generator 22 configured to receive a preliminary standard signal to generate a second clock and a second PLL unlock signal, and to exchange a clock with the first clock generator 21; A first transient removal unit 23 configured to receive an external clock and receive a first clock, a first PLL unlock signal, and a free cell signal generated by the first clock generator 21 to generate a first control signal; A second transient removal unit 24 configured to receive an external clock and receive a second clock, a second PLL unlock signal, and a free cell signal generated by the second clock generator 22 to generate a second control signal; A first clock and a first control signal generated by each of the first clock generator 21 and the first transient removing unit 23 are received, and the second clock generator 22 and the second transient removing unit ( 22) a sync recovery detector 25 for receiving a second clock and a second control signal generated in each of the two clocks; And a clock switching unit 26 configured to generate a clock signal by receiving the output of the synchronous recovery detector 25, a first clock, a first control signal, a second clock, and a second control signal. .

Description

이중화 클럭절체시 과도현상 제거회로 및 불필요한 절체방지회로Transient elimination circuit and unnecessary switching prevention circuit during redundant clock switching

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 이중화 클럭절체 블록도.1 is a conventional redundant clock switching block diagram.

제2도는 본 발명에 따른 이중화 클럭절체 블록도.2 is a redundant clock switching block diagram according to the present invention.

제3도는 제2도의 상세회로도.3 is a detailed circuit diagram of FIG.

제4도는 제3도의 각부 파형도.4 is a waveform diagram of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,2,21,22 : 클럭발생기 3 : 클럭분배기1,2,21,22: Clock generator 3: Clock divider

23,34 : 과도현상 제거부 25 : 동기복구 검출기23,34: transient removal unit 25: synchronous recovery detector

26 : 클럭절체부26: clock switching unit

Claims (1)

이중화 클럭절체시 과도현상 제거회로 및 불필요한 절체방지회로에 있어서, 주표준신호를 입력받아 제1클럭 및 제1PLL 언록(UNLOCK)신호를 생성하는 제1클럭발생기(21)와; 예비표준신호를 입력받아 제2클럭 및 제2PLL 언록신호를 생성하며 상기 제1클럭발생기(21)와 클럭을 주고받는 제2클럭발생기(22)와; 외부클럭을 입력받되, 상기 제1클럭발생기(21)에서 생성된 제1클럭, 제1PLL 언록신호, 프리신호를 입력받아 제1제어신호를 생성하는 제1과도 현상 제거부(23)와; 외부클럭을 입력받되, 상기 제2클럭발생기(22)에서 생성된 제2클럭, 제2PLL 언록신호, 프리신호를 입력받아 제2제어신호를 생성하는 제2과도현상 제거부(24)와; 상기 제1클럭발생기(21), 제1과도현상 제거부(23) 각각에서 생성된 제1클럭, 제1제어신호를 입력받고, 상기 제2클럭발생기(22), 제2과도현상 제거부(22) 각각에서 생성된 제2클럭, 제2제어신호를 입력받는 동기복구검출기(25)와; 상기 동기복구검출기(25)의 출력, 제1클럭, 제1제어신호, 제2클럭, 제2제어신호를 입력받아 클럭신호를 생성하는 클럭절체부(26)를 포함하여 이루어지는 것을 특징으로 하는 이중화 클럭절체시 과도현상 제거회로 및 불필요한 절체방지회로.A transient clock removal circuit and an unnecessary switching prevention circuit in a redundant clock switching, comprising: a first clock generator 21 for receiving a main standard signal and generating a first clock and a first PLL unlock signal; A second clock generator 22 which receives the preliminary standard signal to generate a second clock and a second PLL unlock signal and exchanges a clock with the first clock generator 21; The external clock is input, but the first clock, the first PLL unlock signal, and the free signal generated by the first clock generator 21 are free. A first transient removing unit 23 receiving a signal and generating a first control signal; The external clock is input, but the second clock, the second PLL unlock signal, and the free signal generated by the second clock generator 22 are free. A second transient phenomenon removing unit 24 receiving a signal and generating a second control signal; The first clock generator 21 receives the first clock and the first control signal generated by each of the first clock generator 21 and the first transient phenomenon removing unit 23, and the second clock generator 22 and the second transient phenomenon removing unit ( 22) a synchronous recovery detector 25 for receiving the second clock and the second control signal generated in each of the two; And a clock switching unit 26 configured to receive the output of the synchronous recovery detector 25, the first clock, the first control signal, the second clock, and the second control signal to generate a clock signal. Transient elimination circuit and unnecessary transfer prevention circuit during clock switching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930030002A 1993-12-27 1993-12-27 Transition rid of circuit KR960000128B1 (en)

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KR1019930030002A KR960000128B1 (en) 1993-12-27 1993-12-27 Transition rid of circuit

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KR1019930030002A KR960000128B1 (en) 1993-12-27 1993-12-27 Transition rid of circuit

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KR950022074A true KR950022074A (en) 1995-07-26
KR960000128B1 KR960000128B1 (en) 1996-01-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100310232B1 (en) * 1999-03-25 2001-10-29 박종섭 Method for clock selecting according to first order

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328761B1 (en) * 1999-09-17 2002-03-15 서평원 A device of switching system clock unit for optical communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100310232B1 (en) * 1999-03-25 2001-10-29 박종섭 Method for clock selecting according to first order

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