KR970024375A

KR970024375A - An apparatus for synchronizing system clock to network in a digital exchanger

Info

Publication number: KR970024375A
Application number: KR1019950038859A
Authority: KR
Inventors: 성도상
Original assignee: 유기범; 대우통신 주식회사
Priority date: 1995-10-31
Filing date: 1995-10-31
Publication date: 1997-05-30

Abstract

본 발명은 상위국으로부터 T1 혹은 E1 라인으로 비트 스트림을 입력 받아 망동기 기준클럭을 재생하는 트렁크장치(21)와 ; 상기 트렁크장치(21)를 통해 입력된 망동기 기준 클럭에 동기된 시스템 동기클럭을 발생하는 클럭발생부(22) ; 및 상기 클럭발생부(22)에서 발생된 클럭을 입력받아 소정의 클럭과 프레임 펄스를 발생하는 스페이스 스위치 및 중앙링크부(23)로 구성되어 클럭을 일괄처리하므로써 신뢰성을 향상시킬수 있다.The present invention provides a trunk apparatus 21 for receiving a bit stream from a higher station to a T1 or E1 line and reproducing a network synchronizer reference clock; A clock generator 22 for generating a system synchronization clock synchronized with the network synchronizer reference clock inputted through the trunk apparatus 21; And a space switch and a center link unit 23 which receive a clock generated by the clock generator 22 and generate a predetermined clock and frame pulse, thereby improving reliability by collectively processing clocks.

Description

An apparatus for synchronizing system clock to network in a digital exchanger

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 동기장치를 도시한 블럭도이다.2 is a block diagram showing a synchronization device according to the present invention.

Claims

A trunk apparatus 21 for receiving a bit stream from an upper station to a T1 or E1 line and reproducing a network synchronizer reference clock; A synchronization device including a clock generator 22 for generating a basic clock synchronized with the network synchronizer reference clock inputted through the trunk device 21; And a space switch and a central link unit 23 which receive a basic clock from the synchronizer and multiply and divide the clock to generate a plurality of clocks and frame pulses required by the system. And generating only a clock, and generating a clock required by the system from the space switch and the central link unit which have received the basic clock.

The synchronization device of claim 1, wherein the synchronization device of the digital electronic switching device is configured to improve the reliability of the clock by minimizing the multi-level PLL since the clock generator generates only basic clicks.

※ Note: The disclosure is based on the initial application.