KR970049270A

KR970049270A - Interface device for switching between synchronous clock sources

Info

Publication number: KR970049270A
Application number: KR1019950067834A
Authority: KR
Inventors: 최민선
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-30
Filing date: 1995-12-30
Publication date: 1997-07-29

Abstract

1.청구 범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

인터페이스장치에 관한 것이다.It relates to an interface device.

2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve

절체경보발생을 체크한 프로세서에 의해 제어되어 간단하게 클럭발생부가 동기원 클럭을 절체할 수 있도록 하는 동기원클럭의 절체를 위한 인터페이스장치를 제공한다.Provided is an interface device for switching the synchronization source clock that is controlled by a processor that checks the switching alarm occurrence so that the clock generator can switch the synchronization clock.

3.발명의 해결방법의 요지3. Summary of the solution of the invention

상위프로세서나 종속장치의 경보를 체크하여 절체제어신호를 발생하는 프로세서와, 동기원기준클럭을 클럭원으로 하여 클럭을 발생하는 클럭발생부와,상기 프로세서에 의해 제어되며,상기 프로세서와 상기 클럭발생부 사이에 위치하여 인터페이스기능을 하는 라인인터페이스장치는 상기 프로세서의 절체제어신호를 입력하여,경보발생에 의해 상기 절체제어신호가 활성화일 시 클럭절체신호를 발생하는 클럭절체신호발생부와,상기 클럭절체발생부의 출력 및 수신되는 수신기준클럭을 입력하며,상기 클럭절체신호가 입력될 시 상기 클럭절체신호를 상기 클럭발생부에 출력하여 클럭을 절체시킬 수 있도록 하며,상기 클럭절체신호가 입력되지 않을 시 상기 수신기준클럭을 동기원기준클럭으로 출력하는 동기원기준클럭발생부로 구성한다.A processor for generating a switching control signal by checking an alarm of an upper processor or a slave device, a clock generator for generating a clock using the synchronization source reference clock as a clock source, and controlled by the processor, the processor and the clock generation The line interface device located between the units and having an interface function may include a clock transfer signal generation unit configured to input a transfer control signal of the processor to generate a clock transfer signal when the transfer control signal is activated by an alarm generation; Inputs the output of the transfer generator and the received reference clock, and when the clock transfer signal is input, outputs the clock transfer signal to the clock generator to switch the clock, and the clock transfer signal is not input. And a synchronization source reference clock generator for outputting the reception reference clock to the synchronization source reference clock.

4.발명의 중요한 용도4. Important uses of the invention

프로세서가 절체경보를 체크하여 간단하게 동기클럭원을 절체시키도록 하기 위해 이를 구현한다.Implement this to allow the processor to simply check the switchover alarm and switch the sync clock source.

Description

Interface device for switching between synchronous clock sources

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명을 수행하기 위한 동기클럭원의 절체를 위한 장치의 시스템블럭도를 도시한 도면.1 shows a system block diagram of an apparatus for switching a synchronization clock source for carrying out the present invention.

제2도는 본 발명에 따른 동기클럭원의 절체를 위한 인터페이스 장치의 구성도를 도시한 도면.2 is a diagram illustrating a configuration of an interface device for switching a synchronization clock source according to the present invention.

Claims

A processor for generating a switching control signal by checking an alarm of an upper processor or a slave device, clock generation means for generating a clock using a synchronous reference clock as a clock source, controlled by the processor, and generating the processor and the clock A line interface device positioned between the means and having an interface function, comprising: a clock switching signal generating means for inputting a switching control signal of the processor to generate a clock switching signal when the switching control signal is activated by an alarm; Inputting the output of the clock switching signal generating means and a receiving reference clock received; and outputting the clock switching signal to the clock generating means when the clock switching signal is input to switch the clock; Number of synchronization source reference clocks that output the reception reference clock to the synchronization source reference clock when is not input Interface device for the transfer of the synchronization source clock source, characterized by consists of.

※ Note: The disclosure is based on the original application.